ankaya University, Faculty of Engineering and Architecture

Department of Computer Engineering

CENG 222 Computer Organization (Spring Semester 2008/2009)
Final June 11, 2009

Solutions

Student Name______________________________________
Faculty No: _______________________________________
1. Early examples of CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set
Computer) are the VAX 11/780 and the IBM RS/6000, respectively. Using a typical benchmark program,
the following machine characteristics result:
Processor
VAX 11/780
IBM RS/6000

Clock Frequency
5 MHz
25 MHz

Performance
1MIPS
18 MIPS

CPU time
12 x seconds
x seconds

The final column shows that the VAX required 12 times longer than the IBM measured in CPU time.
a). What is the relative size of the instruction count of the machine code for this benchmark program
running on the two machines?
Solution:
We can express the MIPs rate as: [(MIPS rate)/106] = Ic/T.
So that:
Ic = T [(MIPS rate)/106].
The ratio of the instruction count of the RS/6000 to the VAX is
[x 18]/[12x 1] = 1.5.

b). What are the CPI (Cycles Per Instruction) values for the two machines?
Solution:
For the Vax, CPI = (5 MHz)/(1 MIPS) = 5.
For the RS/6000, CPI = 25/18 = 1.39.

2. Consider a system employing interrupt-driven I/O for a particular device that transfers data at an
average of 8000 times per second on a continuous basis.
a). Assume that interrupt processing takes about 100 s (i.e., the time to jump to the interrupt service
routine (ISR), execute it and return to the main program). Determine what fraction of processor time this
I/O device consumes if it interrupts for every byte.
Solution:
The device generates 8000 interrupts per second or a rate of one every
125 s. If each interrupt consumes 100 s, then the fraction of
processor time consumed is 100/125 = 0.8

b). Now assume that the device has two 16-byte buffers and interrupts the processor when one of the
buffers is full. Naturally, interrupt processing takes longer, because the ISR must transfer 16 bytes. While
executing the ISR, the processor takes about 8 s for transfer of each byte. Determine what fraction of
processor time this I/O device consumes in this case.
Solution:
In this case, the time interval between interrupts is 16 125 =
s. Each interrupt now requires 100 s for the first character
the time for transferring each remaining character, which adds up
15 = 120 s, for a total of 220 s. The fraction of processor
consumed is 220/2000 = 0.11

2000
plus
to 8
time

c). Now assume that the processor, in addition to b), is equipped with a block transfer I/O instruction.
This permits the associated ISR to transfer each byte of a block in only 2 s. Determine what fraction of
processor time is consumed by this I/O device in this case.
Solution:
The time per byte has been reduced by 6 s, so the total time
reduction is 16 6 = 96 s. The fraction of processor time consumed
is therefore (220 96)/2000 = 0.062. This is an improvement of almost
a factor of 2 over the result from part (b).

3. Consider two microprocessors having 16- and 32-bit-wide external data buses, respectively. The two
processors are identical otherwise and their bus cycles take just as long.
a). Suppose all instructions and operands are four bytes long. By what factor do the maximum data
transfer rates differ?
Solution:
During a single bus cycle, the 16-bit microprocessor transfers two
bytes while the 32-bit microprocessor transfers four bytes. The 32-bit
microprocessor has twice the data transfer rate.
b). Repeat assuming that half of the operands and instructions are two bytes long.
Solution:
Suppose we do 100 transfers of operands and instructions, of which 50
are two bytes long and 50 are four bytes long. The 16-bit
microprocessor takes 50 + (2 x 50) = 150 bus cycles for the transfer.
The 32-bit microprocessor requires 50 + 50 = 100 bus cycles. Thus, the
data transfer rates differ by a factor of 1.5.

4. Consider a single-platter hard disk with the following parameters: rotation speed 7200 rpm (revolutions
per minute); number of tracks on one side of platter: 30,000; number of sectors per track: 600; seek time:
one ms for every hundred tracks traversed. Let the disk receive a request to access a random sector and
assume the head starts at track 0.
a). What is the average seek time?
Solution:
If we assume that the head starts at track 0, then the calculations
are simplified. If the request track is track 0, then the seek time is
0; if the requested track is track 29,999, then the seek time is the
time to traverse 29,999 tracks. For a random request, on average the
number of tracks traversed is 29,999/2 = 14999.5 tracks. At one ms per
100 tracks, the average seek time is therefore 149.995 ms.
b). What is average rotation latency (delay)?
Solution:
At 7200 rpm, there is one revolution every 8.333 ms. Therefore the
average rotational delay is 4.167 ms.

c). What is the transfer time for a sector?

Solution:
With 600 sectors per track and the time for one complete revolution of
8.333 ms, the transfer time for one sector is 8.333 ms/600 = 0.01389
ms.
d). What is the total average time to satisfy a request?
Solution:
The result is the sum of the preceding quantities, or approximately
154 ms.

5. A no pipelined processor has a clock rate of 2.5 GHz and an average CPI (Cycles Per Instruction) of 4.
An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays,
such as latch delay, the clock rate of the new processor has to be reduced to 2 GHz.
a). What is the speedup achieved for a typical program (of 100 instructions)?
Hint: To calculate speedup use equation S = (nk)/[k + (n 1)], where S speedup, n number of
instructions in program, k number of stages in pipeline.
Solution:

Using equation, we can calculate the speedup of the pipelined 2-GHz

processor versus a comparable 2- GHz processor without pipelining:
S = 500/104 = 4.8
However, the unpipelined 2-GHz processor will have a reduced speed of
a factor of 0.8 compared to the 2.5-GHz processor. So the overall
speedup is
4.8 0.8 = 3.8.

b). What is the MIPS (Million Instructions Per Second) rate for each processor?

For the first processor, each instruction takes 4 clock cycle, so the
MIPS rate is 2500 MHz/4 = 625 MIPS. For the second processor,
instructions are completed at the rate of one per clock cycle, so that
the MIPS rate is 2000 MIPS.

6. Assembly language.
a). Write and briefly explain the function of instructions in each row. Write ERROR if the instruction is
an illegal instruction. Explain why it is illegal.
Instruction

Function

movax,1234

ax=1234(Example)

addcx,5

cx=cx+5;Add5toCX.

incbl

bl=bl+1;Incrementblby1.

xorax,ax

ax=axxorax;XORaxbyitself.
axwillbe0.

subbx,10h

bx=bx16;subtract16(=10h)frombx.

cmpdl,7

Settheflagswithrespecttotheresultof
operation(dl7).

movdl,1BEAh

ERROR.Thevalue1BEAhcannotfitinto8bit
registerdl.

jgeLABEL

Jumpiftheresultofthelastinstructionis
positiveorzero.

int10h

Callinterruptserviceroutine10h.

andcx,dl

ERROR.Sizeofcxanddlarenotequal.

ret

Returntothecallerfunction.

b). The loop between the labels L1 and L2 in the given code below is supposed to be executed 15 times.
But there is a flaw in the code so that it loops forever. Find the mistake and propose a solution to the
problem. Re-write the corrected version of the code.
Incorrect code:
mov dx, 2
xor ax, ax
L1:
inc ax
mul dx
testax,8000h
jzL1
L2:

Corrected code:
mov bx, 2
xor ax, ax
L1:
inc ax
mul bx
testax,8000h
jzL1
L2:

c). Write a piece of assembly code to exchange 4-bit nibbles of AL register. You can use any register to
store data.
Example:
If AL = 0101 1110, then the result should be AL = 1110 0101.
AL = 0101 1110

AL = 1110 0101
Write your code below:
mov bl, 16
mov dl, al
and dl, 0F0h
mov ah, 0
mul bl
mov dh, al
mov al, dl
mov ah, 0
div bl
or al, dh

All questions are equally weighted

Good luck!