On Improvement of Bus-Invert Coding for

Low-Power I/O
Mohammed Alamgir

Iftekhar Ibne Basith

Tareq Supon

School of Electrical Engineering

University of Windsor
Windsor, ON, Canada
Email: alamgirm@uwindsor.ca

School of Electrical Engineering

University of Windsor
Email: basithi@uwindsor.ca

School of Electrical Engineering

University of Windsor
Email: supon@uwindsor.ca

AbstractIn low-power VLSI design good amount of power

can be saved by using coding scheme such as Bus-Invert (BI).
Such a coding scheme looks at successive words on a data bus and
applies transformation to minimize the number of transitions.
In this paper, we propose a new coding scheme that circularly
shifts the data on a bus to attain even better power saving.
While the performance of BI deteriorates with wider bus width
present scheme performs better both in maximum and average
power cases. Simulation results are reported to show the proposed
method is about 10% better at power saving.
Index Termslow-power, bus-invert, bus-shifting, activity factor.

I. I NTRODUCTION
With the widespread adoption of portable devices CMOS
VLSI chip design employs significant efforts in reducing
power dissipation. In a CMOS chip, the majority of power is
dissipated in load capacitance due to logic transitions, known
as dynamic power. The other components of power dissipation
are static power and leakage power both of which are either
less dominant or technology dependent [1]. The dynamic
power dissipated by a chip is given by
Pdyn =

N
X

2
CLi Vdd
fCLK i

(1)

i=1

where the sum is taken over all the nodes N of the chip, Vdd is
the supply voltage, and for node i, CLi is the load capacitance
being driven by the node with an activity factor of i ; fCLK
is the chip clock frequency.
In quest for reducing the dynamic power, Vdd is an important choice because of its quadratic effect. But Vdd cannot be
arbitrarily lowered because of the required threshold voltages
of nMOS and pMOS transistors. Unused portion of a chip is
commonly switched off by turning the clock off (setting fCLK
to zero.) The load capacitance is generally the gate capacitance
of transistors and limited by the fabrication technology used.
So, reducing the activity factor has good merit in reducing
overall power consumption of a VLSI chip.
In chip floor-planning the core pins are connected to the
outside world via I/O pads. These I/O pads, connections to
them, and in general the connection outside of the chip pose
significant capacitive load and consumes as much as 80% [2],
and on average 50% of total power [3]. Depending on the

specific characteristics of the information being transferred

(for example, program instructions, memory addresses) there
are techniques reported in the literature [4][5][6]. When the
information on wires is considered randomly distributed, Businversion [7] is a very simple and elegant approach to minimize the activity factor. It has been reported to reduce the
peak power by 50% and average power by as much as 25%.
The dismal average power saving inspired modifications of BI
such as [8] and [9]. Such modifications, for example involves
complex partitioning, based on the activity factor of each line.
We present a modification to the scheme, called Bus Shifting
(BS) where the word to be transmitted is shifted in a circular
manner so that word to word transitions are reduced, and hence
the the average power dissipation is improved.
The rest of the paper is organized as followed: Section
II discusses bus invert scheme and highlights its weakness,
Section III introduces bus shifting scheme and Section IV
presents it superiority over bus inversion. Concluding remarks
are given in Section V.
II. B US -I NVERT C ODING
Consider a n-bit bus carrying uniformly distributed random
data. The current word on the bus is curWord while the next
word is nextWord. There is also a line called invert to denote
whether the data on the bus has been inverted nor not so that
the receiver can act properly. (Though the terms current and
next seem little confusing, we stick to them to conform to the
original paper [7].)
The bus-invert coding works as follows:
Compute the hamming distance between curWord and
nextWord.
If the distance is greater than n/2, invert nextWord and
send the inverted word on bus. Set invert to 1.
Otherwise, send the nextWord as is, and set invert to 0.
A receiver first looks at the invert line and if 1 takes an
inverted value of the data found on the bus.
The bus-invert coding scheme alters the hamming distance
between successive words by inverting words with large distance. If the probability distribution of the hamming distances
are plotted the effect is right half of the distribution is folded
back to the left half. In practice, words with larger hamming

0.35

0.3

0.3

0.25

0.25

Probability

Probability

0.35

0.2

0.15

0.1

0.05

0.05

Fig. 1.

3
4
5
Hamming distance

Distribution of hamming distance for original data.

0.3

Probability

0.25
0.2
0.15
0.1
0.05

Fig. 2.

2
3
Hamming distance

Distribution of hamming distance for bus-invert encoded data.

distances are coded back to lower distances. Fig. 1 and Fig. 2.

While the large-distance words are modified, BI does not
touch words in the middle of the distribution which represents
the most of the data transmission. The consequence is that on
the average, when the hamming distance is about n/2, the BI
coding does not attempt to alter the word.
III. B US -S HIFT C ODING
We propose to shift the data word on a bus to get minimum
transitions. For simplicity, we use only left-shift but in a
circular manner. Given curWord and nextWord, to determine
how many bits of nextWord to shift we do the following:

Fig. 3.

4
5
Hamming distance

Distribution of hamming distance for bus-shift encoded data.

A. Example of Bus-Shift

0.35

0.4

0.15

0.1

0.2

For i = 1 to n shift nextWord on left by i-bit and compute

hamming distance between the shifted word and curWord.
Let hmin denotes the number of bits that result in
minimum hamming distance.
Shift nextWord by hmin bits, transmit the shifted word.
Send hmin as a binary number on the control lines.

Consider curWord= 01100010 and nextWord= 00100110,

where the hamming distance is 2. The bus-shift algorithm
will find that nextWord can be shifted on the left by 4-bits
to achieve 01100010 which would result in zero hamming
distance when compared to curWord. Bus-shift scheme will
transmit this shifted word as nextWord and along with that
send 100 on the control lines.
If we used bus-invert, it would have transmitted the same
word as the hamming distance is 2 which is lower than 4.
From this example it might appear that bus-shift would
not attain any significant improvement. We explore another
example where the data words are chosen so that the hamming
distance is 4, the most likely case for 8-bit bus.
Consider curWord= 10110110 and nextWord= 01101111;
the hamming distance being 4. As the distance does not exceed
4(n/2 for b-bit bus), bus-invert scheme will not do anything.
However, our scheme will figure out that shifting the word by
7-bit on the left (or equivalently 1-bit to the right) will give
a hamming distance of 0. We then transmit 7 = 111 on the
control lines.
B. Probability Distribution
The effect of shifting a word on hamming distance is difficult to analyze analytically. We followed the same numerical
approach as [7] and plot the probability distribution in Fig. 3.
It is interesting to note that the probability distribution has not
changed much when compared to Fig. 1.
IV. S IMULATION R ESULTS
The weakest point of BI coding is that the power saving
gets worse for wider bus. As a modern chip usually has few
hundred I/O pins we are interested to see how bus-shifting
works for wider bus. For this experiment, we setup both of
the coding schemes for varying bus widths and fed with same
uniformly distributed random data. The result is shown in
Fig. 4. On the same figure we also plot two horizontal lines
that represent 4-bit and 8-bit fixed sub-grouping respectively.

0.44

0.44
Bus Invert
Bus Shift

0.42

0.4

0.41

0.38

n=8

0.4
0.39
0.38

n=4

Bus Invert
Bus Shift

0.42

Transition probability

Transition probability

0.43

0.36
0.34
0.32
0.3

0.37

0.28

0.36

0.26

0.35
0.24

0.34

Fig. 4.

200

400

600
Bus width

800

1000

500

1000

1500

1200

Transition probability for bus-invert and bus-shift coding.

2000 2500
Bus width

3000

3500

4000

4500

Fig. 5. Asymptotic transition probability for bus-invert and bus-shift coding.

0.5
0.45
0.4
Ratio of control bits/bus width

It has been reported in [main paper] that the transition

probability for bus-invert approaches 0.43 when the width of
the bus gets wider. In our experiment, this is found to be 0.427,
and found at n = 256 or higher.
Our proposed bus-shift coding performs no better than the
bus-invert for N = 4 and n = 8. This is because the overhead
for the control lines is just too high. To be specific, 2 control
lines for n = 4 means 50% overhead; 3 control lines for n = 8
means 37% overhead.
However, bus-shift coding performs best for n = 32, and
almost the same for n = 64. This corresponds to transition
probability of 0.345, about 69% of un-coded power level. For
bus-invert coding, this approximately 83%; 14% higher than
bus-shift coding.
For bus width larger than 64, the power saving starts to wear
off, but it is still about 10% better than bus-invert coding. For
example, n = 512 has a transition probability of 0.377 which
represents 75.4% of un-coded power. For bus-invert coding,
this is 85.4%.
Being interested in asymptotic performance of the bus-shift
coding scheme we further increase the bus width and plot
the results in Fig. 5. It appears that the asymptotic transition
probability approaches about 0.4 which represents 80% of
uncoded power level. In contrast, the bus-invert coding tends
towards 0.43, or 86% of uncoded power level. In asymptotic
sense we could expect to achieve 6% better power saving when
compared to bus-invert coding.
The number of extra control lines required could be a
concern. For instance, for smaller bus width, such as 4 or
8, the control lines pose a significant overhead. However, as
the bus size grows the overhead diminishes quickly. In Fig. 6
we plot the ratio log2 n/n, which represents the overhead as a
fraction of original bus width. It is evident that for a moderate
width of n = 1024 the overhead is less than 1%. Therefore
the additional capacitance added by the control lines are not
significant.

0.35
0.3
0.25
0.2
0.15
0.1
X: 1024
Y: 0.009766

0.05
0

Fig. 6.

500

1000

1500

2000 2500
Bus width

3000

3500

4000

4500

Control line overhead as a fraction of bus width.

V. C ONCLUSION
Bus-invert is a simple coding scheme to reduce dynamic
power dissipation in a data bus by conditionally inverting the
word. We propose a new scheme that attempts to reduce power
by shifting the word in a circular manner. Simulation results
show that the proposed scheme can do about 10-14% better
than the bus-invert scheme when considering average power.
Also, unlike bus-invert power saving of our scheme does not
deteriorate as fast with wider bus.
R EFERENCES
[1] H. Veendrick, Short-Circuit Dissipation of Static CMOS Circuitry and
its Impact on the Design of Buffer Circuits, IEEE Journal of Solid-State
Circuits, Vol. SC-19, no. 4, pp.468473, 1984.
[2] C. A. Neugebauer and R. O. Carlson, Comparison of wafer scale integration with VLSI packaging approaches, IEEE Transaction on Components,
Hybrids, and Manufacturing Technology, pp. 184-189, June 1987.
[3] R. Wilson, Low power and paradox, Electronic Engineering Times, pp.
38, Nov. 1, 1993.
[4] C. L. Su, C. Y. Tsui, and A. M. Despain, Saving power in the control
path of embedded processors, IEEE Design and Test of Computers, vol.11,
no.4, pp.24-30, 1994.

[5] L. Benni, G. De Micheli, E. Macii, D. Scivto, and C. Silvano, Asymptotic zero-transition activity encoding for address buses in low-power
microprocessor-based systems, Proceedings of Grate Lakes Symposium
on VLSI, pp.71-82, 1997.
[6] L. Benni, G. De Micheli, E. Macii, M. Poncino, and S. Quer, System level
power optimization of special purpose applications, the beach solution,
Proceedings of International Symposium on Low Power Electronics and
Design, pp.24-29, 1997.
[7] M. R. Stan and W. P. Burleson, Bus-invert coding for low-power I/O,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
Volume: 3, Issue: 1, DOI: 10.1109/92.365453, Publication Year: 1995,
Page(s): 49-58.
[8] U. Narayanan, K. Chung and T. Kim, Enhanced bus invert encodings
for low-power, IEEE International Symposium on Circuits and Systems
(ISCAS), DOI: 10.1109/ISCAS.2002.1010631 Publication Year: 2002 ,
Page(s): V25-V28, Volume-5.
[9] S. Hong, U. Narayanan, K. Chung and T. Kim, Bus-invert coding for
low-power I/O - a decomposition approach, Proceedings of the 43rd
IEEE Midwest Symposium on Circuits and Systems, DOI: 10.1109/MWSCAS.2000.952865, Publication Year: 2000, Page(s): 750-753, Volume-2.