Sie sind auf Seite 1von 50

1

Mailam Engineering College


(Approved by AICTE, New Delhi, Affiliated to Anna University, Chennai
& Accredited by National Board of Accreditation (NBA), New Delhi)

Mailam (Po), Villupuram (Dt). Pin: 604 304


DEPARTMENT OF COMPUTER APPLICATIONS
Computer Organization MC9211
UNIT V

MEMORY AND I/O SYSTEM

Memory technology Memory systems Virtual memory Caches Design methods


Associative memories Input / Output system Programmed I/O DMA and Interrupts
I/O Devices and Interfaces.

Part A
1. What is memory system?
Every Computer contains several types of devices to store the instructions and data
for its operation. These storage devices plus the algorithm implements by hardware and
software needed to manage the stored information from the memory system of computer.
2. Give the classification of memory
CPU Register
Main memory
Secondary Memory
Cache memory.
3. Define Static Memories and Dynamic Memories.
Memories that consist of circuits capable of retaining their state as long as power is
applied are knowns static memories. In Dynamic Memories such cells do not retain their
state indefinitely.
4. What is read access time?
A basic performance measure is the average time to read a fixed amount of
information for instance, one word from the memory. This parameter is called the read
access time.
5. Define RAM
In storage location can be accessed in any order and access time is independent of
the location being accessed, the memory is termed as random access memory.
6. What is ROM?
Memories whose content cannot be altered online if they can be altered at all are
read only memories.
7. What are PROMs?
Semi conductor ROMs whose contents can be changed offline-with some difficulties is called
PROMs.

Prepared By
Mrs. V.Rekha AP / MCA

2
8. What is SRAM AND DRAM?
SRAM: Static random access memory. It tends to be faster. They require no refreshing.
DRAM: Dynamic random access memory. Data is stored in the form of charges. So
continuous refreshing is needed.
9. What is volatile memory?
A memory is volatile if the loss of power destroys the stored information. Information
can be stored indefinitely in a volatile memory by providing battery backup or other means
to maintain a continuous supply of power.
10. What are the categories of memories,
SRAM
DRAM
11. What is flash memory?
A recent semiconductor technology called flash memory of a same non-volatility as a
PROM, but it can be done a bit at a time.
12. What is cache memory and write an advantage of using cache memory?
[JAN 2012]
Memory word are stored in cache data memory and are grouped into small pages
called cache blocks or line. The contents of the caches data memory are thus copies of a
set of main memory blocks. Used to increase the speed and performance during memory
access.
13. Mention two system organizations for caches.
Two system organizations for caches are
Look aside
Look through
14. What is RAMBUS memory?
The key feature of RAMBUS technology is a fast signaling method used to transfer
information between chips using narrow bus. Instead of using signals that have voltage
levels of either 0 or V supply to represent the logic values, the signals consist of much
smaller voltage swings around a reference voltage, vref. Small voltage swings make it
possible to have short transition times, which allows for a high speed of transmission.
15. What is write-through protocol?
For write operation, the cache location and the main memory location are updated
simultaneously.
16. Give the difference between EEPROM and Flash memory?
The primary difference between EEPROM and flash memory is that flash restricts
writes to multiple kilobytes blocks, increasing the memory capacity per chip by reducing
area of control.
17. Differences between cache memory and virtual memory
In caches, replacement is primarily controlled by the hardware. In VM, replacement is
primarily controlled by the OS.
The Number of bits in the address determines the size of VM, where as cache size is
independent of the address size.
But there is only one class of cache.

Prepared By
Mrs. V.Rekha AP / MCA

3
18. Uses of Virtual Memory.
Protection: VM is often used to protect one program from others in the system Base
and Bounds: this method allows relocation. User processes cannot be allowed to change
these registers, but the OS must be able to do so on a process switch.
19. Interleaved Memory.
Banks of memory are often one word wide, so bus width need not be changed to
access memory. However several independent areas of memory can be accessed
simultaneously by using interleaved memory.
20. What is write back protocol?
In this scheme, only the block in cache is modified. The main memory when the
block must be replaces in the cache. This requires the use of a dirty bit to keep track of
blocks, that have been modified.
21. Define the term interrupt. [JAN 2012]?
The interrupt is a task used to perform specific operation. Set of instructions which is
invoked by interrupt is called interrupt service routine [ISR]. Generally is classified as
hardware and software interrupt.
22. What is the function of ALU & CU?
Most of the computer operations (arithmetic and logic) are performed in ALU. The
data required for the operation is brought by the processor and the operation is performed
by the ALU.
The control unit acts as the nerve center, which coordinates all the computer
operations. It issues timing signals that governs the data transfer.
23. What are basic operations of a computer?
The basic operations are READ and WRITE.
24. What are the registers generally contained in the processor?
MAR-Memory Address Register
MDR-Memory Data Register
IR-Instruction Register
R0-Rn-General purpose Registers
PC-Program Counter
25. What is the use of buffer register?
The buffer register is used to avoid speed mismatch between the I/O device and the
processor.
26. What is the maximum size of the memory that can be used in a 16-bit
computer and 32 bit computer?
The maximum size of the memory that can be used in a 16-bit computer is 216=64K
memory locations. The maximum size of the memory that can be used in a 32-bit computer
is 232 =4G memory locations.
27. Define memory access time & memory cycle time?
The time required to access one word is called the memory access time. Or it is the
time that elapses between the initiation of an operation and the completion of that
operation.

Prepared By
Mrs. V.Rekha AP / MCA

4
It is the minimum time delay required between the initiations of two successive
memory operations. Eg. The time between two successive read operations.
29. When is a memory unit called as RAM?
A memory unit is called as RAM if any location can be accessed for a read or writes
operation in some fixed amount of time that is independent of the locations address.
30. What is MMU?
MMU is the Memory Management Unit. It is a special memory control circuit used for
implementing the mapping of the virtual address space onto the physical memory.
31. Define memory cell & Word line?
A memory cell is capable of storing one bit of information. It is usually organized in
the form of an array. In a memory cell, all the cells of a row are connected to a common line
called as word line.
32. How will you handle multiple interrupts? [JUN 2012]
When the processor is being processing an interrupt, the processor ignores any new
interrupt signal and these new signals have to wait in a queue and processor will check after
the currently processing interrupt is finished. Each interrupt has a priority value. When the
processor is being executing an interrupt, another interrupt can interrupt and gain the
processor if the second interrupt has a higher priority than first one
33. Define static memories?
A memory that consists of circuits capable of retaining their state as long as power is
applied is called Static memories.
34. What are the Characteristics of semiconductor RAM memories?
They are available in a wide range of speeds.
Their cycle time range from 100ns to less than 10ns.
They replaced the expensive magnetic core memories.
They are used for implementing memories.
35. Why SRAMs are said to be volatile & its characteristics?
Because their contents are lost when power is interrupted. So SRAMs are said to be
volatile.

SRAMs are fast.

They are volatile.

They are of high cost.

Less density.
36. What are the Characteristics of DRAMs?

Low cost.

High density.

Refresh circuitry is needed.


37. Define Refresh Circuit?
It is a circuit which ensures that the contents of a DRAM are maintained when each
row of cells are accessed periodically.
38. Define Memory Latency?
It is used to refer to the amount of time it takes to transfer a word of data to or from
the memory.

Prepared By
Mrs. V.Rekha AP / MCA

39. What are asynchronous DRAMs?


In asynchronous DRAMs, the timing of the memory device is controlled
asynchronously. A specialized memory controller circuit provides the necessary control
signals RAS and CAS that govern the timing. The processor must take into account the
delay in the response of the memory. Such memories are asynchronous DRAMs.
40. Where is a TLB located and what does it contain?
[JUN 2012 & Jan 2013]
A translation look aside buffer (TLB) is a cache that memory management hardware
uses to improve virtual address translation speed. All current desktop, notebook, and server
processors use a TLB to map virtual and physical address spaces, and it is nearly always
present in any hardware which utilizes virtual memory.
41. Define Bandwidth?
When transferring blocks of data, it is of interest to know how much time is needed
to transfer an entire block. Since blocks can be variable in size it is useful to define a
performance measure in terms of number of bits or bytes that can be transferred in one
second. This measure is often referred to as the memory bandwidth.
42. What is double data rate SDRAMs? [DEC 2011]
Double data rates SDRAMs are those which can transfer data on both edges of the
clock and their bandwidth is essentially doubled for long burst transfers.
43. What is motherboard?
Mother Board is a main system printed circuit board which contains the processor. It will
occupy an unacceptably large amount of space on the board.
44. What are SIMMs and DIMMs?
SIMMs are Single In-line Memory Modules. DIMMs are Dual In-line Memory Modules.
Such modules are an assembly of several memory chips on a separate small board that
plugs vertically into a single socket on the motherboard.
45. What is memory Controller?
A memory controller is a circuit which is interposed between the processor and the
dynamic memory. It is used for performing multiplexing of address bits. It provides RASCAS timing. It also sends R/W and CS signals to the memory. When used with DRAM chips,
which do not have self refreshing capability, the memory controller has to provide all the
information needed to control the refreshing process.
46. Differentiate static RAM and dynamic RAM?

Static RAM Dynamic RAM

They are fast They are slow

They are very expensive They are less expensive

They retain their state indefinitely They do not retain their state indefinitely

They require several transistors They require less no transistors.

Low density High density


47. What are RIMMs?
RDRAM chips can be assembled in to larger modules called RIMMs. It can hold upto
16 RDRAMs.
48. What are RDRAMs?

Prepared By
Mrs. V.Rekha AP / MCA

6
RDRAMs are RAMBUS DRAMs. RAMBUS requires specially designed memory chips.
These chips use cell arrays based on the standard DRAM technology. Multiple banks of cell
arrays are used to access more than one word at a time. Circuitry needed to interface to the
RAMBUS channel is included on the chip. Such chips are known as RDRAMs.
49. What are the special features of Direct RDRAMs?

It is a two channel Rambus..

It has 18 data lines intended to transfer two bytes of data at a time.

There are no separate address lines.


50. Define ROM?
It is a non-volatile memory. It involves only reading of stored data.
51. What are the features of PROM?
They are programmed directly by the user.
Faster
Less expensive
More flexible.
52. Why EPROM chips are mounted in packages that have transparent window?
Since the erasure requires dissipating the charges trapped in the transistors of
memory cells. This can be done by exposing the chip to UV light.
53. What are the disadvantages of EPROM?
The chip must be physically removed from the circuit for reprogramming and its entire
contents are erased by the ultraviolet light.
54. What are the advantages and disadvantages of using EEPROM?
The advantages are that EEPROMs do not have to be removed for erasure. Also it is
possible to erase the cell contents selectively. The only disadvantage is that different
voltages are needed for erasing, writing and reading the stored data.
55. Differentiate flash devices and EEPROM devices.
Flash devices: It is possible to read the contents of a single cell, but it is only possible to
write an entire block of cells. It is possible to read and write the contents of a single cell.
EEPROM devices: Greater density which leads to higher capacity. Relatively lower
density Lower cost per bit. Relatively more cost. Consumes less power in their operation
and makes it more attractive for use in portable equipments that is battery driven.
Consumes more power.
56. Define flash memory?
It is an approach similar to EEPROM technology. A flash cell is based on a single
transistor controlled by trapped charge just like an EEPROM cell.
57. What is locality of reference?
Analysis of programs shows that many instructions in localized areas of the program
are executed repeatedly during some time period., and the remainder of the program is
accessed relatively infrequently. This is referred to as locality of reference. This property
leads to the effectiveness of cache mechanism.
58. What are the two aspects of locality of reference?. Define them.

Prepared By
Mrs. V.Rekha AP / MCA

7
Two aspects of locality of reference are temporal aspect and spatial aspect. Temporal
aspect is that a recently executed instruction is likely to be executed again very soon. The
spatial aspect is that instructions in close proximity to a recently executed instruction are
also to be executed soon.
59. Define cache line.
Cache block is used to refer to a set of contiguous address locations of some size.
Cache block is also referred to as cache line.
60. What are the two ways in which the system using cache can proceed for a
write operation?
Write through protocol technique.
Write-back or copy back protocol technique.
61. What is writing through protocol?
For a write operation using write through protocol during write hit: the cache location
and the main memory location are updated simultaneously. For a write miss: For a write
miss, the information is written directly to the main memory.
62. When does a readmiss occur?
When the addressed word in a read operation is not in the cache, a read miss occur.
63. What is write-back or copy back protocol?
For a write operation using this protocol during write hit: the technique is to update
only the cache location and to mark it as updated with an associated flag bit, often called
the dirty or modified bit. The main memory location of the word is updated later, when the
block containing this marked word is to be removed from the cache to make room for a new
block. For a write miss: the block containing the addressed word is first brought into the
cache, and then the desired word in the cache is overwritten with the new information.
64. What is load-through or early restart?
When a read miss occurs for a system with cache the required word may be sent to
the processor as soon as it is read from the main memory instead of loading in to the cache.
This approach is called load through or early restart and it reduces the processors waiting
period.
65. What are the mapping techniques?
Direct mapping
Associative mapping
Set Associative mapping
66. What is a hit & hit rate?
A successful access to data in cache memory is called hit. The number of hits stated
as a fraction of all attempted access.
67. What are vectored interrupts? [DEC 2011]
In a computer, a vectored interrupt is an I/O interrupt that tells the part of the
computer that handles I/O interrupts at the hardware level that a request for attention from
an I/O device has been received and also identifies the device that sent the request.
68. What are the two ways of constructing a larger module to mount flash chips on
a small card?

Prepared By
Mrs. V.Rekha AP / MCA

8
Flash cards
Flash drivers.
69. Define miss rate and miss penalty?
It is the number of misses stated as a fraction of attempted accesses. The extra time
needed to bring the desired information into the cache.
70. Define access time for magnetic disks?
The sum of seek time and rotational delay is called as access time for disks. Seek
time is the time required to move the read/write head to the proper track. Rotational delay
or latency is the amount of time that elapses after the head is positioned over the correct
track until the starting position of the addressed sector passes under the read/write head.
71. What is phase encoding or Manchester encoding?
It is one encoding technique for combining clocking information with data. It is a
scheme in which changes in magnetization occur for each data bit. It s disadvantage is poor
bit-storage density.
72. What are prefetch instructions?
Prefetch Instructions are those instructions which can be inserted into a program
either by the programmer or by the compiler.
73. Define system space and user space.
Management routines are part of the operating system of the computer. It is
convenient to assemble the OS routines into a virtual address space.
The system space is separated from virtual address space in which the user
application programs reside. The letter space is called user space.
74. What are pages?
All programs and data are composed of fixed length units called pages. Each consists
of blocks of words that occupy contiguous locations in main memory.
75. What is replacement algorithm?
When the cache is full and a memory word that is not in the cache is referenced, the
cache control hardware must decide which block should be removed to create space for the
new block that contains the reference word .The collection of rules for making this decision
constitutes the replacement algorithm.
76. What is dirty or modified bit?
The cache location is updated with an associated flag bit called dirty bit.
77. What is write miss?
During the write operation if the addressed word is not in cache then said to be write
miss.
78. What is associative research?
The cost of an associative cache is higher than the cost of a direct mapped cache because of
the need to search all 128 tag patterns to determine whether a given block is in the cache.
A search of this kind is called an associative search.
79. What is virtual memory?

Prepared By
Mrs. V.Rekha AP / MCA

9
Techniques that automatically move program and data blocks into the physical main
memory when they are required for execution are called as virtual memory.
80. What is virtual address?
The binary address that the processor used for either instruction or data called as virtual
address.
81. What is virtual page number & page frame?
Each virtual address generated by the processor whether it is for an instruction fetch
is interpreted as a virtual page.
An area in the main memory that can hold one page is called as page frame.
82. What is Winchester technology?
The disk and the read/write heads are placed in a sealed air-filtered enclosure called
Winchester technology.
83. What is a disk drive & disk controller?
The electromechanical mechanism that spins the disk and moves the read/write
heads called disk drive.
The electronic circuitry that controls the operation of the system called as disk
controller.
84. What is main memory address?
The address of the first main memory location of the block of words involved in the
transfer is called as main memory address.
85. What is Error checking?
It computes the error correcting code (ECC) value for the data read from a given sector and
compares it with the corresponding ECC value read from the disk.
86. What is booting?
When the power is turned on the OS has to be loaded into the main memory which
takes place as part of a process called booting. To initiate booting a tiny part of main
memory is implemented as a nonvolatile ROM.
87. What are the two states of processor?
Supervisor state
User state.
88. What is lockup-free?
A cache that can support multiple outstanding misses is called lockup-free.
89. What is a cycle stealing in DMA?

[Jan 2013]

Prepared By
Mrs. V.Rekha AP / MCA

10
The timing sequence of events for the devices as DMA controller 2 requests and
acquires bus mastership and later releases the bus. During Its tenure as the bus master, it
may perform one or more data transfer operations, depending on whether it is operating in
the cycle stealing or block mode.
Part - B
1. Explain some basic concepts of memory system.
Computer should have a large memory to facilitate execution of programs that are
large and deal with huge amounts of data. The memory should be fast, large, and
inexpensive. Unfortunately, it is impossible to meet all three of these requirements
simultaneously. Increased speed and size are achieved at increased cost. To solve this
problem, much work has gone into developing clever structures that improve the apparent
speed and size of the memory, yet keep the cost reasonable.
The maximum size of the memory that can be used in any computer is determined
by the addressing scheme. For example, a 16-bit computer that generates 16-bit addresses
is capable of addressing up to 216 = 64K (65536) memory locations. Similarly, machines
whose instructions generate 32-bit addresses can utilize a memory that contains up to 232
= 4G (giga) memory locations, whereas machines with 4O-bit addresses can access up to
240 = 1 T (Tera) locations. The number of locations represents the size of the address space
of the computer.
From the system standpoint, we can view the memory unit as a black box. Data
transfer between the memory and the processor takes place through the use of two
processor registers, usually called MAR (memory address register) and MDR (memory data
register), If MAR is k bits long and MDR is n bits long, then the memory unit may contain up
to 2 k addressable locations.
During a memory cycle, n bits of data are transferred between the memory and the
processor. This transfer takes place over the processor bus, which has k address lines and n
data lines. The bus also includes the con1rollines Read / Write (R / W) and Memory Function
Completed (MFC) for coordinating data transfers. Other control lines may be added to
indicate the number of bytes to be transferred. The connection between the processor and
the memory are shown.

Connection of the memory to the processor

The processor reads data from the memory by loading the address of the required
memory location into the MAR register and setting the R / W line to 1. The memory
responds by placing the data from the addressed location onto the data lines, and confirms

Prepared By
Mrs. V.Rekha AP / MCA

11
this action by asserting the MFC signal. Upon receipt of the MFC signal, the processor loads
the data on the data lines into the MDR register.
The processor writes data into a memory location by loading the address of this
location into MAR and loading the data into MDR. It indicates that a write operation is
involved by setting the R/ W line to 0. If read or write operations involve consecutive
address locations in the main memory, then a "block transfer" operation can be performed
in which the only address sent to the memory is the one that identifies the first location.
The time between the Read and the MFC signals is referred to as the memory access
time. The memory cycle time is the minimum time delay required between the initiations of
two successive memory operations, If any location can be accessed for a Read or Write
operation some fixed amount of time that is independent of the location's address in a
memory unit is called random-access memory (RAM). One way to reduce the memory
access time is to use a cache memory. This is a small, fast memory that is inserted between
the larger, slower main memory and the processor. It holds the currently active segments of
a program and their data.
Virtual memory is used to increase the apparent size of the physical memory. Data
are addressed in a virtual address space that can be as large as the addressing capability of
the processor. But at any given time, only the active portion of this space is mapped onto
locations in the physical memory. The remaining virtual addresses are mapped onto the
bulk: storage devices used, which are usually magnetic disks. The virtual address space is
mapped onto the physical memory where data are actually stored. The mapping function is
implemented by a special memory control circuit, often called the memory management
unit.
2. Discuss internal organization of memory chips.
Memory cells are usually organized in the form of an array, in which each cell is
capable of storing one bit of information. A possible organization is illustrated,

Prepared By
Mrs. V.Rekha AP / MCA

12

Organization of bit cell in a memory chip


Each row of cells constitutes a memory word, and all cells of a row are connected to
a common line referred to as the word line, which is driven by the address decoder on the
chip. The cells in each column are connected to a Sense/Write circuit by two bit lines. The
Sense/Write circuits are connected to the data input/output lines of the chip. During a Read
operation, these circuits sense, or read, the information stored in the cells selected by a
word line and transmit this information to the output data lines. During a Write operation,
the Sense/Write circuits receive input information and store it in the cells of the selected
word.
An example of a very small memory chip consisting of 16 words of 8 bits each. This
is referred to as a 16 x 8 organization. The data input and the data output of each
Sense/Write circuit are connected to a single bidirectional data line that, can be connected
to the data bus of a computer. Two control lines, R/W and CS, are provided in addition to
address and data lines. The R/W (Read/Write ) input specifies the required operation, and
the CS (Chip Select) input selects a given chip in a multichip memory system.

Prepared By
Mrs. V.Rekha AP / MCA

13

Organization of 1K x 1 memory chip


The memory circuit in Figure 4.2 stores 128 bits and requires 14 external
connections for address, data, and control lines. Of course, it also needs two lines for power
supply and ground connections. Consider now a slightly larger memory circuit, one that has
l K (1024) memory cells. This circuit can be organized as a 128 x 8 memory, requiring a
total of 19 external connections. Alternatively, the same number of cells can be organized
into a l K x 1 format. In this case, a 100bit address is needed, but there is only one data
line, resulting in 15 external connections.
The required 100bit address is divided into two groups of 5 bits each to form the row
and column addresses for the cell array. A row address selects a row of 32 cells, all of which
are accessed in parallel.
However, according to the column address, only one of these cells is connected to
the external data line by the output multiplexer and input de-multiplexer. For an example, a
4M-bit chip may have a 512K x 8 organization, in which case 19 address and 8 data
input/output pins are needed.
3. Explain Static Memories.
Static memories are the Memories that consist of circuits capable of retaining their
state as long as power is applied are known as static memories. Figure 4.4 illustrates how a
static RAM (SRAM) cell may be implemented. Two inverters are cross-connected to form a
latch. The latch is connected to two bit lines by transistors Tl and T2. These transistors act
as switches that can be opened or closed under control of the word line. When the word line
is at ground level, the transistors are turned off and the latch retains its state. For example,
let us assume that the cell is in state 1 if the logic value at point X is 1 and at point Y is 0.
This state is maintained as long as the signal on the word line is at ground level.
Read operation
In order to read the state of the SRAM cell, the word line is activated to close
switches Tl and T2. If the cell is in state 1, the signal on bit line b is high and the signal on
bit line b' is low. The opposite is true if the cell is in state 0. Thus, b and b' are complements
of each other. Sense/Write circuits at the end of the bit lines monitor the state of b and b'
and set the output accordingly.

Prepared By
Mrs. V.Rekha AP / MCA

14

Write operation
The state of the cell is set by placing the appropriate value on bit line b and its
complement on b', and then activating the word line. This forces the cell into the
corresponding state. The required signals on the bit lines are generated by the Sense/Write
circuit. If Tl and T2 are turned on (closed), it lines b and b ' will have high and low signals,
respectively.

A static RAM cell

An example of a CMOS memory cell

The power supply voltage, V supply, is 5 V in older CMOS SRAMs or 3.3 V in new low
voltage versions. Note that "continuous power is needed for the cell to retain its state. If
power is interrupted, the cell's contents will be lost.
When power is restored, the latch will settle into a stable state, but it will not
necessarily be the same state the cell was in before the interruption. Hence, SRAMs are said
to be volatile memories because their contents are lost when power is interrupted.
A major advantage of CMOS SRAMs is their very low power consumption because
current flows in the cell only when the cell is being accessed. Otherwise, Tl, T2 and one
transistor in each inverter are turned off, ensuring that there is no active path between V
supply and ground.
Static RAMs can be accessed very quickly. Access times of just a few nanoseconds
are found in commercially available chips. SRAMs are used in applications where speed is of
critical concern.

Prepared By
Mrs. V.Rekha AP / MCA

15

4. Explain Asynchronous DRAMS & Synchronous DRAMS .


Asynchronous DRAMS:
Static RAMs are fast, but they come at a high cost because their cells require several
transistors. Less expensive RAMs can be implemented if simpler cells are used. However,
such cells do not retain their state indefinitely; hence, they are called dynamic RAMs
(DRAMs).
Information is stored in a dynamic memory cell in the form of a charge on a
capacitor, and this charge can be maintained for only tens of milliseconds. Since the cell is
required to store information for a much longer time, its contents must be periodically
refreshed by restoring the capacitor charge to its full value.
An example of a dynamic memory cell that consists of a capacitor, C, and a
transistor, T, is order to store information in this cell, transistor T is turned on and an
appropriate voltage is applied to the bit line. This causes a known amount of charge to be
stored in the capacitor.

A single transistor dynamic memory cell

Prepared By
Mrs. V.Rekha AP / MCA

16

Internal Organization of a 2M x 8 dynamic memory chip

A 16-megabit DRAM chip, configured as 2M x 8, is shown in Figure 4.7. The cells are
organized in the form of a 4 K x 4 K array. The 4096 cells in each row are divided into 512
groups row. Another 9 bits are needed to specify a group of 8 bits in the selected row.
Thus, a 21-bit address is needed to access a byte in this memory. The high-order 12 bits
and the low-order 9 bits of the address constitute the row and column addresses of a byte,
respectively.
To reduce the number of pins needed for external connections, the row and column
addresses are multiplexed on 12 pins. During a Read or a Write operation, the row address
is applied first. It is loaded into the row address latch in response to a signal pulse on the
Row Address Strobe (RAS) input of the chip.
Then a Read operation is initiated, in which all cells on the selected row are read and
refreshed. Shortly after the row address is loaded, the column address is applied to the
address pins and loaded into the column address latch under control of the Column Address
Strobe (CAS) signal. The information in this latch is decoded and the appropriate groups of
8 Sense/Write circuits are selected. If the R/W control signal indicates a Read operation, the
output values of the selected circuits are transferred to the data lines, D7-0.
For a Write operation, the information on the D7-0 lines is transferred to the selected
circuits. This information is then used to overwrite the contents of the selected cells in the
corresponding 8 columns. We should note that in commercial DRAM chips, the RAS and CAS
control signals are active low so that they cause the latching of addresses when they change
from high to low.
In the DRAM described in this section, the timing of the memory device is controlled
asynchronously. A specialized memory controller circuit provides the necessary control
signals, RAS and CAS, which govern the timing. The processor must take into account the
delay in the response of the memory. Such memories are referred to as asynchronous
DRAMs.
Because of their high density and low cost, DRAMs are widely used in the memory
units of computers. Available chips range in size from 1M to 256M bits, and even larger

Prepared By
Mrs. V.Rekha AP / MCA

17
chips are being developed. To reduce the number of memory chips needed in a given
computer, a DRAM chip is organized to read or write a number of bits in parallel. To provide
flexibility in designing memory systems, these chips are manufactured in different
organizations.
Synchronous DRAMS
DRAMs whose operation is directly synchronized with a clock signal are known as
synchronous DRAMs (SDRAMs). The cell array is the same as in asynchronous DRAMs. The
address and data connections are buffered by means of registers. We should particularly
note that the output of each sense amplifier is connected to a latch. A Read operation
causes the contents of all cells in the selected row to be loaded into these latches. But, if an
access is made for refreshing purposes only, it will not change the contents of these latches;
it will merely refresh the contents of the cells. Data held in the hitches that correspond to
the selected column(s) are transferred into the data output register, thus becoming available
on the data output pins.
The row address is latched under control of the RAS signal. The memory typically
takes 2 or 3 clock cycles to activate the selected row. Then, the column address is latched
under control of the CAS signal. After a delay of one clock cycle, the first set of data bits is
placed on the data lines. The SDRAM automatically increments the column address to
access the next three sets of bits in the selected row, which are placed on the data lines in
the next 3 clock cycles.
SDRAMs have built-in refresh circuitry. A part of this circuitry is a refresh counter,
which provides the addresses of the rows that are selected for refreshing. In a typical
SDRAM, each row must be refreshed at least every 64 ms. Commercial SDRAMs can be
used with clock speeds above 100 MHz. These chips are designed to meet the requirements
of commercially available processors that are used in large volume.
Transfers between the memory and the processor involve single words of data or
small blocks of words. Large blocks, constituting a page of data, are transferred between
the memory and the disks. The speed and efficiency of these transfers have a large impact
on the performance of a computer system.

Synchronous DRAM

Prepared By
Mrs. V.Rekha AP / MCA

18

Burst read of length 4 in SDRAM

A good indication of the performance is given by two parameters: latency and


bandwidth. The term memory latency is used to refer to the amount of time it takes to
transfer a word of data to or from the memory. In the case of reading or writing a single
word of data, the latency provides a complete indication of memory performance. But, in
the case of burst operations that transfer a block of data, the time needed to complete the
operation depends also on the rate at which successive words can be transferred and on the
size of the block.
When transferring blocks of data, it is of interest to know how much time is needed
to transfer an entire block. Since blocks can be variable in size, it is useful to define a
performance measure in terms of the number of bits or bytes that can be transferred in one
second. This measure is often referred to as the memory bandwidth. The bandwidth of a
memory unit depends on the speed of access to the stored data and on the number of bits
that can be accessed in parallel.
5. Discuss about Read Only Memories.
ROM memories are non-volatile memories, which mean only reading of stored data,
a memory of this type is called read-only memory.

A ROM cell

Prepared By
Mrs. V.Rekha AP / MCA

19
The diagram shows a possible configuration for a ROM cell. A logic value 0 is stored
in the cell if the transistor is connected to ground at point P; otherwise, a 1 is stored. The
bit line is connected through a resistor to the power supply. To read the state of the cell, the
word line is activated.
Thus, the transistor switch is closed and the voltage on the bit line drops to near zero
if there is a connection between the transistor and ground. If there is no connection to
ground, the bit line remains at the high voltage, indicating a 1. A sense circuit at the end of
the bit line generates the proper output value. Data are written into a ROM when it is
manufactured.
Types of ROM:
a. PROM
Programmable ROM (PROM). Programmability is achieved by inserting a fuse at point
P in above diagram. Before it is programmed, the memory contains all 0s. The user can
insert 1s at the required locations by burning out the fuses at these locations using highcurrent pulses.
b. EPROM
Another type of ROM chip allows the stored data to be erased and new data to be
loaded. Such an erasable, reprogrammable ROM is usually called an EPROM. It provides
considerable flexibility during the development phase of digital systems. Since EPROMs are
capable of retaining stored information for a long time, they can be used in place of ROMs
while software is being developed.
c. EEPROM
A significant disadvantage of EPROMs is that a chip must be physically removed from
the circuit for reprogramming and that its entire contents are erased by the ultraviolet light.
It is possible to implement another version of erasable PROMs that can be both programmed
and erased electrically. Such chips, called EEPROMs, do not have to be removed for erasure.
d.

FLASH MEMORIES

A flash memory devices cell is based on a single transistor controlled by trapped


charge, just like an EEPROM cell. While similar in some respects, there are also substantial
differences between flash and EEPROM devices. In EEPROM it is possible to read and write
the contents of a single cell.
Typical applications include hand-held computers, cell phones, digital cameras, and
MP3 music players. Single flash chips do not provide sufficient storage capacity for the
applications mentioned above. Larger memory modules consisting of a number of chips are
needed. There are two popular choices for the implementation of such modules: flash cards
and flash drives.
Flash Cards
One way of constructing a larger module is to mount flash chips on a small card.
Such flash cards have a standard interface that makes them usable in a variety of products.

Prepared By
Mrs. V.Rekha AP / MCA

20
A card is simply plugged into a conveniently accessible slot. Flash cards come in a variety of
memory sizes. Typical sizes are 8, 32, 64 MB and so on.
Flash drive
Larger flash memory modules have been developed to replace, hard disk drives.
These flash drives are designed to fully emulate the bard disks, to the point that they can be
fitted into standard disk drive bays. The fact that flash drives are solid state electronic
devices that have no movable parts provides.
Advantages:

They have shorter seek and access times, which results in faster response.
They have lower power consumption, which makes them attractive for battery driven
applications, and they are also insensitive to vibration.
Another type of ROM chip allows the stored data to be erased and new data to be
loaded.

Dis-advasntages:

Flash drives are less storage capacity.


Higher cost per bit and it will become weak after it has been written several times.

6. Discuss speed, size and cost of Memories


An ideal memory would be fast, large, and inexpensive. a very fast memory can be
implemented if SRAM chips are used. But these chips are expensive because their basic cells
have six transistors, which preclude packing a very large number of cells onto a single chip.
It is impractical to build a large memory using SRAM chips. The alternative is to use
dynamic RAM chips, which have much simpler basic cells and thus are much less expensive.
But such memories are significantly slower.
Although dynamic memory units in the range of hundreds of megabytes can be
implemented at a reasonable cost, the affordable size is still small compared to the
demands of large programs with voluminous data.
A solution is provided by using secondary storage, mainly magnetic disks, to
implement large memory spaces. Very large disks are available at a reasonable price, and
they are used extensively in computer systems.
They are much slower than the semiconductor memory units. So a huge amount of
cost-effective storage can be provided by magnetic disks. A large, yet affordable, main
memory can be built with dynamic RAM technology. This leaves SRAMs to be used in smaller
units where speed is of the essence, such as in cache memories.
All of these different types of memory units are employed effectively in a computer.
The entire computer memory can be viewed as the hierarchy depicted. The fastest access is
to data held in processor registers. Therefore, if we consider the registers to be part of the
memory hierarchy, then the processor registers are at the top in terms of the speed of
access. Of course, the registers provide only a minuscule portion of the required memory.

Prepared By
Mrs. V.Rekha AP / MCA

21

Memory hierarchy

At the next level of the hierarchy is a relatively small amount of memory that can be
implemented directly on the processor chip. This memory, called a processor cache, holds
copies of instructions and data stored in a much larger memory that is provided externally.
There are often two levels of caches. A primary cache is always located on the
processor chip. This cache is small because it competes for space on the processor chip,
which must implement many other functions.
The primary cache is referred to as level (L1) cache. A larger, secondary cache is
placed between the primary cache and the rest of the memory. It is referred to as level 2
(L2) cache. It is usually implemented using SRAM chips. It is possible to have both Ll and L2
caches on the processor chip.
The next level in the hierarchy is called the main memory. This rather large memory
is implemented using dynamic memory components, typically in the form of SIMMs, DIMMs,
or RIMMs. The main memory is much larger but significantly slower than the cache memory.
In a typical computer, the access time for the main memory is about ten times longer than
the access time for the L 1 cache. Disk devices provide a huge amount of inexpensive
storage. They are very slow compared to the semiconductor devices used to implement the
main memory.

Prepared By
Mrs. V.Rekha AP / MCA

22
A hard disk drive is a device for storing and retrieving digital information, primarily
computer data. It consists of one or more rigid rapidly rotating discs coated with magnetic
material and with magnetic heads arranged to write data to the surfaces and read it from
them. During program execution, the speed of memory access is of utmost importance. The
key to managing the operation of the hierarchical memory system in Figure 4.13 is to bring
the instructions and data that will be used in the near future as close to the processor as
possible. This can be done by using the hardware mechanisms.
7. Explain the cache memory mapping functions with necessary block diagrams.
[JUN 2012]
Speed of the main memory is very low in comparison with the speed of processor.
For good performance, the processor cannot spend much time of its time waiting to access
instructions and data in main memory. Important to device a scheme that reduces the time
to access the information. An efficient solution is to use fast cache memory. When a cache is
full and a memory word that is not in the cache is referenced, the cache control hardware
must decide which block should be removed to create space for the new block that contain
the referenced word.
The effectiveness of the cache mechanism is based on a property of computer
programs called locality of reference. Analysis of programs shows that most of their
execution time is spent on routines in which many instructions are executed repeatedly.
These instructions may constitute a simple loop, nested loops, or a few procedures that
repeatedly call each other.
Many instructions in localized areas of the program are executed repeatedly during
some time period, and the remainder of the program is accessed relatively infrequently. This
is referred to as locality of reference. It manifests itself in two ways: temporal and spatial.

The temporal means that a recently executed instruction is likely to be executed again very
soon.

The spatial aspect means that instructions in close proximity to a recently executed
instruction are also likely to be executed soon.
When a Read request is received from the processor, the contents of a block of
memory words containing the location specified are transferred into the cache one word at a
time. Subsequently, when the program references any of the locations in this block, the
desired contents are read directly from the cache. Usually, the cache memory can store a
reasonable number of blocks at any given time, but this number is small compared to the
total number of blocks in the main memory.
Replacement algorithm
The correspondence between the main memory blocks and those in the cache is
specified by a mapping function. When the cache is full and a memory word that is not in
the cache is referenced, the cache control hardware must decide which block should be
removed to create space for the new block that contains the referenced word. The collection
of rules for making this decision constitutes the replacement algorithm.

Prepared By
Mrs. V.Rekha AP / MCA

23

Cache memory

The basics of Caches:


The caches are organized on basis of blocks, the smallest amount of data which can
be copied between two adjacent levels at a time. If data requested by the processor is
present in some block in the upper level, it is called a hit.
If data is not found in the upper level, the request is called a miss and the data is
retrieved from the lower level in the hierarchy. The fraction of memory accesses found in the
upper level is called a hit ratio. The storage, which takes advantage of locality of accesses,
is called a cache
The processor does not need to know explicitly about the existence of the cache. It
simply issues Read and Write requests using addresses that refer to locations in the
memory. The cache control circuitry determines whether the requested word currently exists
in the cache.
The Read or Write operation is performed on the appropriate cache location. In this
case, a read or write hit is said to have occurred. In a Read operation, the main memory is
not involved.
For a Write operation, the system can proceed in two ways. In the first technique,
called the writethrough protocol, the cache location and the main memory location are
updated simultaneously.
The second technique is to update only the cache location and to mark it as updated
with an associated flag bit, often called the dirty or modified bit.
The main memory location of the word is updated later, when the block containing
this marked word is to be removed from the cache to make room for a new block. This
technique is known as the write- back, or copy-back, protocol.
The write-through protocol is simpler, but it results in unnecessary Write operations
in the main memory when a given cache word is updated several times during its cache
residency. Note that the write-back protocol may also result in unnecessary Write operations
because when a cache block is written back to the memory all words of the block are written
back, even if only a single word has been changed while the block was in the cache.
When the addressed word in a Read operation is not in the cache, a read miss
occurs. The block of words that contains the requested word is copied from the main

Prepared By
Mrs. V.Rekha AP / MCA

24
memory into the cache. After the entire block is loaded into the cache, the particular word
requested is forwarded to the processor.
Alternatively, this word may be sent to the processor as soon as it is read from the
main memory. The latter approach, which is called load-through, or early restart, reduces
the processor's waiting period somewhat, but at the expense of more complex circuitry.
During a Write operation, if the addressed word is not in the cache, a write miss
occurs. Then, if the write-through protocol is used, the information is written directly into
the main memory. In the case of the write-back protocol, the block containing the
addressed word is first brought into the cache, and then the desired word in the cache is
overwritten with the new information.

Accessing a Cache:

Prepared By
Mrs. V.Rekha AP / MCA

25

Address Mapping in Cache:

8. With an example illustrate the effects of different cache mapping techniques.


[DEC 2011].
The process of keeping information of moved data blocks from main memory to
cache memory is known as mapping. For example: Consider a cache consisting of 128
blocks of 16 words each, for a total of 2048 (2K) words, and assumes that the main

Prepared By
Mrs. V.Rekha AP / MCA

26
memory is addressable by a 16-bit address. The main memory has 64K words, which we
will view as 4K (4096) blocks of 16 words each.
These mappings can be done in three ways.

Direct mapping
Associative mapping
Set associative mapping

Direct mapping:
The simplest way to determine cache locations in which to store memory blocks is
the direct-mapping technique. In this technique, block j of the main memory maps onto
block j modulo 128 of the cache. Thus, whenever one of the main memory blocks 0, 128,
256, is loaded in the cache, it is stored in cache block 0. Blocks 1, 129, 257, are stored in
cache block 1, and so on. Since more than one memory block is mapped onto a given cache
block position, contention may arise for that position even when the cache is not full.
For example, instructions of a program may start in block 1 and continue in block
129, possibly after a branch. As this program is executed, both of these blocks must be
transferred to the block-1 position in the cache. Contention is resolved by allowing the new
block to overwrite the currently resident block.
The replacement algorithm is trivial. Placement of a block in the cache is determined
from the memory address. The memory address can be divided into three fields. The loworder 4 bits select one of 16 words in a block. When a new block enters the cache, the 7 -bit
cache block field determines the cache position in which this block must be stored. The
high-order 5 bits of the memory address of the block are stored in 5 tag bits associated with
its location in the cache.

Prepared By
Mrs. V.Rekha AP / MCA

27
Associative mapping:
More flexible mapping technique a main memory block can be placed into any cache
block position. In this case, 12 tag bits are required to identify a memory block when it is
resident in the cache. The tag bits of an address received from the processor are compared
to the tag bits of each block of the cache to see if the desired block is present. This is called
the associative-mapping technique.
It gives complete freedom in choosing the cache location in which to place the
memory block. Thus, the space in the cache can be used more efficiently. A new block that
has to be brought into the cache has to replace (eject) an existing block only if the cache is
full. In this case, we need an algorithm to select the block to be replaced. Many replacement
algorithms are possible; the cost of an associative cache is higher than the cost of a directmapped cache because of the need to search all 128 tag patterns to determine whether a
given block is in the cache. A search of this kind is called an associative search. For
performance reasons, the tags must be searched in parallel.

Associative-mapped cache.

Set-Associative mapping
A combination of the direct- and associative-mapping techniques can be used. Blocks
of the cache are grouped into sets, and the mapping allows a block of the main memory to
reside in any block of a specific set. Hence, the contention problem of the direct method is

Prepared By
Mrs. V.Rekha AP / MCA

28
eased by having a few choices for block placement. At the same time, the hardware cost is
reduced by decreasing the size of the associative search.
An example of this set-associative-mapping technique for a cache with two blocks
per set. In this case, memory blocks 0, 64, 128, 4032 map into cache set 0, and they can
occupy either of the two block positions within this set. Having 64 sets means that the 6-bit
set field of the address determines which set of the cache might contain the desired block.
This two-way associative search is simple to implement. The number of blocks per
set is a parameter that can be selected to suit the requirements of a particular computer.
For the main memory and cache sizes, four blocks per set can be accommodated by a 5-bit
set field, eight blocks per set by a 4-bit set field, and so on.

Set-Associative-mapped cache with two blocks per set.

A similar difficulty arises when a DMA transfer is made from the main memory to the
disk, and the cache uses the write-back protocol. In this case, the data in the memory
might not reflect the changes that may have been made in the cached copy. One solution to
this problem is to flush the cache by forcing the dirty data to be written back to the memory
before the DMA transfer takes place.
9. With neat diagram, explain how virtual memory uses address translation
method to translate virtual addresses into corresponding physical addresses.
[Jan 2013]

Prepared By
Mrs. V.Rekha AP / MCA

29
The physical main memory is not as large as the address space spanned by an
address issued by the processor. When a program does not completely fit into the main
memory, the parts of it not currently being executed are stored on secondary storage
devices, such as magnetic disks. Of course, all parts of a program that are eventually
executed are first brought into the main memory.
When a new segment of a program is to be moved into a full memory, it must
replace another segment already in the memory. The operating system moves programs
and data automatically between the main memory and secondary storage. This process is
known as swapping. Thus, the application programmer does not need to be aware of
limitations imposed by the available main memory.
Techniques that automatically move program and data blocks into the physical main
memory when they are required for execution are called virtual-memory techniques.
Programs, and hence the processor, reference an instruction and data space that is
independent of the available physical main memory space. The binary addresses that the
processor issues for either instructions or data are called virtual or logical addresses. These
addresses are translated into physical addresses by a combination of hardware and software
components.
If a virtual address refers to a part of the program or data space that is currently in
the physical memory, then the contents of the appropriate location in the main memory are
accessed immediately. On the other hand, if the referenced address is not in the main
memory, its contents must be brought into a suitable location in the memory before they
can be used.

Virtual memory organization

Address Translation of Virtual memory:


The process of translating a virtual address into physical address is known as address
translation. It can be done with the help of MMU. A simple method for translating virtual

Prepared By
Mrs. V.Rekha AP / MCA

30
addresses into physical addresses is to assume that all programs and data are composed of
fixed-length units called pages, each of which consists of a block of words that occupy
contiguous locations in the main memory.
Pages commonly range from 2K to 16K bytes in length. They constitute the basic unit
of information that is moved between the main memory and the disk whenever the
translation mechanism determines that a move is required. Pages should not be too small,
because the access time of a magnetic disk is much longer than the access time of the main
memory. The reason for this is that it takes a considerable amount of time to locate the data
on the disk, but once located, the data can be transferred at a rate of several megabytes
per second. On the other hand, if pages are too large it is possible that a substantial portion
of a page may not be used, yet this unnecessary data will occupy valuable space in the main
memory.

Virtual memory address translation

The cache bridges the speed gap between the processor and the main memory and
is implemented in hardware. The virtual-memory mechanism bridges the size and speed
gaps between the main memory and secondary storage and is usually implemented in part
by software techniques. Conceptually, cache techniques and virtual- memory techniques are
very similar. They differ mainly in the details of their implementation.
A virtual-memory addresses translation method based on the concept of fixed-length
pages. Each virtual address generated by the processor, whether it is for an instruction fetch
or an operand fetch/store operation, is interpreted as a virtual page number followed by an
offset that specifies the location of a particular byte within a page. Information about the

Prepared By
Mrs. V.Rekha AP / MCA

31
main memory location of each page is kept in a page table. This information includes the
main memory address where the page is stored and the current status of the page. An area
in the main memory that can hold one page is called a page frame.
The starting address of the page table is kept in a page table base register. By
adding the virtual page number to the contents of this register, the address of the
corresponding entry in the page table is obtained. The contents of this location give the
starting address of the page if that page currently resides in the main memory.
10. Define the term memory. Explain various to implement associative memory.
[JAN 2012 & JUN 2012]
`Many data-processing applications require the search of items in a table stored in
memory. They use object names or number to identify the location of the named or
numbered object within a memory space. For example, an account number may be
searched in a file to determine the holder's name and account status. To search an object,
the number of accesses to memory depends on the location of the object and the efficiency
of the search algorithm.
The time required to find an object stored in memory can be reduced considerably if
objects are selected based on their contents, not on their locations. A memory unit
addressed by the content is called an associative memory or content addressable Memory
(CAM).
This type of memory is accessed simultaneously and in parallel on the basis of data
content rather than by specific address or location. In general, the instructions which are
available in a special kind of memories like cache, ROM and Virtual memory are addressed
by content and not by address location.

Block diagram of associative memory

The block diagram of an associative memory it consists of memory array with match
logic for m n-bit words and associated registers. The argument register (A) and key register
(K) each have n-bits per word. Each word in memory is compared in parallel with the
contents of the argument register. The words match with the word stored in the argument

Prepared By
Mrs. V.Rekha AP / MCA

32
register set corresponding bits in the match register. Therefore, reading can be
accomplished by a sequential access to memory for those words whose corresponding bits
in the match register have been set.
The key register provides a mask for choosing a particular field or bits in the
argument word. Only those bits in the argument register having 1's in their corresponding
position of the key register are compared.
For example, if an argument register A and the key register K have the bit
configuration shown below. Only the three rightmost bits of A are compared with memory
words because K has 1's in these positions.

The associated memory with cells of each register. The cells in the memory array are
marked by the letter C with two subscripts. The first subscript gives the word number and
the second subscript gives the bit position in the word

Cells of each register of associative memory

Prepared By
Mrs. V.Rekha AP / MCA

33

Internal organization of typical cell of associative memory

The internal organization of a typical cell. It consists of RS flip-flop as a storage


element and the circuit for reading, writing and matching the cell. By making the write
signal logic 1, it is possible to transfer the input bit into the storage cell. To carry-out read
operation read signal is made logic 1. The match logic compares the bit in the storage cell
with the corresponding unmasked bit of the argument and provides an output for the
decision logic that sets the corresponding bit the match register.
The cell bit (Qij) is compared with the corresponding argument bit with Ex-NOR gate.
Ex-NOR gate gives output logic1 only when its inputs are same. The output of Ex-NOR gate
is valid only when the corresponding bit in key register is logic 1.
This condition is implemented using 2-input OR gate. When corresponding bit in key
register is logic 1, the inverter gives output 0 which forces the output of OR gate to follow
the second input, i.e. the comparison output; otherwise output of OR-gate is logic 1.
The outputs of all OR-gates are then AND with n-input AND gate to check whether all
bits in the word are matched with the bits in the argument register.

Match logic of one word of associative memory

Read Operation:
In the read operation, all matched words are read in sequence by applying a read
signal to each word line whose corresponding Mi bit is logic 1. In applications where no two
identical items are stored in the memory, only one word may match the unmasked
argument field.
Write Operation
In write operation, consider two separate cases: 1. It is necessary to load entire
memory with new information. 2. It is necessary to replace one word with new information.

Prepared By
Mrs. V.Rekha AP / MCA

34
The entire memory can be loaded with new information by addressing each location in
sequence. This will make the memory device a random access memory for writing and a
content addressable memory for reading. Here, the address for the input can be decoded as
in a random access memory.
11. Discuss Accessing I/O Devices.
In computing, input/output, or I/O, refers to the communication between an
information processing system, and the outside world. Inputs are the signals or data
received by the system, and outputs are the signals or data sent from it. I/O devices are
used by a person to communicate with a computer.
Some of the input devices are keyboard, mouse, track ball, joy stick, touch screen,
digital camera, webcam, image scanner, fingerprint scanner, barcode reader, microphone
and so on. Some of the output devices are speakers, headphones, monitors and printers.
Devices for communication between computers, such as modems and network cards,
typically serve for both input and output.
I/O devices can be connected to a computer through a single bus which enables the
exchange of information. The bus consists of three sets of lines used to carry address, data,
and control signals. Each I/O device is assigned a unique set of addresses. When the
processor places a particular address on the address lines, the device that recognizes this
address responds to the commands issued on the control lines.
The processor requests either a read or a write operation, and the requested data
are transferred over the data lines. The simple arrangement of I/O devices to processor and
memory with single bus.

Memory-mapped I/O: The arrangement of I/O devices and the memory share the
same address space is called memory-mapped I/O. With memory-mapped I/O, any machine
instruction that can access memory can be used to transfer data to or from an I/O device.
For example, if DATAIN is the address of the input buffer associated with the
keyboard, the instruction
Move DATAIN,R0

Prepared By
Mrs. V.Rekha AP / MCA

35

reads the data from DATAIN and stores them into processor register RO. Similarly, the
instruction
Move R0,DATAOUT
sends the contents of register R0 to location DATAOUT, which may be the output data buffer
of a display unit or a printer. Most computer systems use memory-mapped I/O. Some
processors have special In and Out instructions to perform I/O transfers.
The hardware required to connect an I/O device to the bus. The address decoder
enables the device to recognize its address when this address appears on the address lines.
The data register holds the data being transferred to or from the processor. The status
register contains information relevant to the operation of the I/O device.
Both the data and status registers are connected to the data bus and assigned
unique addresses. The address decoder, the data and status registers, and the control
circuitry required to coordinate I/O transfers constitute the device's interface circuit.

I/O interface for an input device

I/O devices operate at speeds that are vastly different from that of the processor.
When a human operator is entering characters at a keyboard, the processor is capable of
executing millions of instructions between successive character entries. An instruction that
reads a character from the keyboard should be executed only when a character is available
in the input buffer of the keyboard interface. An input character is read only once.
For an input device such as a keyboard, a status flag, SIN, is included in the
interface circuit as part of the status register. This flag is set to 1 when a character is
entered at the keyboard and cleared to 0 once this character is read by the processor.
Hence, by checking the SIN flag, the software can ensure that it is always reading valid
data. This is often accomplished in a program loop that repeatedly reads the status register
and checks the state of SIN. When SIN becomes equal to 1, the program reads the input
data register. A similar procedure can be used to control output operations using an output
status flag, SOUT.

Prepared By
Mrs. V.Rekha AP / MCA

36

12. Explain Program-controlled I/O.


Consider a simple example of I/O operations involving a keyboard and a display
device in a computer system. The four registers are used in the data transfer operations.
Register STATUS contains two control flags, SIN and SOUT, which provide status information
for the keyboard and the display unit, respectively. The two flags KIRQ and DIRQ in this
register are used in conjunction with interrupts. They, and the KEN and DEN bits in register
CONTROL, Data from the keyboard are made available in the DATAIN register, and data sent
to the display are stored in the DATAOUT register.

Registers in keyboard and display interfaces.

The program reads a line of characters from the keyboard and stores it in a memory
buffer starting at location LINE. Then, it calls a subroutine PROCESS to process the input
line. As each character is read, it is echoed back to the display. Register R0 is used as a
pointer to the memory buffer area. The contents of R0 are updated using the Autoincrement
addressing mode so that successive characters are stored in successive memory locations.
Each character is checked to see if it is the Carriage Return (CR) character, which has
the ASCII code 0D (hex). If it is, a Line Feed character (ASCII code 0A) is sent to move the
cursor one line down on the display and subroutine PROCESS is called. Otherwise, the
program loops back to wait for another character from the keyboard.
In program-controlled I/O the processor repeatedly checks a status flag to achieve
the required synchronization between the processor and an input or output device. The
processor polls the device.
There are two other commonly used mechanisms for implementing I/O operations:
Interrupts and direct memory access. In the case of interrupts, synchronization is achieved
by having the I/O device send a special signal over the bus whenever it is ready for a data
transfer operation.
13. What is DMA? Discuss DMA controller and DMA transfer with diagram explain
DMA Operation. [JAN & JUN 2012, JAN 2013]
A special control unit is provided to allow transfer of a block of data directly between
an external device and the main memory, without continuous intervention by the processor.
This approach is called direct memory access, or DMA.

Prepared By
Mrs. V.Rekha AP / MCA

37
DMA transfers are performed by a control circuit that is part of the I/O device
interface. We refer to this circuit as a DMA controller. The DMA controller performs the
functions that would normally be carried out by the processor when accessing the main
memory. For each word transferred, it provides the memory address and all the bus signals
that control data transfer. Since it has to transfer blocks of data, the DMA controller must
increment the memory address for successive words and keep track of the number of
transfers.
Although a DMA controller can transfer data without intervention by the processor, its
operation must be under the control of a program executed by the processor. To initiate the
transfer of a block of words, the processor sends the starting address, the number of words
in the block, and the direction of the transfer.
On receiving this information, the DMA controller proceeds to perform the requested
operation. When the entire block has been transferred, the controller informs the processor
by raising an interrupt signal.
While a DMA transfer is taking place, the program that requested the transfer cannot
continue, and the processor can be used to execute another program. After the DMA
transfer is completed, the processor can return to the program that requested the transfer.
I/O operations are always performed by the operating system of the computer in
response to a request from an application program. The OS is also responsible for
suspending the execution of one program and starting another. Thus, for an I/O operation
involving DMA, the OS puts the program that requested the transfer in the Blocked state
initiates the DMA operation, and starts the execution of another program.
When the transfer is completed, the DMA controller informs the processor by sending
an interrupt request. In response, the OS puts the suspended program in the Runnable
state so that it can be selected by the scheduler to continue execution.
DMA Operation
Single Transfer:
Each trigger causes a single transfer. The module will disable itself when DMAxSZ number
of transfers has occurred. The DMAxSA and DMAxDA registers set the addresses to be
transferred to and from.
Block Transfer:
An entire block is transferred on each trigger. The module disables itself when this block
transfer is complete. This transfer halts the CPU, and will transfer each memory location one
at a time.
Burst-Block Transfer:
This is very similar to Block Transfer mode except that the CPU and the DMA transfer can
interleave their operation. This reduces the CPU to 20% while the DMA is going on, but the
CPU will not be stopped altogether.
Repeated Single Transfer:
The same as Single Transfer mode above except that the module is not disabled when the
transfer is complete.
Repeated Block Transfer:

Prepared By
Mrs. V.Rekha AP / MCA

38
The same as Block Transfer mode above except that the module is not disabled when the
transfer is complete.
Repeated Burst-Block Transfer:
The same as Burst Block Transfer mode above except that the module is not disabled when
the transfer is complete.

Registers in a DMA interface

DMA controller registers that are accessed by the processor to initiate transfer
operations. Two registers are used for storing the starting address and the word count. The
third register contains status and control flags. The R/W bit determines the direction of the
transfer. When this bit is set to 1 by a program instruction, the controller performs a read
operation, that is, it transfers data from the memory to the I/O device.
Otherwise, it performs a write operation. When the controller has completed
transferring a block of data and is ready to receive another command, it sets the Done flag
to 1. Bit 30 is the Interrupt-enable flag, IE.

Use of DMA controllers in a computer system.

14. Discuss briefly the bus arbitration methods. [JUN 2012]


A conflict may arise if both the processor and a DMA controller or two DMA
controllers try to use the bus at the same time to access the main memory. To resolve these

Prepared By
Mrs. V.Rekha AP / MCA

39
conflicts, an arbitration procedure is implemented on the bus to coordinate the activities of
all devices requesting memory transfers.
The device that initiates data transfers on the bus at any given time is called the bus
master. When the current master relinquishes control of the bus, another device can acquire
this status. Bus arbitration is the process by which the next device to become the bus
master is selected and bus mastership is transferred to it. The selection of the bus master
must take into account the needs of various devices by establishing a priority system for
gaining access to the bus.
There are two approaches to bus arbitration:

Centralized
Distributed.

Centralized arbitration
The bus arbiter may be the processor or a separate unit connected to the bus. A
basic arrangement in which the processor contains the bus arbitration circuitry.

A simple arrangement for bus arbitration using a daisy chain

The processor is normally the bus master unless it grants bus mastership to one of
the DMA controllers. A DMA controller indicates that it needs to become the bus master by
activating the Bus-Request line, BR; this is an open-drain line for the same reasons that the
Interrupt- Request line is an open-drain line.
The signal on the Bus-Request line is the logical OR of the bus requests from all the
devices connected to it. When Bus-Request is activated, the processor activates the BusGrant signal, BG 1, indicating to the DMA controllers that they may use the bus when it
becomes free. This signal is connected to all DMA controllers using a daisychain
arrangement.
The timing sequence of events for the devices as DMA controller 2 requests and
acquires bus mastership and later releases the bus. During Its tenure as the bus master, it
may perform one or more data transfer operations, depending on whether it is operating in
the cycle stealing or block mode.

Prepared By
Mrs. V.Rekha AP / MCA

40
After it releases the bus, the processor resumes bus mastership. This figure shows
the causal relationships among the signals involved in the arbitration process. Details of
timing, which vary significantly from one computer bus to another, are not shown.

Sequence of signals during transfer of bus mastership for the devices

Distributed arbitration:
Distributed arbitration means that all devices waiting to use the bus have equal
responsibility in carrying out the arbitration process, without using a central arbiter. A
simple method for distributed arbitration. Each device on the bus is assigned a 4- bit
identification number. When one or more devices request the bus, they assert the StartArbitration signal and place their 4-bit ill numbers on four open-collector lines, ARB0
through ARB3. The drivers are of the open-collector type. Hence, if the input to one driver is
equal to one and the input to another driver connected to the same bus line is equal to 0
the bus will be in the low-voltage state. In other words, the connection performs an OR
function in which logic 1 wins.

Prepared By
Mrs. V.Rekha AP / MCA

41

A distributed arbitration scheme

Assume that two devices, A and B, having ID numbers 5 and 6, respectively, are
requesting the use of the bus. Device A transmits the pattern 0101, and device B transmits
the pattern 0110. The code seen by both devices is 0111. Decentralized arbitration has the
advantage of offering higher reliability, because operation of the bus is not dependent on
any single device. Many schemes has been proposed and used in practice to implement
distributed arbitration. The SCSI bus is another example.
15. Describe about Standard I/O Interface
A number of standards have been developed for I/O Interface. IBM developed a they
called ISA (Industry Standard Architecture) for their personal computer known at the time
as PCAT. The popularity of that computer led to other manufacturers producing ISA
compatible interfaces for their 110 devices, thus making ISA into a de facto standard.
Some standards have been developed through industrial cooperative efforts, even
among competing companies driven by their common self-interest in having compatible
products.
There are three widely used bus standards, PCI (Peripheral Component
Interconnect), SCSI (Small Computer System Interface), and USB (Universal Serial Bus).
The way these standards are used in a typical computer system. The PCI standard defines
an expansion bus on the motherboard.
SCSI and USB are used for connecting additional devices, both inside and outside the
computer box. The SCSI bus is a high-speed parallel bus intended for devices such as disks
and video displays. The USB bus uses serial transmission to suit the needs of equipment
ranging from keyboards to game controls to internet connections. The interface circuit that
enables devices compatible with the earlier ISA standard, such as the popular IDE
(Integrated Device Electronics) disk, to be connected. It also shows a connection to an
Ethernet.

Prepared By
Mrs. V.Rekha AP / MCA

42

The Ethernet is a widely used local area network, providing a high-speed connection
among computers in a building or a university campus. A given computer may use more
than one bus standard. A typical Pentium computer has both a PCI bus and an ISA bus, thus
providing the user with a wide range of devices to choose from.
PCI (Peripheral Component Interconnect):
The PCI bus is a good example of a system bus. It supports the functions found on a
processor bus but in a standardized format that is independent of any particular processor.
Devices connected to the PCI bus appear to the processor as if they were connected directly
to the processor bus.
They are assigned addresses in the memory address space of the processor. Early
PCs used the 8-bit XT bus, whose signals closely mimicked those of Intel's 80x86
processors.
Data Transfer:
Most memory transfers involve a burst of data rather than just one word. The reason
is that modem processors include a cache memory. The PCI is designed primarily to support
this mode of operation. A read or a write operation involving a single word is simply treated
as a burst of length one. The bus supports three independent address spaces: memory, I/O,
and configuration. The first two are self-explanatory. The I/O address space is intended for
use with processors, such as Pentium, that have a separate I/O address space.

Prepared By
Mrs. V.Rekha AP / MCA

43

An example of a computer system using different interface standards

Device configuration
When an I/O device is connected to a computer, several actions are needed to
configure both the device and the software that communicates with it. The PCI simplifies
this process by incorporating in each I/O device interface a small configuration ROM
memory that stores information about that device. The configuration ROMs of all devices are
accessible in the configuration address space.
SCSI (Small Computer System Interface)
The acronym SCSI stands for Small Computer System Interface. It refers to a
standard bus defined by the American National Standards Institute (ANSI) under the
designation X3.131. In the original specifications of the standard, devices such as disks are
connected to a computer via a 50- wire cable, which can be up to 25 meters in length and
can transfer data at rates up to 5 megabytes/s.
14. Briefly explain about USB.

Prepared By
Mrs. V.Rekha AP / MCA

44
Universal Serial Bus (USB) is a simple and low cost mechanism to connect the
devices such as keyboards, mouse, cameras, speakers, printer and display devices to the
computer. The USB supports two speeds of operation, called low-speed (1.5 megabits/s)
and full speed (12 megabits/s). The most recent revision of the bus specification (USB 2.0)
introduced a third speed of operation, called high-speed (480 megabits/s).
The USB is quickly gaining acceptance in the market place, and with the addition of
the high-speed capability it may well become the interconnection method of choice for most
computer devices.
objectives:
Provide a simple, low-cost, and easy to use interconnection system that overcomes
the difficulties due to the limited number of I/O ports available on a computer
Accommodate a wide range of data transfer characteristics for I/O devices, including
telephone and Internet connections
Enhance user convenience through a "plug-and-play" mode of operation
Device Characteristics
The different kinds of devices may be connected to a computer cover a wide range of
functionality. The speed, volume, and timing constraints associated with data transfers to
and from such devices vary significantly. In the case of a keyboard, one byte of data is
generated every time a key is pressed, which may happen at any time. These data should
be transferred to the computer promptly.
Since the event of pressing a key is not synchronized to any other event in -8
computer system, the data generated by the keyboard are called asynchronous.
Furthermore, the rate at which the data are generated is quite low. It is limited by the speed
of the human operator to about 100 bytes per second, which is less than 1000 bits per
second.
Many computers have a microphone either externally attached or built in. The sound
picked up by the microphone produces an analog electrical signal, which must be converted
into a digital form before it can be handled by the computer. This is accomplished by
sampling the analog signal periodically.
Plug-and-play
The plug-and-play feature means that a new device, such as an additional speaker,
can be connected at any time while the system is operating. The system should detect the
existence of this new device automatically, identify the appropriate device-driver soft- ware
and any other facilities needed to service that device, and establish the appropriate
addresses and logical connections to enable them to communicate.
The plug-and-play requirement has many implications at all levels in the system,
from the hardware to the operating system and the applications software. One of the
primary objectives of the design of the USB has been to provide a plug-and-play capability.
USB Architecture
A serial transmission format has been chosen for the USB because a serial bus
satisfies the low-cost and flexibility requirements. Clock and data information are encoded
together and transmitted as a single signal. Hence, there are no limitations on clock

Prepared By
Mrs. V.Rekha AP / MCA

45
frequency or distance arising from data skew. Therefore, it is possible to provide a high data
transfer bandwidth by using a high clock frequency. As pointed out earlier, the USB offers
three bit rates, ranging from 1.5 to 480 megabits/s, to suit the needs of different I/O
devices.
To accommodate a large number of devices that can be added or removed at any
time, the USB has the tree structure. Each node of the tree has a device called a hub, which
acts as an intermediate control point between the host and the I/O devices. At the root of
the tree, a root hub connects the entire tree to the host computer. The leaves of the tree
are the I/O devices being served which are called functions in USB terminology.

Universal Serial Bus tree structure

The tree structure enables many devices to be connected while using only simple
point to point serial links. Each hub has a number of ports where devices may be
connected, including other hubs. In normal operation, a hub copies a message that it
receives from its upstream connection to all its downstream ports. As a result, a message
sent by the host computer is broadcast to ill VO devices, but only the addressed device will
respond to that message.
A message from an I/O device is sent only upstream towards the root of the tree and
is not seen by other devices. Hence, the USB enables the host to communicate with the I/O
devices, but it does not enable these devices to communicate with each other.
The USB operates strictly on the basis of polling. A device may send a message only
in response to a poll message from the host. Hence, upstream messages do not encounter
conflicts or interfere with each other, as no two devices can send messages at the same
time. This restriction allows hubs to be simple, Low-cost devices.

Prepared By
Mrs. V.Rekha AP / MCA

46

USB Split bus operations.

The mode of operation described above is observed for all devices operating at either
low speed or full speed. However, one exception has been necessitated by the introduction
of high speed operation in USB version 2.0. Consider the situation in Figure 5.34. Hub A is
connected to the root hub by a high-speed link. This hub serves one high-speed device, C,
and one low-speed device, D. Normally, a message to device D would be sent at low speed
from the root hub.
Addressing:
I/O devices are normally identified by assigning them a unique memory address. In
fact, a device usually has several addressable locations to enable the software to send and
receive control and status information and to transfer data. When a USB is connected to a
host computer, its root hub is attached to the processor bus, where it appears as a single
device. The host software communicates with individual devices attached to the USB by
sending packets of information, which the root hub forwards to the appropriate device in the
USB tree.
USB Protocol:
All information transferred over the USB is organized in packets, where a packet
consists of one or more bytes of information. There are many types of packets that perform
a variety of control functions. The information transferred on the USB can be divided into
two broad categories: control and data.
Control packets perform such tasks as addressing a device to initiate data transfer,
acknowledging that data have been received correctly, or indicating an error.
Data packets carry information that is delivered to a device. For example, put and
output data are transferred inside data packets.

Prepared By
Mrs. V.Rekha AP / MCA

47

USB packet format.

The four PID bits identify one of 16 different packet types. Some control packets,
such as ACK (Acknowledge), consist only of the PID byte. Control packets used for
controlling data transfer operations are called token packets. They have the format token
packet starts with the PID field, using one of two PID values to distinguish between an IN
packet and an OUT packet, which control input and output transfers, respectively.

Successive data packets on a full-speed or low-speed pipe carry the numbers 0 and
1, alternately. This simplifies recovery from transmission errors. If a token, data, or
acknowledgment packet is lost as a result of a transmission error, the sender resends the
entire sequence. By checking the data packet number in the PID field, the receiver can

Prepared By
Mrs. V.Rekha AP / MCA

48
detect and discard duplicate packets. High-speed data packets are sequentially numbered 0,
1, 2, 0, and so on.
16. Discuss I/O device

Keyboard:
The computer keyboard is used to enter text information into the computer, as when
you type the contents of a report. The keyboard can also be used to type commands
directing the computer to perform certain actions. In addition to the keys of the main
keyboard, keyboards usually also have a numeric keypad, a bank of editing keys, and a row
of function keys along the top. Laptop computers, which dont have room for large
keyboards, often include an fn key so that other keys can perform double duty.
Mouse:
The mouse pointing device sits on your work surface and is moved with your hand.
In older mice, a ball in the bottom of the mouse rolls on the surface as you move the mouse
and internal rollers sense the ball movement and transmit the information to the computer
via the cord of the mouse.
The newer optical mouse does not use a rolling ball, but instead uses a light and a small
optical sensor to detect the motion of the mouse by tracking a tiny image of the desk
surface. Optical mice avoid the problem of a dirty mouse ball, which causes regular mice to
roll a smoothly if the mouse ball and internal rollers are not cleaned frequently.
Scanners:
A scanner is a device that images a printed page or graphic by digitizing it, producing
an image made of tiny pixels of different brightness and color values which are represented
numerically and sent to the computer. Scanners scan graphics, but they can also scan pages
of text which are then run through OCR (Optical Character Recognition) software that
identifies the individual letter shapes and creates a text file of the page's contents.

Prepared By
Mrs. V.Rekha AP / MCA

49
Monitors:
CRT (Cathode Ray Tube), LCD (Liquid Crystal Display)
Printers:
Laser Printer, Inkjet Printer, Dot matrix printer
17. Discuss about various types of ROM.

[Jan 2013]

ROM stands for Read Only Memory. It is type of internal memory. The data and
instructions in ROM are stored by the manufacturer at the time of its manufacturing. This
data and programs cannot be changed or deleted after wards. The data or instructions
stored in ROM can only be read but new data or instructions cannot be written into it.
ROM stores data and instructions permanently. When the power is turned off, the
instructions stored in ROM are not lost. That is the reason ROM is called non-volatile
memory.
ROM is used to store frequently used instructions and data to control the basic input &
output operations of the computer. Mostly, frequently used small programs like operating
system routines and data, are stored into the ROM. When the computer is switched on,
instructions in the ROM are automatically activated. These instructions help the booting
process of computer.
* PROM
PROM is programmable ROM. Sometimes we may want to write some data on the ROM. In
such cases we use PROM. Data can be written on it using special equipment. It is important
to note that data can be written on PROM only once but it cannot be removed from the
PROM.
* EPROM
EPROM is programmable ROM from which data can be programmed and erased. Note that
programming and erasing is not limited to just one time. It is done using ultra violet light.
The downside to this that i requires additional hardware to program it. EPROM is now used
in most bios systems. This provides flexibility for the programmer.
* EEPROM
EEPROM is the next generation of ROM. It takes EPROM to the next level. As compared to
EPROM, EEPROM can be programmed using software technology. The user himself can
program the ROM using system software. The main advantage of this is you don't need
special hardware to program it. This saves the programmer a lot of money. This has become
the dominating force in the BIOS ROM market. Majority of the motherboards these days
come with EEPROM.
Anna University Questions
Part A
1. What is cache memory and write an advantage of using cache memory?

[Ref. No.: 12]

Prepared By
Mrs. V.Rekha AP / MCA

50
2. Define the term interrupt.

[Ref. No.: 21]

3. How will you handle multiple interrupts?

[Ref. No.: 32]

4. Where is a TLB located and what does it contain?

[Ref. No.: 40]

5. What is double data rate SDRAMs?

[Ref. No.: 42]

6. What are vectored interrupts?

[Ref. No.: 67]

89. What is a cycle stealing in DMA?

[Ref. No.: 89]

Part B
1. Explain the cache memory mapping functions with necessary block diagrams.
[Ref. No.: 7]
2. With an example illustrate the effects of different cache mapping techniques.
[Ref. No.: 8]
3. Define the term memory. Explain various to implement associative memory.
[Ref. No.: 10]
4. What is DMA? Discuss DMA controller and DMA transfer with diagram explain DMA
Operation.

[Ref. No.: 13]

5. Discuss briefly the bus arbitration methods.

[Ref. No.: 14]

6. With neat diagram, explain how virtual memory uses address translation method to
translate virtual addresses into corresponding physical addresses.

[Ref. No.: 9]

7. Discuss about various types of ROM.

[Ref. No.: 17]

Prepared By
Mrs. V.Rekha AP / MCA

Das könnte Ihnen auch gefallen