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Level I
10. Ans: (c)
Sol: A0 to A9 are used for line selection
A10 to A12 are used for chip selection of
RAM.
Output 4 (select code is 100) of 3 8 line
decoder is used to drive chip select of RAM.
A13 to A15 are used for chip selection of
Decoder.
A15 A14 A13 A12 A11 A10 A9 - - --A0
1
1 1 1 0 0
0----0
=F000H
0 0
0 0 0 0 0 0 0 0 0 0 0 = 0000H
1 1 1 1 1 1 1 1 1 1 1= 1FFFH
.
.
.
0 0
0 1
1----1
=F3FFH
A3
A4
A5
A6
A7
1
1
0
1
1
2 20 8
32
216 4
Chip select 0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
A2 can be either 0 or 1.
If A2 = 0, then Address Range becomes
F8 to FB.
If A2 = 1, then Address Range becomes
FC to FF.
The Range of Addresses for which the 8255
chip would get selected is F8 to FF.
0 1
0----0
1 0 1
1----1
=FD00H
=FDFFH
16.
Ans: (b)
A7
1
1
1
1
A6
1
1
1
1
A5 A4 A3 A2 A1 A0
0 1 0 1 0 0
0 1 0 1 0 1
0 1 0 1 1 0
0 1 0 1 1 1
Level II
04. Ans: (b)
Sol: Processor frequency =
fc
2
5MHz
2.5 MHz
2
= processor frequency
1
= 0.4s
2.5MHz
1
=E000H
01 - - - - - - - - 1
=EFFFH
17.
Sol:
Ans: (d)
Both
the
chips have active high chip select
inputs.
Chip 1 is
selected when A8 = 1, A9 = 0
Chip 2 is selected when A8 = 0, A9 = 1
Chips
b0
0
1
b1
1
0
b2
1
1
b3
Chip selection cs must be low means A15 high
a1=1 a0=0
A15=1 A13=1 A14=0
A15 A14 A13 0 0 0 0 0 0 0 0 0
1
0
1
0 0 0 0 0 0 0 0 0
0 0
Ans: (b).
Out put 2 of 38 Decoder is used for
selecting the output port. Select code is
010
A15 A14 A13 A12 A11 A10 -- A0
0 1
0
1
0 0 --- - 0
5000H
This mapping is memory mapped I/o
0 0 0 0
0
= (C000)H
Chapter-10
Level I
0----0
=0800H
1----1
=0BFFH
0----0
=1800H
1----1
=1BFFH
0----0
=2800H
1----1
=2BFFH
0----0
=3800H
20.
=3BFFH
1----1
Ans: (d)
1 1
1 0 0
0 =F8F8H
;
;
(2050H)
(2051H)
(L)
(H)
; (A) = 00H
; (L) (A) = 00H
; (H) (L) = 00H
; (HL) = 0001H
DAD
A, 00H
B
C
LOOP
on
; (PC)(HL) = 6979H
(PC) = E000H
(SP) = 23FEH
; (A) = 60H
The result in Accumulator is 60H
07.
Sol:
Ans: (b)
MVI B, 87H ; (B) = 87H
MOV A, B ; (A) (B) = 87H
JMP NEXT ; Jumps to NEXT
NEXT: XRA B ; (A)(A)=87H
Level -2
01. Ans: (c)
Sol: Compare instructions
(CMPC & CPI 3A) execution doesnt alter
content of operands involved in comparison.
And, ORA A instruction retains the value in A
02. Ans: (d)
Sol: Initial contents:
(SP) = F000H
(PC) = 2400H
For the execution of CALL E000, the
current contents of program counter i.e, 2400
is pushed into top of stack and then program
counter will be initialized with E000.
Because of pushing, contents of stack
pointer will be decremented by 2.
(B)=87H
; (A)=00H,(B)=87H,
S=0
JP START; Jumps to START
since S = 0
START: JMP NEXT
NEXT: XRA B ; (A) (A) = 00H
(B)= 87H
; (A) = 87H,
(B) = 87H, S=1
JP START ; Test fails since S=1
OUT PORT 2 ; (PORT 2)(A)
=87H
HLT
; Halted
08.
SP HL + SP
= 0000H + 200EH
= 200EH
XCHG HL & DE will exchange
DE 200EH
Ans: (b)
DAD
; (PC) 3000H--Target
Address
3000H: LXI H,3CF4H ; (HL) = 3CF4H
PUSH PSW
SUB 2 : INR A
; (TOS)(PSW)
; (SP) = EFFB
SPHL
; (SP)(HL) = 3CF4H
POP PSW
; (PSW)(TOS) and
(SP)
; (SP) = 3CF6H
RET
; (SP)
; (SP) = 3CF8H
PUSH
H
00 00
00
2010
00
200F
HL
00 00
POP
A
01H
and (SP)
PUSH
H=1 :L=0,255,254,253,---0
H=0 :
In first iteration (with H=255), the value in L
is decremented from 255 to 0 i.e., 255
times
In further remaining 254 iterations, the value in
L is decremented from 0 to 0 i.e., 256 times
DCRL instruction gets
executed for
[255 (254 256)]
65279 times
BC
00 00
00
200E
00
200D
00
200F
00
200D
PTR:ADD B ; (A)(A)=0AH+(B)
=04H
; This looping is continued till
; (B) becomes 0 due to
DCR B instruction
; (A) = 14H
ADI 03H ; (A) = 17H
HLT
At the end of program, Accumulator
contains 17H
14. Ans: (a)
Sol: STA 1234H is a 3Byte Instruction and it
requires 4 Machine cycles (Opcode fetch,
Operand1 Read, Operand2 Read, Memory
write). The Higher order Address (A15 A8)
sent in 4 machine cycles is as follows
Given STA 1234 is stored at 1FFEH
i.e.,
Address
Instruction
Address
(A15-A0)
1. Opcode
fetch
2. Operand1
Read
3. Operand2
Read
4. Memory
Write
1FFEH
Higher order
address
(A15-A8)
1FH
1FFFH
1FH
2000H
20H
1234H
12H
Ans: (a) .
B
04
A
03
Cy
0
initial values