Lab 9: Counters, Clock

Dividers, and Debounce

Circuits
Rebecca Sontheimer
ECEN 248-511
TA: Mehnaz Rahman
Date: November 12, 2014

Objective
The purpose of this lab is to better understand sequential circuits and counters. In
this lab, we introduce a binary counter that is built with pervious circuits and calls other
functions. This will also demonstrate the usage of binary counters on the Xilinx board
and use them to perform clock frequency division and I/O debouncing.

Design
Attached are the source codes for all of the circuits we simulated as well as the
.ucf code we had to write ourselves.

Results
Below are the waveforms of the various experiments throughout the lab and they
are labeled accordingly.
Waveforms of Experiment 1

Up Counter waveform

Switch Bounce

Conclusion
In conclusion, the code ran according to plan and I learned a bit more about the
inner workings of the circuit and this was the first time we experienced the real world
time delay and bounce in the circuit. You would think that a few nanoseconds of delay
here and there wouldnt matter, but it really starts to accumulate in a circuit. This means
that I need to be more careful in calculating these delays when I am designing circuits to
make sure that all of the information gets to the right place at the right time.

Post-Lab Deliverables
1)
2)
3)
4)

Source code included in the design section.

UCFs included in the design section.
Screenshots included in results.
Questions:
a) Experiment 1: Based on your measurements what frequency do you think the
input clock is running at?
i) 0 wave = 80 ns
ii) 1 wave = 160 ns
iii) 2 wave = 320 ns
iv) 3 wave = 640 ns
v) This insinuates that the clock is running at 12.5 MHz
b) Experiment 2: What is the frequency of the up-counter clock signal?
i) 100 MHz
c) How long is the reset interval for the up-counter?
i) 20 ns
d) How long does the up-counter hold the enable LOW for before allowing the
counter to run?
i) 20 ns
e) What is the maximum count value and what signal in the waveform can be used
to know exactly when the counter is going to roll-over?
i) The signal rolls over at the end of F (195 ns) and the signal to watch out for is
when carry 3 is high for 10 ns.
f) If a 50 MHz clock is used to drive the frequency divider in clock_divider, what
rate will the most significant bit of the divider oscillate at?
i) 50 MHz
g) Experiment 3: What does switch_bounce.v and .ucf describe?
i) These two files are just a program written to demonstrate what happens when
a switch is flipped. Switch_bounce.v is a simple program which is an input of
a button being pressed and an output of a high value. This demonstrates the
interference that occurs immediately after the button is pressed. This
interference is then fixed by the debounce file.

Feedback
1. I liked this lab because it was very informative and useful. I liked that the lab
manual was like a tutorial with step-by-step instructions. There was nothing that I
disliked.
2. All parts were very clear and informative.
3. No need to improve this lab.