Rebecca Sontheimer

ECEN 248-511
Pre-lab: Lab 5
1. Examples demonstrating how the circuit in Figure 5 adds and subtracts and how
the overflow detection circuit works.
2. Truth table and minimized boolean expression for a 1-bit wide, 2:1 multiplexer.
Truth Table for 2:1 Multiplexor:
S
A
B
F
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
K-Map for 2:1 Multiplexor:
AB\S
00
01
11
10

0
0
0
1
1

1
0
1
1
0

Minimized expression:
F = S * A + S * B
3. Gate-level schematics for the Addition/Subtraction unit, 1-bit and 4-bit 2:1
multiplexers, and final ALU design.
1-bit 2:1 MUX

4-bit addition/subtraction circuit

Rebecca Sontheimer
ECEN 248-511

4-bit 2:1 MUX

Final ALU design

Rebecca Sontheimer
ECEN 248-511

4. Table of ALU operations and suggested design modification.

Operations of the MUX within the ALU:
c0 c1 Op
0 0 Add
0 1 Sub
1 0 AND
1 1 AND