Reg. No.

Question Paper Code :

77903

M.E. DEGREE EXAMINATION, APRIL/MAY 2011

First Semester
Applied Electronics
VL 9212 VLSI DESIGN TECHNIQUES
(Common to M.E. VLSI Design)
(Regulation 2009)
Time : Three Hours

Maximum : 100 marks

Answer ALL questions.
Any missing data may be assumed suitably.
PART A (10 2 = 20 marks)

1.

Draw the transfer characteristics of PMOS depletion and enhancement type

MOSFETS.

2.

List the parameters which influence the threshold voltage of a MOSFET.

3.

An NMOS inverter has a ratio of 8 : 1. Write the lengths and widths of the
transistors in 90 nm technology.

4.

Draw the stick diagram of a static gate with an output expression

5.

The sheet resistance of a certain silicon slab of L =10 cms and W = 2 cms is
4
10 / . What is the resistance of this slab?

6.

The saturation current of a nMOSFET before scaling is 0.1 mA. What will be
this current when the device is scaled using constant electric field model with
=5 ?

7.

Realise a 2 : 1 MUX using transmission gates. Write the output expression

also.

8.

Draw a 4 bit, single phase CMOS- transmission gate dynamic shift register.

Y = A+B .

9.

Give 2 reasons
simulators.

as to why HDL simulators

are better

than

gate

10.

Verilog differs from languages like C and Pascal in 3 main aspects. What are
they?

level

PART B (5 16 = 80 marks)
11.

(a)

Explain the working of an enhancement type NMOSFET transistor with

the help of I ds , Vs , VGs and I ds , Vs , Vds characteristics.

(16)

Or
(b)

12.

(a)

(i)

Illustrate
the
PMOSFET.

body effect in case

of an

enhancement

(ii)

What is channel length modulation?

relevant figure and current equation.

(i)

Realize the expression

Y = A + BC using static CMOS logic. Verify
the circuit operation with the help of truth table.
(8)

(ii)

Derive an expression for rise time in case of a CMOS inverter.

Explain

the

type
(6)

same

with
(10)

(8)

Or
(b)

It is required to drive an off-Chip large capacitance load of 30 PF. Design

a suitable buffer which reduces the over all delay. Calculate the delay in
C g = 0 . 1 PF . Derive the equation used for the
terms of z. Assume 1
calculation. Give the Inverter ratios of all the stages.

13.

(a)

(i)
(ii)

(16)

Deduce an expression for dynamic power dissipated by a CMOS

inverter operating at a frequency f cycle per second.

(8)

Discuss the possible ways through which leakage power could occur
in a CMOS IC.

(8)

Or
(b)

(i)

Explain the working of a domino CMOS logic gate.

(8)

(ii)

Briefly explain the limits of scaling.

(8)

77903

14.

(a)

Explain the carry-look ahead adder, bringing the salient features of the
same. Use the CMOS circuit for your explanation.

(16)

Or
(b)

15.

(a)

(i)

What is Clock distribution? Explain briefly.

(ii)

Explain any two ways to improve clock distribution by physical

design.

Verilog supports 4 different abstraction models. What are they? Explain

them with appropriate examples.

(6)
(10)

(16)

Or
(b)

(i)

Explain Verilog logic system and Verilog Data types.

(6)

(ii)

What are the different post modes available in Verilog? Explain

with examples.

(6)

Write a Verilog code with comments for a D-Flip-Flop.

(4)

(iii)

77903