IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 59, NO.

2, FEBRUARY 2012

305

Inductorless Wideband CMOS Low-Noise Amplifiers

Using Noise-Canceling Technique
Ke-Hou Chen, Student Member, IEEE, and Shen-Iuan Liu, Fellow, IEEE

AbstractTwo inductorless wideband low-noise amplifiers

(LNAs) fabricated in a 65-nm CMOS process are presented. By
using the gain-enhanced noise-canceling technique, the gain at
noise-cancelling condition is increased, while the input matching
is maintained. The first work is a common-source LNA with
resistive shunt feedback. It achieves a maximum power gain of
10.5 dB, a bandwidth of 10 GHz, a noise figure (NF) of 2.73.3 dB,
and an IIP3 of
dBm. The power consumption is 13.7 mW
from a 1-V supply, and the area is 0.02 mm . The second work
is a common-gate LNA. It achieves a maximum power gain of
10.7 dB, a bandwidth of 5.2 GHz, a NF of 2.95.4 dB, and an IIP3
of
dBm. The power consumption is 7 mW from a 1-V supply,
and the area is 0.03 mm . Experimental results demonstrate
that the first LNA shows the largest bandwidth, and the second
LNA has the lowest power consumption among the inductorless
wideband LNAs.
Index TermsCMOS, gain-enhanced, inductorless, low-noise
amplifier (LNA), noise-canceling technique, wideband.

I. INTRODUCTION

ECENTLY, various high-speed wireless standards such

as GSM, DECT, Bluetooth, Wi-Fi, and GPS have been
developed. To satisfy the specific demands for each application, it is straightforward to integrate different wireless receivers
together on a chip; however, the required power consumption
and chip area will be huge. Therefore, it is desirable to have a
multi-standard receiver to meet all the above standards. A software-defined radio receiver [1] is one of the possible solutions
for multiple standards.
A wideband low-noise amplifier (LNA) is a key component
for a RF front-end in a multi-standard receiver. The wideband LNA must meet several stringent requirements, such
as broadband input matching to minimize the return loss,
sufficient gain to suppress the noise of a mixer, low noise
figure (NF) to enhance the sensitivity of a receiver, small die
area to reduce the cost, and low power consumption. There
are several methods that achieve wideband input matching for
wideband amplifiers. For example, the distributed amplifier
[2], the filter-type amplifier [3], the common-gate amplifier
[4], and the resistive shunt feedback amplifier [5]. However,
these methods may suffer from several disadvantages, such as
Manuscript received December 29, 2010; revised March 24, 2011; accepted
June 29, 2011. Date of publication August 22, 2011; date of current version
January 27, 2012. This work was supported in part by the NSC and MOEA.
The authors are with the Graduate Institute of Electronics Engineering and
Department of Electrical Engineering, National Taiwan University, Taipei,
Taiwan 10617 (e-mail: lsi@cc.ee.ntu.edu.tw).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2011.2162461

high power consumption, large chip area, and inadequate NF.

Moreover, the tradeoff between wideband input matching and
low NF makes the design difficult and complicated.
A noise-canceling technique [6] has been widely used to release the tradeoff in the wideband LNAs. The noise of the input
matching transistor is reduced through a feedforward path,
while the input impedance is matched simultaneously. The
amplifiers that adopt this technique have several advantages.
They accomplish wideband input matching, relative low NF,
sufficiently voltage gain, and high linearity. However, in order
to reduce the noise of the matching transistor, the gain of the
feedforward amplifier is limited. Therefore, the overall gain of
the LNA is limited when the noise is perfectly canceled.
To relax the tradeoff between voltage gain and NF, a gain-enhanced noise-canceling technique is exploited. By adding a
voltage amplifier, the voltage gain is enhanced, while the input
matching and noise-canceling characteristics are maintained.
Moreover, the degradation of NF and power consumption is
small. Therefore, the figure of merit (FOM) of the gain-enhanced noise-canceling LNA will be improved. Using inductors
to increase the gain or extend the bandwidth is effective in a
wideband LNA; however, it requires relatively large chip area
and accurate EM simulation. In this paper, the gain-enhanced
noise-canceling technique is used in the inductorless wideband common-source and common-gate LNAs, respectively.
This paper is organized as follows. Section II describes and
compares the conventional and gain-enhanced noise-canceling
techniques. The circuit analysis and design consideration for
these two LNAs are addressed. Section III shows the experimental results, and Section IV gives the conclusions of this
work.
II. CIRCUIT DESCRIPTION
A. Conventional Noise-Canceling Technique
The noise-canceling concept is to generate the noises with
the opposite phase-polarities in different paths, and cancel the
noises at the output. Since the cancellation is irrelevant to the
input impedance, this technique allows for simultaneously noise
cancellation and impedance matching. Fig. 1 shows a simplified
resistive shunt feedback LNA by using a conventional noisecanceling technique [6]. This LNA is composed of a transistor
, and a feedforward voltage amplifier with
, a resistor
). To have a maximal power transfer,
a gain of
is designed to match to the source
the input impedance
. Neglecting the loading effect at node
impedance,
, where
is the transconductance
is approximated to
. However, the NF is not optimized
of the input transistor
in this condition. To observe the noise at the output, modeling

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Fig. 1. Simplified resistive shunt feedback LNA using a conventional noisecanceling technique [6].

Fig. 3.

versus frequency.

by
, the reduction of bandwidth is unavoidable. Therefore,
there exists a tradeoff between gain and bandwidth, even if the
input matching and noise cancellation are both completed.
B. Gain-Enhanced Noise-Canceling Technique
Fig. 2. Simplified resistive shunt feedback LNA using the gain-enhanced
noise-canceling technique.

the noise of the input transistor

by a current source
between the drain and source. The noise current
generates the noise voltages
and
at nodes X and Y with
the same phase polarity. On the contrary, the signal voltages,
and
, have the opposite-phase polarities. Therefore, the
output noise voltage,
is given as
(1)
To have a zero
plifier should be

Fig. 2 shows a simplified resistive shunt feedback LNA by

using the gain-enhanced noise-canceling technique. An additional voltage amplifier
with a gain of
is
exploited in the upper feedforward path. The purposes of this
gain-enhanced noise-canceling technique are two-folded; one
is to increase the overall voltage gain,
, and the other is to
match the phase delay for two paths. By using the similar calculations, the output noise voltage is canceled, when
(4)
Therefore,

equals to

, the gain of the feedforward voltage am(5)

(2)

equals to
, the noise of the
It shows that when
input transistor
is canceled at the output. Despite the noise
of
itself, any noise current source that flows between the
drain and source of
will be canceled as well.
For the signal voltage, the overall voltage gain
can be
calculated when
is canceled, i.e.,

(3)
The cancellation is independent of the input matching condition.
i.e.,
. For simultaneous input matching and
noise cancellation,
equals to
.
From (2) and (3),
is increased with
, and
is in
proportional to
. However, a large
induces noise and degrades the bandwidth. Although the noise of
will be divided

When
equals to
. By observing (3) and (5), the overall voltage gain is amplified by
,
i.e.,
.
Even though the voltage gain is enhanced, there is still a
tradeoff between gain and bandwidth. For a multi-band wireless
receiver, the power gain can be provided by the following IF amplifier; therefore, a wideband LNA is to designed to achieve a required bandwidth with a moderate voltage gain. In this topology,
the bandwidth is dominated by the resistors
, and the parasitic capacitances at nodes X, Y. As a result, the advantage of
gain enhancement by
can be converted to bandwidth extension by choosing a small size of
and
. Therefore, the
increased gain can be used to relax the tradeoff between gain
and bandwidth, and thus makes the wideband amplifier design
more flexible.
Fabricated in a 65-nm CMOS process, the large
and
(
GHz) are beneficial to the wideband LNA. The simulation of the NMOS transistors is based on the compact model of

CHEN AND LIU: INDUCTORLESS WIDEBAND CMOS LOW-NOISE AMPLIFIERS

307

Fig. 4. First noise-canceling LNA.

BSIM4V4.5.0 provided by the foundry. Fig. 3 shows that for

nm,
um, and
V,
is lower than 0.5 dB within 12 GHz. Details about the
noise modeling of the process are found in [7].

a voltage gain of
. The amplifier
is implemented in
a common-gate configuration by
with a voltage gain of
.
and
are expressed as
(6)

C. Circuit Analysis of First LNA

Fig. 4 shows the first noise-canceling LNA. It consists of
is a 50a noise-canceling stage and an output buffer.
source impedance, which connects the input pad via a large capacitor
. In the noise-canceling stage,
is a shunt
feedback resistor, which is used for wideband matching, and for
sensing the signal and noise of input transistor
.
and
are used to combine the signal and subtract the noise of
.
and
are load resistors. The output buffer
will be discussed later. To subtract the noise at the drain of
, the polarities of the signals at the drains of
and
should be in-phase. If
is implemented in a commonsource configuration, the signals at the drains of
and
will be out-of-phase. Therefore, a subsequent stage is needed to
convert the polarities. In this way, the linearity decreases, and
power consumption increases. Hence, a common-gate configuration is chosen rather than a common-source one in the first
LNA.
The input impedance
is equal to the parallel combination of the input parasitic capacitance
and resistance
.
is the gate-to-source capacitances of
, and
is
. At low frequency,
the input matching is achieved by setting
to 50 . As the
frequency goes high,
will deviate from 50 because the
admittance of
increases as well. Therefore, to keep
as
small as possible is important for wideband input matching. In
the first LNA, by adding
, the part of the current of
flows into
, which increases
. As a result, for a given
, the required size of
is small, which reduces
and maintains a wideband input matching.
In (4), the cancellation of noise depends on the ratio of
to
. Analogous to the schematic in Fig. 3, the amplifier
is
implemented in a common-source configuration by
with

(7)

(8)
is the input resistance of the buffer.
and
are the equivalent load resistances at the drain of
and
.
is approximated to the ratio of the resistance
at the drain to the resistance at the source of
.
Upon cancellation, the ratio of
to
is
. If
is large enough, the noise-canceling
condition becomes

where

(9)
Therefore, according to (5), the voltage gain of the noise-canceling stage can be calculated as

(10)
, if
dB, the required
is reFor a fixed
duced by a half. As a result, to satisfy (9), the required
for noise cancellation can be reduced, which indicates the reduction of power consumption or the size of
. To evaluate
the gain enhancement by
, the simulated voltage gains of
each stage of the first LNA are shown in Fig. 5.
is the
voltage gain of the output buffer, and
is the overall gain.
The currents of the noise-canceling stage and the buffer are 8

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In (13)(17), if

, the ratios of
are described as
and
, where
represents
and
. Therefore, it is observed
that
contributes relatively low noise. In addition, since
, the noise in the
noise-canceling stage is primarily contributed by
.
The reduction of
and
are achieved by lowing
and
. As discussed, the need of large
and
for noise cancellation is reduced compared with conventional noise-canceling technique, hence the total noise factor is
also reduced. On the other hand, as shown in (14), although
induces extra noise, its noise contribution will be reduced
by
, where
is enhanced by adding
. Moreover, the noise current that flows into
will be canceled
since they are modeled as a part of the noise current,
.
Note that
is biased with a current mirror, where the noise
from the bias of
is bypassed to ground with a large on-chip
capacitor. In summary, the additional feedforward amplification
increases the design flexibility with small noise contribution and
power consumption, which is the main advantage of the first
LNA.
and

Fig. 5. Voltage gain of the first LNA.

mA and 5.3 mA, respectively. It is shown that a 4-dB improvement of voltage gain is obtained by adding
.
Modeling the channel thermal noise of
by a current
source between drain and source,
, whose power spectral
density is defined as

to

D. Circuit Analysis of Second LNA

(11)
is a noise parameters and
, where
is the
channel conductance for
. For deep-submicron MOSFETs, the value of exceeds unity in saturation and may become 23 under some biasing conditions, and is often less
than unity [8]. The noise factor
can be
derived by
(12)
where
and
are the output voltage and current at
the noise-canceling stage;
and
are the voltage
gain and transconductance of the noise-canceling stage. By
noise cancellation, the noise of
is largely reduced;
hence the noise of the noise-canceling stage is contributed by
, and
. Therefore, the noise
factor of each device is expressed as
(13)
(14)

(15)

(16)
(17)

The second noise-canceling LNA is shown in Fig. 6. In

the noise-canceling stage,
is an input transistor, which
provide wideband input matching and voltage gain. For input
matching, the input impedance
.
and
are used to combine the signal and subtract the
noise of
.
and
are load resistors.
In general, the source of the input transistor in a common-gate
configuration is connected with a current source or an inductor
to provide a dc path. However, a current source induces noise at
the input and consumes voltage headroom; an inductor increases
the chip area and results in narrow-band input matching. Here,
the dc path is provided by an external bias-T, which also provides a bias voltage for
. Because of the high capacitance,
assume that
in Fig. 6 is ac-shorted, and the bypass capacitors
are ac-shorted to ground. The equivalent circuit that depicts the noise cancellation is shown in Fig. 7.
generates a noise current
, whose power spectral density
is defined as
. Because
flows into the
source but out of the drain of
, the noise voltages are in opposite phase. Therefore, the output noise current
caused
by the source of
can be subtracted at the drain of
,
which is expressed as
(18)
. Ideally,
is zero, which
where
means that it is canceled when
. For
the signal path, the voltage at the drain and source of
are
in-phase, resulting in the summation of signals at the output.
Therefore,
is derived as
(19)

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309

Fig. 6. Second noise-canceling LNA.

to

are

and
. In noise-canceling
condition,
. Here,
is about 5 and
is larger than 1, which
indicates that the noise contribution of
is smaller than
and
.
The amplifiers
and
in Fig. 3 are implemented in
common-source configurations with voltage gains of
and
, respectively
Fig. 7. Noise-canceling stage of the second LNA.

(26)
In contrast, if the signal and noise are combined without
,
the noise contributed by
and the equivalent transconductance becomes
(20)
(21)
Comparing (18)(21), without
, the noise-canceling condition is simplified to
. However, the equivalent
transconductance is reduced, which results in a lower gain and
a higher noise.
The noise factors of the other devices are then calculated according to (12)
(22)

is the output impedance of

and
, which
.
is the production of
and
. The simulated voltage gains of each
stage of second LNA are shown in Fig. 8. The currents of the
noise-canceling stage and the buffer are 4 mA and 3 mA, respectively. It is shown that a 5-dB improvement of voltage gain
is obtained by adding
. Although transistor
provides
additional gain, the bandwidth is limited by the miller effect.
and
construct capacitive peaking
structure, which increase the input pole magnitude by a factor
of
[9]. In summary,
increases the
gain and decreases the noise with a small bandwidth and noise
degradation, which is the main advantage of the second LNA.
At low frequency, assuming input is matched and
, the ratio of the gain of the two noise-canceling stages
is expressed as
is

(23)
(24)
(25)
is the
By observing (22)(25), it is shown that
smallest, and hence
are the main noise
sources in the second LNA. The ratios of

(27)
Equation (27) shows that the second LNA has a larger gain
since the production of
and
is larger than that of
and
by four times. For example, if
mS
mS, and
, the ratio

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 59, NO. 2, FEBRUARY 2012

Fig. 8. Voltage gain of the second LNA.

Fig. 9. Micrographs of (a) the first and (b) the second LNA.
TABLE I
DESIGN PARAMETERS

is about 1.5. Therefore, the second LNA achieves the same gain
as the first LNA with less power consumption.
E. Output Buffer
In order to achieve wideband output matching, the source
follower is commonly incorporated in wideband amplifier.
However, for low-voltage applications, source follower suffers
from poor driving ability and consumes a large voltage headroom. A resistive shunt feedback output stage is used in the two
LNAs, which is composed of
and
. The voltage
gain
and output resistance
is calculated as
(28)
(29)
is designed to be 50 . It not only provides 50- wideband
output matching, but also increases the overall gain. The design
parameters are summarized in Table I.
III. EXPERIMENTAL RESULTS
The LNAs have been fabricated in a 65-nm CMOS process.
The die micrographs are shown in Fig. 9. The areas of the first
and the second LNA are 0.02 mm and 0.03 mm , respectively.
To avoid the parasitic inductances of bondwires, the dc probes
are used. However, the chip area is expanded by the requirement
of dc probes, and hence cause extra path between the buffer and
output pad. Therefore, EM simulation is utilized for concerning
the parasitic effects on this path.

Fig. 10. Measured and simulated S11, S22 of the first LNA.

On-wafer measurements are performed on a probe station. S

parameters and IIP3s are measured using Agilent N5245A network analyzer, and the NFs are measured with Agilent E4440A
spectrum analyzer. Fig. 10 demonstrates the measured and simulated S11 and S22 of the first LNA. The measured S11 and S22
are below
dB up to 10 GHz, which is similar to the simulation results. S21 and NF are shown in Figs. 11 and 12. The measured maximum S21 is 10.5 dB, and the measured NF is 2.73.3
dB with a
dB bandwidth of 10 GHz. Two-tone testing is
performed with 1-MHz spacing for third-order inter-modulation
distortion, which is shown in Fig. 13. At 5 GHz, the measured
IIP3 is
dBm. The group delay based on the measured S parameter is shown in Fig. 14. It shows a low group delay ripple
of
-ps across the whole band of operation. The measurement
results show that with good input matching and moderate gain,
the first LNA achieves a low NF and wide bandwidth.
For the second LNA, the measured S22 is below
dB up
to 10 GHz, but S11 is higher at lower frequencies, as shown
in Fig. 15. Figs. 16 and 17 show that the measured maximum
S21 is 10.7 dB, and the measured NF is 2.95.4 dB with a
dB bandwidth of 5.2 GHz. The input impedance and voltage
gain are affected by
by previous analysis. Therefore, the

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Fig. 11. Measured and simulated S21 of the first LNA.

Fig. 12. Measured and simulated NF of the first LNA.

311

Fig. 14. Measured and simulated group delay of the first LNA.

Fig. 15. Measured and simulated S11, S22 of the second LNA.

Fig. 16. Measured and simulated S21 of the second LNA.

Fig. 13. Measured IIP3 at 5 GHz of the first LNA.

discrepancy between the simulated and measured S11 and S21

could be caused by the process variation and inaccuracy of modeling of
and
, which deviate the source voltage of
from the designed value. Because input impedance is not
well-matched near 1 GHz, the NF is obviously higher at lower

frequency band. The IIP3 measured at 1 GHz is

dBm, which
is shown in Fig. 18. The group delay is shown in Fig. 19, which
ranges from
to 28 ps.
Table II shows the performance summary of this work and
compares with previous published wideband LNAs. For comparison, the voltage gains are converted to power gains by a

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TABLE II
PERFORMANCE SUMMARY AND COMPARISON

Fig. 17. Measured and simulated NF of the second LNA.

6-dB subtraction. The gains and power consumption of the two

LNAs with and without the buffers are changed from 10.5, 10.7
dB to 8, 8.3 dB, and from 13.7, 7 mW to 8, 4 mW. To compare
the performances among the wideband LNAs, the FOM defined
in [15] is adopted.

(30)
is the power consumption, and the maximum power
where
gain and minimum NF are calculated in (30). The conventional

Fig. 18. Measured IIP3 at 1 GHz of the second LNA.

noise-canceling LNA [6] is included for comparison. The FOMs

of the LNAs in [14] and [15] are excellent by using inductors to
perform wideband matching and extend the bandwidth. A noise/
distortion-canceling common-gate LNA was implemented in
[17]. Comparing with this LNA [17], the proposed second LNA
has advantages in high bandwidth, small area, and low supply
voltage. Firstly, to minimized the second-order distortion, an additional PMOS transistor and large (
pF) coupling capacitors in the input stage are needed in [17], hence its bandwidth

CHEN AND LIU: INDUCTORLESS WIDEBAND CMOS LOW-NOISE AMPLIFIERS

Fig. 19. Measured and simulated group delay of the second LNA.

is limited, and the chip area is increased. Secondly, to minimize the degradation of linearity caused by the output stage,
the output matching is achieved by stacking a transistor and
a resistor, therefore extra voltage headroom is needed. Exclusive of [17], the first LNA shows the highest bandwidth and the
best FOM in the inductorless LNAs. The power consumption
without the output buffer of the second LNA is 4 mW, which is
the lowest among them.
IV. CONCLUSION
Two inductorless wideband 65-nm CMOS LNAs by using the
gain-enhanced noise-canceling technique are illustrated. For the
first LNA, the measured maximum power gain is 10.5 dB, the
NF is 2.73.3 dB, the
dB bandwidths is 10 GHz, and the
measured IIP3 at 5 GHz is
dBm. The core area is 0.02
mm , and it consumes 13.7 mW from a 1-V supply. For the
second LNA, the measured maximum power gain is 10.7 dB,
the NF is 2.95.4 dB, the
dB bandwidths is 5.2 GHz, and the
measured IIP3 at 1 GHz is
dBm. The core area is 0.03 mm ,
and it consumes 7 mW from a 1-V supply. In addition to the enhancement of gain, the proposed LNAs achieve wide bandwidth
with small power consumptions and chip area. The gain-enhanced noise-canceling technique improves the FOM compared
with previous wideband LNAs; hence it is suitable for wideband
and multi-standard applications.
ACKNOWLEDGMENT
The authors thank UMC, Hsinchu, Taiwan, for fabricating the
chips and Nano Device Laboratories (NDL) for measurement
support.
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Ke-Hou Chen was born in Taipei, Taiwan, in 1980.

He received the B.S. and M.S. degrees in electrical
engineering from National Chi Nan University,
Nantou, Taiwan, in 2002 and 2004, respectively.
He is currently working toward the Ph.D. degree
in electronics engineering from National Taiwan
University, Taipei, Taiwan.
His current research interests are RFICs and power
integrated circuits.

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 59, NO. 2, FEBRUARY 2012

Shen-Iuan Liu (S88M93SM03F10) was born

in Keelung, Taiwan, 1965. He received the B.S. and
Ph.D. degrees in electrical engineering from National
Taiwan University (NTU), Taipei, Taiwan, in 1987
and 1991, respectively.
During 19911993, he served as a second lieutenant in the Chinese Air Force. During 19911994,
he was an Associate Professor in the Department of
Electronic Engineering, National Taiwan Institute of
Technology. He joined the Department of Electrical
Engineering, NTU, in 1994, where he has been a
professor since 1998. Now, he is a distinguished professor in NTU since Aug.
2010. His research interests are in analog and digital integrated circuits and
systems.
In 20042008, Dr. Liu has served as chair of the IEEE SSCS Taipei Chapter,
which achieved the Best Chapter Award in 2009. He has served as general chair
of the 15th VLSI Design/CAD Symposium, Taiwan, (2004) and as Program
Co-chair of the Fourth IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, Fukuoka, Japan, in 2004. He was the recipient of the Engi-

neering Paper Award from the Chinese Institute of Engineers in 2003, the Young
Professor Teaching Award from MXIC Inc., the Research Achievement Award
from NTU, and the Outstanding Research Award from National Science Council
in 2004. He has served as a technical program committee member for ISSCC
in 20062008, IEEE VLSI-DAT in 20082010, and A-SSCC in 20052010. He
also served as the technical program committee co-chair and chair for A-SSCC
2010 and 2011, respectively. He was an Associate Editor for IEEE JOURNAL OF
SOLID-STATE CIRCUITS in 20062009 and a Guest Editor for IEEE JOURNAL OF
SOLID-STATE CIRCUITS Special Issue in 2008 Dec. He was an Associate Editor
for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS in
20062007. He was an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMSI: REGULAR PAPERS in 20082009. He was the Editorial Board
of Research Letters in Electronics in 20082009. He is also an Associate Editor for IEICE (The Institute of Electronics, Information and Communication
Engineers) TRANSACTIONS ON ELECTRONICS from 2008. He is an Associate
Editor for ETRI Journal, and also an Associate Editor for Journal of Semiconductor Technology and Science, Korea, from 2009. He is a Fellow of IEEE and
a member of IEICE.