MU Sch Tek teller} CTE OH (Las cyi(. Technical Publications Pune’MOSFET RAM cell - Dynomic RAM cell - ROM organization - PROM - EPROM - EEPROM - EAPROM - Programmable logic devices - Programmable Logic Array (PLA) - Programmable Array Logic (PAL), Field Programmable Gate Arrays (FPGA). (1-1) to (1-78) Chapter -2 Boolean Algebra and Switching Functions (2-1) to (2-72) Chapter -3 Logic Gates (3-1) to (3-98) Chapter -4 Combinational Circuits (4- 1) to (4- 142) Chapter - 5 Flip-Flops (6-1) to (5-36) Chapter -6 Counters (6-1) to (6 - 28) Chapter-7 Analysis and Design of Clocked Sequential Circuits (7-1) to 7-74) Chapier-8 Registers (@-1)t0(6-%8) Chapler-9 Asynchronous Sequential Circuits (8-1) to (9-38) Chapter- 10 Hazards u (10-1) 6) Chapter- 11 Memory Devices (11 1)to (11-34) ‘Appendix -A Algorithmic State Machines (ASN) (A= 1) to (A-68) Appendix -B Typical Digital ICs ‘Appendix -C Data Sheets For Commanly Used Digital ICs Chapterwise University Questions wilh Answers Best of Technical Publications As per Revised Syllabus of Anna University - 2006 Course Semester-IIl [ECE] Electrical Machines Environmental Science and Engineering Electronic Circuits - 1 (4)id Digital Electronics ISBN 9788184314113 All rights reserved with Technical Publications, No part of this book should be reproduced in ony form, Electronic, Mechanical, Photocopy or any information storoge ond retrieval system without prior permission in wating, from Technical Publications, Pune. Published by = ‘Technical Publications Pune” #1, Amit Residency, 412, Shaniwar Peth, Pune - 411 030, India. Printer : ‘Nee DTP Sore 10 Schated Road, Reeve AEE ES OY Ss Se EOTable of Contents Chapter-1 Number Systems — 1.1 Introduction 1.2 Decimal Number System ........008 1.3 Binary Number System... 1.4 Octal Number System....... 1.5 Hexadecimal Number System 1.6 Counting in Radix (Base) r... 1.7 Number Base Conversions . : 1.7.4 Binary to Octal Conversion ........ 0. e ce 1.7.2 Ootal to Binary Conversion... 0.0.6 cece rere 1.7.3 Binary to Hexadecimal Conversion 1.7.4 Hexadecimal to Binary Conversion . 1.7.5 Octal to Hexadecimal Conversion . 1.7.6 Hexadecimal to Octal Conversion... cece ee eee eee eerie 1.1.7 Converting any Radix to Decimal... a peerterenery ed) 1.7.8 Conversion of Decimal Numbers to any Radix Number ...........- eee 1-10 1.7.8.1 Successive Division for Integer Part Conversion . 1-44 1.7.82 Successive Multiplication for Fractional Part Conversion, 00 1-13 1.7.9 Radix Conversion Algorithms 1.8 Complements... 1.8.1 1's Complement Representation ........ weet reer 119 1.8.2 2's Complement Representation... Seen eeeeeesereeery| 9 1.8.3 1's Complement Subtraction , 1.8.4 2s Complement Subtraction 1.9 Signed Binary Numbers.1.10 Binary Arithmetic. 1.11 Hexadecimal Arithmetic 1.12 Binary Code ..... soe 1.12.1 Classification of Binary Codes 1.12.2 BCD (8-4-2-1) 4.42.24 BCD Addition. . 1.12.22 BCD Subtraction 1.12.3 Other 4-Bit BCD Cades 1.12.3,1 242-1 Code 1.1232 Other Codes 1.12.4 Excess-3 Code 1.12.4.1 Excess:3 Addition 4.124.2 Excass-3 Subtraction 112.5 Gray Code... 11254 ‘Advanage of Gray Code 1.12.52 Gray-to-Binary Conversion... 1.12.5.3 Binary to Gray Conversion 1.12.6 Five Bit Codes... : 4.12.7 Biquinary Code 1.12.8 Alphanumeric Codes 1.12.8.1 ASCII 14282 BBCDIE eee 1.12.8.3 Hollenith Code. . 4.12.9 Error Detecting and Correcting Codes... 2. eee. 1.12.9.1 Parity Bit 1.12.9.2 Block Parity, . 1.12.9.3 Hamming Cade: Solved Examples . Review Questions .. Chapter 2! Boolean Algebra and suiting ui 2.1 Introduction ..... 2.2 Fundamental Postulates of Boolean Algebra, 2.3 Laws of Boolean Algebra... 2.4 Basic Theorems and Properties... ott CBRE RR,2AM Dually... ceeeceeceeeeee 2.4.2 Basic Theorems. . 2.4.3 DeMorgan's Theorems .. 2.4.4 Consensus Theorem 2.4.5 Dual of Consensus Theorem, .. . wen 2.5 Boolean Expression and Boolean Function... 2.5.1 Sum of Product Form 2.5.2 Product of Sum FOr... 66s eee eee eee 2.6 Canonical Form (Standard SOP and POS Forms) 2.6.1 Standard SOP Form or Minterm Canonical Form. 262 Standard POS Form or Maxterm Canonical Form... 26.3 Converting Expressions in Standard SOP or POS Forms. 2.8.4 M-Notations : Minterms and Maxterms oo... css. 2.6.5 Complements of Canonical Formulas . . 2.7 Minimization of Boolean Expression 2.8 Karnaugh Map Minimization ... 2.8.1 One-Variable, Two-Variable, Three-Variable and Four-Variable Maps. . cece 2B 2.8.2 Plotting a Kamaugh Map....... ceeveteeseyces cee B2T 28.2.1 Representation of Truth Tale on Kamaugh Map. . . 2-28 2.8.2.2 Representing Standard SOP on K-map ee » 2-29 2.8.2.3 Representing Standard POS on K-map . . - . 6 2630 2.8.3 Grouping Cells for Simplification ....... 6.6. cseee eet eee ester e eens ee Red 2.8.3.1 Grouping Two Adjacent Ones (Pair). BH 2.8.3.2 Grouping Four Adjacent Ones (Qusd) . Loe 2-4 2.8.3.3 Grouping Eight Adjacent Ones (Qrtet).. . . ce 636 2.8.4 Simpification of Sum of Products Expressions (Minimal Sums). 2-37 2.85 Essential Prime implicants... ceeeee ere ee Bo 2.8.6 Simplification of Product of Sums Expressions (Minimal Products) ............0...2+48 2.9 Don't Care Conditions... 2.9.1 Describing Incomplete Boolean Function . 2.9.2 Don't Care Conditions in Logic Design .. .2.10 Minimization of Incompletely Specified Functions .... 2.11 Limitations of Karnaugh Map............ 2.12 Five Variable K-map .. Solved Examples .. Review Questions .........:00 wad 40 Chapter -3 Logic Gates (3-1) to (3 - 98) 3.1 Introduction 3.2 Logical Operators. 3.2.1 Logical Operator NOT/INVERT .. 3.22 Logical Operator AND 9.208 Logical Operator OR Sxcconssveaconcnmunmaeeene em 3.3 Logic Gates... ST RENO CN wecrasscarsmmmnesaniramomsaseee sna ee BAZAND Gale ec cece ccc ce cece sesessseeecsetessesessseeees ded 3.4.3 The OR Gate... cee cece ceeeseeeteceeseeseeees essanes ASE 3.3.4 The NAND Gale 0c e cee eee cere tneeeeese eset eetererereee Ged 3.3.5 The NOR Gale... 3.3.6 The Exclusive-OR Gate.......0...0..2 re MERC 3.3.7 The Exclusive-NOR Gale... 815 3.3.8 Boolean Functions for Logic Gates ........ it amc Ie 3.3.9 Alternative Logic-Gate Representation .. _ 3.3.10 Universal Gates... zi vsgeaeanseneenes oxeree BRIE SHAOUNANDGOB Ecce steee HOMEY ot é 3-19 3.3.10.2 NOR Gate ; Be ma: 3:22 3.8.11 Conversion of ANDIORINOT Logic to NANDINOR Logic using Graphical Procedure... occ... rca ceceeee 3-24 3.4 Implementations of Logic Functions using Gates .....0..ccccssccseanned ~ 29 3.4.1 Implementation of SOP Boolean Expression ....................200008 3-29 3.4.2 Implementation of POS Boolean Expression . 3-29 3.4.3 NAND-NAND Implementation gee ENR ACRN: aH 344A NORWNOR Implementation ........0.eeseseersieseceseeceeesecseceevecsee dM vit) SVE3.5 Multilevel Gate Implementations... ee 3.6 Multilevel NAND and NOR Implementations ... 3.7 Multiple Output Implementations ..... 3.8 Logic Families ...... 3.8.1 Logic Levels, 3.8.2 Definition of Parameters ...... 5.6.2.4 Curon! and Vlage Parana. (3.8.2.2 Noise Margin 3.8.2.3 Output Switching Times ‘3.8.2.4 Propagation Delay 38.25 Fan-OulandFanin. 3.8.2.6 Power Dissipation 3.8.27 Speed Power Product (Figure of Merit) . - 3.8.3 Transistor Transistor Logic (TTL) ....... seen ceecseveeevess S-51 38.3.1 Muliple-Emitter Transistor . . 1s. 351 38.3.2 TolemPole Output... . . ee ORD ‘3.8.3.3 Input and Output Currents-Fan-out . . 3-55 38.3.4 Wired Logic cee : cae cee B88 3.8.3.5 Threo-stata Output TTL - wee . 3-62 38.8.6 Standard TTL Characteristies ee ee HOT 38.3.7 High-Speed(H) and LowPower(L}TTL, ee ee 389 3.8.3.8 Sehotthy TTL . : 22. 37 34.3.9 Fast (F)TTL. . eee ee 38.310 Camprson of TL Series Cheeta : es 3-74 3.8.4 CMOS Logic 3.84.1 CMOS Inverter 384.2 CMOS NAND Gate... 384.3 CMOS NOR Gate 38.4.4 Performance. 3.8.5 Interfacing CMOS and TTL. Families. 38.5.1 TTL Driving CMOS: 3.8.5.2 CMOS Driving TTL ET SERPS RE ET eT es et3.8.6 Comparison of CMOS and TTL Famili Solved Examples ..... Review Questions.... Chapter - 4 Combinational Circuits 4.1 Introduction .... 42 Design Procedure 4.3 Adders...... AQAOAGIGT occ eee eee ee teen ee eee nee eter tee 4.3.2 FullAdder... . ete eee eens 4.4 Subtractors..... 4.4.4 Half-Subtractor 4.4.2 Full-Subtractor 4.5 Serial Adder/Subtracto! 4.6 Parallel Adder... 47 Parallel Subtractor ... 4.8 Parallel Adder/Subtractor. 4.9 Garry Look Anead Adder 4.10 BCD Adder... 4.11 BCD Subtractor.. 4.11.19's Complement... 4,11,2 9's Complement Subtraction oo... 0. .scseseseeee esse ereereeerereeeeen ers 4.11.3 10's Complement Subtraction _ 4.12 Magnitude Comparator teoenne 4.12.1 IC 745 ( 4-bit Comparator)... -. 0s weet tetas ee eee 4634 4.42.2 1C 74X682 (B-bit comparator)... oe e cece eeeeeeeeeeteeeeeeeee 4285 4.13 Multiplexers. 4.13.1 The 74XX151 8 to 1 Multiplexer 4.19.2 The 74XX187 Quad 2-Input Mutiplexer. 4.19.3 The 74XX153 Dual 4 to 1 Multiplexer. 4.43.4 Expanding Multiplexers... 0.0.0. ese es ener eee es teen ens nee arenes 4-41 ee4.13.5 implementation of Combinational Logic using MUX. .........2..0.- 4-44 4.14 Demultiplexers ....... 4,15 Decoders.. 4.18.1 Binary Decoder. . 4.18.2 The T4X138 3 to 8 Deooder 4.15.3 The 74X139 Dual 2 to 4 Decoder. 4.15.4 Cascading Binary Decaders......... 4.15.5 Realization of Multiple Output Function using Binary Decoder .................. 4-60 4,15.6 BCD to Decimal Decoder... 0.0.6 4.15.7 BCD to 7 Segment Display Decoder ......... cece tenes 4-63 441871 Bosie Commecion for Ding 7Sgment Osplays 4-61 4.16 Encoders... 4.16.1 Decimal te BCD Encoder . Prererre terres 4-69 4.16.2 Octal to Binary Encoder . ceeceeeeeeeeee wee eeeeteeereeee del 4.16.3 Priority Encoder ......... 4.16 4 Priority Encoder IC (74%X148) 4.17 Parity Generator/Checker .... 4.18 Code Converters. 4.18.1 Binary to BCD Converter... . 4.18.2 BCD to Binary Converter 4.18.3 BCD to Excess 3 4,184 Excess-3 to BCD Code Converter... 0.00. ccccceeesseveeceserceeees 488 4.18.5 Binary to Gray Code Converter ooo eee ee eee ceeeeeee sees 490 4.18.6 Gray Code to Binary Code Converter, .....ccssceeesere 4-2 4.18.7 BCD to Gray Code Converter.......e..0sesessesteneeees : 4-94 4.19 Programmable Logic Devices (PLDs)... 4.19.1 Programmable Read Only Memory (PROM) 4.19.11 AND Matrix 4.19.12 OR Matix... 4.19.1.3 InvartiNon-lnvert Matrix: . 4.19.1 4: Combinational Logic Implementation using PROM =... ss ve 41024.19.2 Programmable Logic Array (PLA) . cee cos 4-105 4.9.2.1 Input Butter . 4-106 419.22 Output Buller. . soe : : : 4-106 4.19.23. Oulput through Flip-Flops 4.108 4.19.2.4 Implementation of Combinatian Lagic Circuit using PLA, . . 4-106 4.19.25 Commercially Available PLAs : an a et 4.19.26 Expanding PLA Capacity... . 4.115 4.19.3. Programmable Aray Logic Devices. . ceeeseeeceeee 4-115 4.19.3.1 Implementation of Combinational Logic Cicuit using PAL . “nT 4.19.32 Registered PALS . 4118 4.19.33. Configurable PALS 4-120 4.19.34 EXORPALs . . : : : : 4-128 4.19.3.5 Comparison between PROM, PLA and PAL 4-128 Solved Examples .. Review Questions. Chapter-5 Flip-Flops 5.1 Introduction 5-4 5.2 The Basic Bistable Elements . 5-3 5.3 Latches and Flip-Flops 5-3 BBASR LAH cee ccecersserersevesevesseeereeee cee 5-3 5.3.2 An Application of the SR Lateh : A Switch Debouncer................ ween 56 53.3 The SR Latch. .. 15-7 5.3.4 The Gated SR Latch... ose cceceecseeeereeeserecseveessenresreresees S28 5.3.5 The Gated D Latch. . 5-10 5.3.6 Edge. Level and Pulse Triggering 5.11 5.3.7 Clocked JK Flip-Flop 5.3.8 Clocked SR Flip-Flop , 5.3.9 Clacked D Flip-Flop 5.3.10 T Flip-Flop 5.3.11 Masier-Slave SR Flip-Flop 5.3.12 Master-Slave JK Flip-Flop... eee eee wee BMP 5.3.13 Asynchronous or Direct Inputs tas eee A 25 ER SAS ae PR OS sO5.3.14 Negative Edge-Triggered D Flip-Flop. 5.4 Realization of One Flip-Flop using Other Flip-Flop 5.4.1 SR Flip-Flop to D Flip-Flop........ 5.4.2 SR Flip-Flop to JK Flip-Flop ...... . 5.4.3 SR Flip-Flop to TFHp+FIOD. occ e cetera nectar eerie eee eeee 5.4.4 JK Flip-Flop to T Flip-Flop .... 5.4.5 JK Flip-Flop to D Flip-Flop 5.4.6 D Flip-Flop to T Flip-Flop . 5.4.7 T Flip-Flop to D Flip-Flop 5.5 Flip-Flop Excitation/Application Tables 55.ARS FlipFlop... 2.20... 5.5.2 JK Flip-Flop ..... 5.5.3D Flip-Flop... (5.5.47 FlipFlop... 5.6 SSI Latches and Flip-Flops. Solved Examples .... Review Questions Chapter - 6.1 Introduction .... 6.2 Asynchronous / 6.3 Asynchronous/Ripple Down Counter ...... 6.4 Synchronous Up Counters ... 6.5 Synchronous Dewn and Up/Down Counters 6.6 Synchronous Vs Asynchronous Counters ..... 6.7 Modulo-n-Counter .. 6.8 Design of Ripple Counters using 7490 and 7493 6.8.1 IC 7490 (Decade Binary Counter)... 2. eo 6.8.2 1C' 7492/93 (4-bit Ripple Counters)... 0... ce cece eee eee eee 6.9 Counter Applications 6.9.1 Digital Clock LLL I EL ITI ES6.9.2 Frequency Counter 0.2.2... cose cetecstesseeceese 6-24 Solved Examples . 6-25 Review Questions ........... ..6-27 Chapter-7 Analysis and Design of Clocked Sequel iris a: ie ay 7.1 Introduction ... eel 7.1.4 Moore Model cecceeeeccuteesteieneveasccceceeeenePed 7.1.2 Meaty Model cectteesees sevens wT? 7.1.3 Moore Vs Mealy Circuit Models. . 74 7.2 Basic Design Steps... 7.2.1 State Diagram . 7.2.2 State Table 7.23 State Reduction 7.24 Slate Assignment . ... 7.2.5 Excitation Tables 7.2.6 Choice of Flip-Flops and Derivation of Next State and Output Expressions . . . 2 Td 7.2.7 Serial Adder Example oo... 00. .ecseeeeeee eee eee eee ere teeter eere ene 7.3 State Assignment Problem ... 7.4 Design with Unused State. 7.5 Lockout Condition ... 7.6 Sequence Generator...... 7.7 Sequence Detector..... 7.8 Analysis of Sequential Circuit... Solved Examples Review Questions Chapter +8: Registers 8.1 Introduction 8.2 Shift Registers _. . 8.3 Modes of Operation of Shift ft Registers . 8.3.1 Serial In Serial Out Shift Register... . 8.3.2 Serial In Parallel Out Shift Register .. er See ree8.3.3 Parallel In Serial Out Shift Register... eee eee BOT 8.3.4 Parallel In Parallel Out Register. ......0.ccccseeeeceeeeeressneeeenereesB-8 8.3.5 Bidirectional Shift Register. . 8.4 Universal Shift Register . 8.5 Applications of Shift Registers .......... 8-12 85.1 DelayLing............ coeeteescceteeesees coer BN 8.5.2 Serial-1o-Paralel Converter ce ceeecerereeseeeerseeseeerserssB=42 8.5.3 Parallel-to-Serial Converter , 8.54 Shift Register Counters 8.6 Shift Register ICs .. . oe a 8.6.1 4-Bit Parallel Access Shift Registers (7495)... 2... cece BIT 86:2 Parallel Access Shift Register (74195)... 2... ceeeeecceeeeeeeee ee Be 20 8.6.3 Universal Shift Register .......... 8.7 MSI Registers .. 8.8 Linear Feedback Shift-Register Counters . Solved Examples Review Questions... 9.1 Introduction 9.2 Fundamental and Pulse Mode Asynchronous Sequential Circuits 9.3 Analysis of Asynchronous Sequential Circuits. ‘9.3.1 Analysis of Fundamental Mode Sequential Circuit . . 9.3.2 Analysis of Pulse Mode Sequential Circuit .. 9.4 Design of Asynchronous Sequential Circui 9.4.1 Derivation of Primitive Flaw Table... . 9.4.2 Reduction of Primitive Flow Table........... 9.4.3 Race Free State Assignment, 9-10 9.4.3.1 Races and Cycles. . wee see wae 9-10 9.4.3.2 Shared Row State Assignment. . - wee wee ~. G2 9.4.3.3 One Hot State Assignment: 9-13 9.44 Realization of Flow Table... 9-18 SA LAS ee a EE Se RSA9144.1 Implementation using Traditional Method. : Loe 9-17 94.4.2 Implementation using SR Latch... eee . ot 9.5 Data Synchronizers. 9.6 Mixed Operating Mode Asynchronous Solved Examples... Review Questions... Chapter 10 Hazards 10.1 Introduction 10.2 Hazards in Combinational Circuits. 10.3 Eliminating a Hazard 10.4 Essential Hazards Review Questions . Chapter- 14 Memory Devices = 11.1 Introduction 11.2 Classification of Memories 11.3 RAM Organisation........... 11.3.1 Read and Write Operation. eee rer ted 11.3.2 Static RAM... vitae beeeveeeceeersseserseesreces TS 114.24 Bipolar RAM Gell... Sees ee 2. M5 11,3.2.2 MOSFET RAM Cell . . - 4-6 14.3.3 Dynamic RAM oe etree ceccceeeceeerese MO? 11.3.3.1 Write Operation. _ ae . . 4-8 11.3.3.2 Read Operation. . . . wee wee se oe 1-8 11.3.3.3 Refresh Operation. . . - 1-9 11.3.4 Comparison between SRAM and DRAM. .....0.c:scecessccccsersseeeeseees 11-10 11218 Mamary Cyaan Tinng Weveloms te 11-10 11.4 Memory Decoding... 11.5 Memory Expansion ........ 11.5.1 Expanding Word Size.......... : 11.5.2 Expanding Memory Capacity weet eect ee cteeeeee 11015 11.6 ROM Organisation ..11.6.1 PROM ( Programmable Read Only Memory) ............005 11.6.2 EPROM ( Erasable Programmable Read Only Memary)... . 11.6.3 EEPROM (Electrically Erasable Programmable Read Only Memory) / EAPROM (Electrically Alterable Programmatle Read Only Memory) 11.7 Programmable Logic Devices. 11.8 Field Programmable Gate Arrays (FPGA) 11.8.1 Architecture of FPGA... 2... 11.8.2 Xilinx XC4000 FPGA Family... 6.0... 11.8.3 XC4000 Architecture .. . Solved Examples .... Review Questions... Appendix A Algorithmic State Machines (ASM) A.1 Introduction .... A.2 ASM Symbols / Notations A.3 Salient Features of ASM Chart .... 4.4 Control Subsystem Implementation .. A4.1 K-map Simplification Method . A.4.2 Multiplexer Control Method. ... . ‘43 PLA Control A.5 ASM for Binary Multiplier. 4.6 ASM for Weighing Machine. Solved Examples. Review Questions.Digital Electronics C-20 Appendix-C ADDERS 54/7483, LS83A LOGIC DIAGRAM 0 or nN Ee ™ Veg Pas | IB, ue Be 12 % (7s Pinnumtere LOGIC DIAGRAM Cy hy ka By ae Ae \esteaa thay froin tn fyi fy pte ven Vv + | 7 = ® a ns os & a Nad courPees Ord ® Combinational Circuits Pee eet Pe ne ce corey Third Revised Edition 2008 ISBN 978-81-8431-411-3 Technical Publications Pune #1, Amit Residency, 412 Shaniwar Peth, Pune - 411030, M.S., India. | pire rst epic ale ae Aa stele eli)