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Section 1: MOSFET-1

Nano-Devices and Their Integration

Objective and Outline


Objective: A brief introduction to MOSFET
Outline:
1)

University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Acknowledgement

This lecture note has been obtained from the similar


courses all over the world. I wish to thank all the
professors who created such good works on those
lecture notes. Without them, these slides could have
not been presented to you.

University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

MOS Capacitors

Note:
1) EF is an indication of the number of electrons.
2) If the EF of two layers are the same, no electron
displacement between the layers occurs.
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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

MOS Band Diagram Different Work functions

Basic idea behind drawing this band diagram:


1) No current dEF/dx = 0 EF (x) = cte..
2) Electron affinity is always constant for the semiconductor
3) No discontinuity for the vacuum level which is achieved by a gradual distribution of
electrons at the interface.
4) The distribution is determined from the balance of electron drift and diffusion at the
interface. The electrons going to the conduction band initially should fall down to valence
band since initially EC is far from EF. These electrons cause annihilation of the holes
Depletion region Band bending toward more electrons in the conduction band.

University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Flat Band Condition

3.1 eV = Si SiO2
It is independent of
the applied voltage.

University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Non-Flat-band conditions
Note: qVg = EfS EfM. If Vg = Vfb No charge build-up. VOx and S = 0.
Charge build-up Band bending

S is the potential which is formed via the QS

University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Surface Accumulation
Note:

Vg < Vfb Difficult for electrons to move toward the gate.

p ni e

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Ali Afzali-Kusha

Ei E f KT

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Depletion

University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Threshold (of Inversion)


EFS = Ei Semiconductor is intrinsic.
A = Ec Ef
C = Ei Ef

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B = Ef Ev
D = Ef Ei

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Inversion

For Vg > Vth, mainly the oxide voltage drop increases.


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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Review: Basic MOS Capacitor Theory

Surface potential does not change


much for the same reason as that for
the strong inversion case.

Determines free carriers


and depletion charges

Determines depletion charges

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Review: Basic MOS Capacitor Theory

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Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Advanced MOSCAP Physics and Technology


So were we too simplistic?

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

A More General and Accurate MOSCAP Analysis

1 du
1 du du du du
d 2. d d
2 dx
2 dx dx dx dx
2
1 1 du 2 d du
1 1 du
d 2u
d

2
2
du
dx
dx
dx
2
du
dx


dx

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Calculation of E(x)

Integration

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Calculation of QS

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Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Calculation of Inversion and Depletion Charge

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Extraction of C-V Characteristics

Na Nd = p0 n0

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Extraction of C at VT

Nd & ps, 0, s = 2 b

Cs = Cdep + Cinv = 2Cdep

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Extraction of C at VFB

To obtain this, the exponential relation for ns and ps


should be expanded using series expansion.

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

MOSCAP LFCV Characteristics

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Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

MOSCAP LFCV Characteristics


No saturation

Saturation

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

MOSCAP HFCV Characteristics

Note: For a p-type substrate, we have a good (via a p+


substrate) contact allowing electrons enter into the
valence band of the substrate during depletion or exit
from the substrate during the accumulation. In the case
of inversion, the electrons should enter into the
valence band first and then rise to conduction band
via thermal generation which is a slow process.

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Summary of MOSCAP CV Characteristics


Note: n is only for
free carriers and not
depletion charges

Vbias = f(t); Vac = f(t)

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Deep Depletion
Deep depletion - DC voltage (VG) is applied fast enough (high frequency) that inversion
layer carriers cannot follow it, so XD must expand (and therefore CD decreases) to balance the
charge on the gate (In HF characteristics, Vac has a high frequency while Vbias has a very low
frequency).
Deep depletion is a sign of a high minority carrier lifetime in the material.
In the case of HFCV, since the DC ramp is very slow, we have enough time for the generation
of nbias, and hence, XD cannot grow much due to limitation on the value of nbias.
The small vg,ac, however, cannot generate any nac. To balance the gate charge, QD, and hence, XD
should increase. Since vg,ac is small, we can ignore the decrease in CD (not shown on the top
figure of the previous slide).
In the case of deep depletion, however, no n is generated at all and all the gate charge should be
compensated with the depletion charge. Here, Vbias is large and hence capacitance reduction
should be shown clearly.
To explain this more, consider what happens after the application of a voltage step from
depletion towards inversion.
On top of step, put HF small signal to measure C
Immediately after the onset of the step (after an RC delay), inversion
layer does not have a chance to grow (electrons must be generated)
MOS remains in depletion (deep depletion)
XD grows beyond XDmax
C smaller than CHF
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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

The Charge Sheet Model

Note: In charge sheet model, charges are expressed in terms of charge density per unit area.
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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Main Assumptions

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Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Derivation of QS

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Derivation of Qdep and Qinv

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Simplification under Weak Inversion

is the coefficient
which relates s to Vg
(approximately).

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Oxide Charges

QF

Qit

Qit has a fixed position but its


amount is a function of the
applied voltage.
Oxide trapped charges is
distributed along the oxide.
Mobile
Charge
position
changes by the applied
voltage.

which is modified by EF.


Both are functions of applied voltage

Reference for x is the gate edge.


Negative sign for positive charges.
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For each charge type, we consider


its effective capacitance. It can be
proven using the Gauss's law.

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Conventionally we put fixed charges in VFB. The reason is


that fixed charge only shifts the entire C-V curve.
Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Oxide Charges
There are four types of charges:
1) Fixed charges (it is always charged) (important for High-K dielectric materials
(Al2O3) but controlled/minimized for SiO2.
The advantages of Al2O3 are 1) good material, 2) large bandgap, 3) large
dielectric constant, 4) easy to deposit, and 5) very robust system but rejected
because of two problems, namely, 1) interface trap charges like most of other
high-K dielectrics and 2) a major fixed charge problem, especially sputtered
(physically vapor deposited).
Fixed charge Shift in VT.
Location: They are located in the order of 3nm from the Si-SiO2 interface.
Origin: It has been suggested that the origins are
1) Excess Si (Trivalent Si) (forming positive charge at the interface) or
2) The loss of an electron from excess oxygen center (non bridging oxygen)
positive ion near Si-SiO2 interface.
Remedy: We use higher doping level to compensate for the VTH shift. Problems
with higher doping level is lower mobility.
2) Oxide trapped charges. Origin: The oxide defects.
They are usually neutral and are charged by introducing electrons and holes into
the oxide. Location: The defects may be distributed within entire oxide thickness.
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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Oxide Charges
3)

Interface trap charges (depending on the Fermi level (function of the gate
voltage), they are charged or discharged. The time constant for bulk is very
short ~ns but for poly is in order of hours or day).
Problems:
1) Highest effect on the threshold.
2) High scattering at the surface Lower mobility.
3) Noise Very bad for analog circuits and turning to a problem for digital as the
supply is scaled.
4) Degrading the swing by moving apart the VFB and VT (increasing the slope due
to the gate capacitance change.) In other words, the swing that you need to turn off
or on the transistor becomes larger (see slide 36). For the (boundary in the case of
poly) states in Amorphous/Poly-Si-Thin Film Transistor used for displays, a
small swing is very desired. They have 0.5-1V of swing per decade (compared
to 60 to 100mV for single crystal MOSFET) which is horrible (not easy
turning off).
- Higher states sometimes deteriorate the stability and reliability depending on
the 1) type of the states, 2) how strong they are, and 3) how deep they are in
the bandgap.
4) Mobile charges. Not an issue in modern clean processes.

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Mobile Ions
D.R. Kerr et. al.
Stabilization of
SiO2 Passivation
Layers with P2O5
IBM JOURNAL SEPTEMBER 1964
pp. 376-384.

Existence of mobile charges

For the left curve, first we have had


positive bias at the temperature of 100C
Negative shift in VFB.
With zero bias or negative bias, the same
temperature treatment (100C) gave no
shifting of the C-V characteristic.
Higher temperatures with zero or
negative bias tended to shift the curve
to the right as shown in the dotted trace,
but such shifts appear to be a function
of time and temperature and not bias.
The hysteresis effect is due to the fact
that, the mobile ions do not move as
fast as we change the voltage, i.e., they
do not follow the voltage change.
Technology has solved the problem of
mobile ions by a large extent. It is not an
issue in a clean process.

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Mobile Charges
Mobile charge results from alkali-metal ions particularly sodium (Na+).
They induce VFB.
. :( )

The alkali ions have sufficient mobility when relatively low gate
biases are applied.
The mobility increases with temperature and thus magnifies the
problem of VFB instability at high temperatures.
The ions are positively charged, therefore VG draws the ions to the
metal-SiO2 interface where their effect is minimal. +VG pushes them
to the Si-SiO2 interface where their effects are most significant.
For threshold voltage stability of 0.1V, less than 2x1010cm-2 mobile
ions can be tolerated.
Mobile ions can be avoided by 1) careful processing and 2) oxidation
in HCl that immobilizes alkali ions.
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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Interface Traps
n-type substrate

Donor type traps

Inversion

Depletion

Accumulation
Technology (such as H2 annealing) has solved the
problem of interface traps ions by a large extent.
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The effect of interface trap shifts the C-V


depending on the Fermi-Level (the gate voltage).
Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Telegraphic (or Flicker) Noise due to Interface Traps

Trapped electron makes


the trap charged.
Trapped electron makes
the trap neutral.

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Interface Traps

38

Interface traps both shifts and smear the slope of the C-V curve.
The amount and sign of the shift depend on the strength and type of the traps.
Interface charges may be donor or acceptor type.
If the trap is filled with electron is neutral and when becomes empty it become
positive, then it is donor type and causes a negative shift in VT
(+charge at the interface) (Donor impurities are either neutral or positive)
If the trap is filled with electron is negative and when becomes empty become
neutral, then it is acceptor type and causes a positive shift in VT.
(charge at the interface) (Acceptor impurities are either neutral or negative)
The Fermi level determines how much of the states are filled.
Hydrogen annealing works better with positive traps (dominant trap type in
the modern process).
If an electron goes from the inversion to a trap, two cases occur:
1. The electron fill a positive trap to make it neutral Higher mobility
Increase in current.
2. The electron fills a negative trap to make it negative Lower mobility
Decrease in current
University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Electrical Tox Raised by Inversion Change Centroid and Gate Depletion

Tox

Tox

In NMOS (PMOS), in inversion, positive (negative) charge on the n+ (p-) poly leads to depletion region.
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Ali Afzali-Kusha

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Section 1: MOSFET-1

Nano-Devices and Their Integration

Polysilicon Gate Depletion


Two serial capacitors. For the same thickness, capacitor in the poly-silicon is higher
due to higher dielectric constant and has less effect (similar parallel resistors).

1)
Its effect is
similar to
the

2) & 3)

where Cox C
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4) It also affects gm
Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

How to Reduce Gate-Depletion Effect

A:
B:
1)

PhosphorOxidChloride

2)
for p+ poly-gate

3)

B tends to diffuse toward oxide


1) Worsening the poly depletion
problem. 2) Also, it can diffuse
toward the channel shifting the VT.

4)

Less an issue for SiGe ploy-gate


(higher solid-solubility).

1) 3) are appropriate for n+-poly gate (no Boron). Since the problems do not exist for As and P doped poly-gate.

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University of Tehran

Ali Afzali-Kusha

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Section 1: MOSFET-1

Nano-Devices and Their Integration

Poly-Si1-xGex Gate Technology


Whereas pure Ge is not suitable for use as a gate material due to its
1) low melting point and 2) its lack of a stable oxide,
poly-Si1-xGex films with Ge mole fractions up to 0.6 were found to be
completely compatible with standard VLSI fabrication processes, in
regard to 1) deposition and patterning techniques, 2) hightemperature chemical and mechanical stability, 3) electrical stability,
and 4) uniformity.
Dual Poly-Gate Process: A new poly-Si-Ge gate CMOS process
has been developed for a submicron CMOS technology.
The incorporation of Ge into a heavily doped p-type poly-Si (p+
poly-Si) gate material causes the gate workfunction to be
reduced (more than 300 mV for a 60% Ge material), so that both
NMOS and PMOS surface channel devices may be achieved.
In addition, the use of Ge increases the dopant activation, and
hence, improving the gate sheet resistance. Dual poly process.
42

University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Quantum Effect (in the Inversion Layer)


Before

Schrdinger Equation

E0, E1, E2
Note: that Ec EF at x = 0 is not important but E0 EF for calculation electron density should be considered.
More bending is required 100 mV increase in VT.

43

University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Quantum Effect (in the Inversion Layer)

Model for inversion capacitance:

Increase in Tox Change of Cox

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University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Quantum Effect (in the Inversion Layer)


The charge centroid is the average distance of the inversion charge
from the interface obtained from the quantum simulation.
The DC charge centroid, which determines the IDS, is obtained from
the simulation.
The AC charge centroid is the average distance of the additional
charge induced by a small change in the gate voltage.
The AC charge centroid is always smaller than the DC charge
centroid because the additional charge accumulates closer to the
interface as the bias increases ( higher electric field).
Reference: Kevin Yang, Ya-Chin King, and Chenming Hu, Quantum Effect in Oxide Thickness Determination
From Capacitance Measurement, in Proceedings of IEDM 1999, pp. 77-78.
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University of Tehran

Ali Afzali-Kusha

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Section 1: MOSFET-1

Nano-Devices and Their Integration

Real MOSCAP CV Characteristics

46

University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Definition of VT
VT is difficult to determine in modern devices (DIBL, etc.,).

VDS effect has been ignored.

Depending on VDS, different Vt is obtained!


In modern MOSFET
VT is a function of VD.

Not easy in the linear region too. It is defined by 100nA/m.


47

University of Tehran

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

Use of Doping to Control VT


n+ poly NMOSFET

The use of n+-poly has


much lower resistance
compared to p+-poly.
Single poly process.

Increasing TOx reduces the


gate control Higher Vt.
Change workfunction

Adjustable workfunction metals are


highly desired for the gate metal.

High (low) metal workfunction is desired for PMOS (NMOS)


high |MS| |MS + 2B + Qf /COx| 0
48

University of Tehran

Ali Afzali-Kusha

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Section 1: MOSFET-1

Nano-Devices and Their Integration

Substrate Doping Profiles due to Ion Implantation


~A

~A
B

Modern processes use


retrograde doping profile
1) to suppress different
short channel effects.
Added advantage is the
2) fixed depletion width.
(See slide #52.)

From before

Modify the threshold voltage


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Ali Afzali-Kusha

Delta doping
at the interface
afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

VT of Retrograde-well Device
N 0 for 0 < X < d
Electric field is almost constant.
Charge space is at the depth d below the interface.

Simplifying Model

Voltage drop across the semiconductor

Voltage drop across the insulator

Lower VT due to smaller doping at the interface manifests at the stronger effect of VFB lowering the threshold voltage.

50

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Ali Afzali-Kusha

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Section 1: MOSFET-1

Nano-Devices and Their Integration

Effects of Non-Uniform Doping

The same body effect characteristics


as Na2 but Vt t the same as Na1.

Side effects:

Use delta
implant
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With delta implant we increase the threshold voltage without


worrying too much about the body effect.
University of Tehran

Ali Afzali-Kusha

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Section 1: MOSFET-1

Nano-Devices and Their Integration

Retrograde Body Doping Profiles

Retrograde doping profile suppress the punch-through problem.


52

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Ali Afzali-Kusha

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Section 1: MOSFET-1

Nano-Devices and Their Integration

MOSFET Threshold Voltage Issues


Simple model:

MOSFET Vt and the Body Effect

= cte

cte.

Also, for retrograde doping


profile, we had Cdep = cte.

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Body effect
Linear
dependence

Vsb = 0

Ali Afzali-Kusha

afzali@ut.ac.ir

Section 1: MOSFET-1

Nano-Devices and Their Integration

MOSFET Vt and the Body Effect

Uniform
Doping
Profile:

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