Exemplos de SystemVerilog

//----------------------------------------------------// Design Name : encoder_using_if
// File Name
: encoder_using_if.sv
// Function
: Encoder using If
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module encoder_using_if(
output reg [3:0] binary_out , // 4 bit binary Output
input wire [15:0] encoder_in , // 16-bit Input
input wire
enable
// Enable for the encoder
);
//--------------Code Starts Here----------------------always_comb
begin
binary_out = 0;
if (enable) begin
if (encoder_in == 16'h0002) begin
binary_out = 1;
end if (encoder_in == 16'h0004) begin
binary_out = 2;
binary_out = 3;
binary_out = 4;
binary_out = 5;
binary_out = 6;
binary_out = 7;
binary_out = 8;
binary_out = 9;
binary_out = 10;
binary_out = 11;
binary_out = 12;
binary_out = 13;
binary_out = 14;
binary_out = 15;
end
end
end
endmodule
//----------------------------------------------------// Design Name : encoder_using_case
// File Name
: encoder_using_case.sv
// Function
: Encoder using Case
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module encoder_using_case(
output reg [3:0] binary_out , // 4 bit binary Output
input wire [15:0] encoder_in , // 16-bit Input

input wire
enable
);
ENCODER : begin
binary_out = 0;
if (enable) begin
case (encoder_in)
16'h0002 : binary_out = 1;
16'h0004 : binary_out = 2;
16'h0008 : binary_out = 3;
16'h0010 : binary_out = 4;
16'h0020 : binary_out = 5;
16'h0040 : binary_out = 6;
16'h0080 : binary_out = 7;
16'h0100 : binary_out = 8;
16'h0200 : binary_out = 9;
16'h0400 : binary_out = 10;
16'h0800 : binary_out = 11;
16'h1000 : binary_out = 12;
16'h2000 : binary_out = 13;
16'h4000 : binary_out = 14;
16'h8000 : binary_out = 15;
endcase
end
end
endmodule
//----------------------------------------------------// Design Name : pri_encoder_using_if
// File Name
: pri_encoder_using_if.sv
// Function
: Pri Encoder using If
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module pri_encoder_using_if (
output reg [3:0] binary_out , // 4 bit binary output
input wire [15:0] encoder_in , // 16-bit input
input wire
enable
);
begin
binary_out = 0;
if (enable) begin
priority if (encoder_in == {{14{1'bx}},1'b1,{1{1'b0}}}) begin
binary_out = 1;
end else if (encoder_in == {{13{1'bx}},1'b1,{2{1'b0}}}) begin
binary_out = 2;
binary_out = 3;
binary_out = 4;
binary_out = 5;
binary_out = 6;
binary_out = 7;
end else if
binary_out
end else if
binary_out
end else if
binary_out
end else if
binary_out
end else if
binary_out
end else if
binary_out
end else if
binary_out
end else if
binary_out
end
end
end
(encoder_in
= 8;
(encoder_in
= 9;
(encoder_in
= 10;
(encoder_in
= 11;
(encoder_in
= 12;
(encoder_in
= 13;
(encoder_in
= 14;
(encoder_in
= 15;
== {{7{1'bx}},1'b1,{8{1'b0}}}) begin
== {{6{1'bx}},1'b1,{9{1'b0}}}) begin
== {{5{1'bx}},1'b1,{10{1'b0}}}) begin
== {{4{1'bx}},1'b1,{11{1'b0}}}) begin
== {{3{1'bx}},1'b1,{12{1'b0}}}) begin
== {{2{1'bx}},1'b1,{13{1'b0}}}) begin
== {{1{1'bx}},1'b1,{14{1'b0}}}) begin
== {1'b1,{15{1'b0}}}) begin
endmodule
//----------------------------------------------------// Design Name : pri_encoder_using_assign
// File Name
: pri_encoder_using_assign.sv
// Function
: Pri Encoder using assign
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module pri_encoder_using_assign (
output wire [3:0] binary_out , // 4 bit binary output
input wire [15:0] encoder_in , // 16-bit input
input wire
enable
);
//--------------Code Starts Here----------------------assign binary_out = (!enable) ? 0 : (
(encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :
(encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :
(encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :
(encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :
(encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :
(encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :
(encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :
(encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :
(encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :
(encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :
(encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :
(encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :
(encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :
(encoder_in == 16'bxx10_0000_0000_0000) ? 13 :
(encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);
endmodule
//----------------------------------------------------// Design Name : decoder_using_case
// File Name
: decoder_using_case.sv
// Function
: decoder using case
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module decoder_using_case (
input wire [3:0] binary_in

, //
output reg [15:0] decoder_out , //
input wire
enable
//
);
always_comb
begin
decoder_out = 0;
if (enable) begin
case (binary_in)
4'h0 : decoder_out
4'h1 : decoder_out
4'h2 : decoder_out
4'h3 : decoder_out
4'h4 : decoder_out
4'h5 : decoder_out
4'h6 : decoder_out
4'h7 : decoder_out
4'h8 : decoder_out
4'h9 : decoder_out
4'hA : decoder_out
4'hB : decoder_out
4'hC : decoder_out
4'hD : decoder_out
4'hE : decoder_out
4'hF : decoder_out
endcase
end
end
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
4 bit binary input

16-bit out
Enable for the decoder
16'h0001;
16'h0002;
16'h0004;
16'h0008;
16'h0010;
16'h0020;
16'h0040;
16'h0080;
16'h0100;
16'h0200;
16'h0400;
16'h0800;
16'h1000;
16'h2000;
16'h4000;
16'h8000;
endmodule
//----------------------------------------------------// Design Name : decoder_using_assign
// File Name
: decoder_using_assign.sv
// Function
: decoder using assign
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module decoder_using_assign (
input wire [3:0] binary_in
, // 4 bit binary input
output wire [15:0] decoder_out , // 16-bit out
input wire
enable
// Enable for the decoder
);
//--------------Code Starts Here----------------------assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;
endmodule
//----------------------------------------------------// Design Name : mux_using_assign
// File Name
: mux_using_assign.sv
// Function
: 2:1 Mux using Assign
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_using_assign (
input wire din_0
, // Mux first input
input wire din_1
, // Mux Second input
input wire sel
, // Select input
output wire mux_out
// Mux output
);
//-------------Code Start----------------assign mux_out = (sel) ? din_1 : din_0;
endmodule //End Of Module mux
//----------------------------------------------------// Design Name : mux_using_if
// File Name
: mux_using_if.sv
// Function
: 2:1 Mux using If
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_using_if(
input wire din_0
input wire din_1
input wire sel
, // Select input
output reg
mux_out
// Mux output
);
//-------------Code Starts Here--------always_comb
begin : MUX
if (sel == 1'b0) begin
mux_out = din_0;
end else begin
mux_out = din_1 ;
end
end
//----------------------------------------------------// Design Name : mux_using_case
// File Name
: mux_using_case.sv
// Function
: 2:1 Mux using Case
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module mux_using_case(
input wire din_0
input wire din_1
input wire sel
, // Select input
output reg
mux_out
// Mux output
);
//-------------Code Starts Here--------always @ (*)
MUX : begin
case (sel)
1'b0 : mux_out = din_0;
1'b1 : mux_out = din_1;
endcase
end
//----------------------------------------------------// Design Name : dff_async_reset
// File Name
: dff_async_reset.sv
// Function
: D flip-flop async reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module dff_async_reset (
input wire data , // Data Input
input wire clk
, // Clock Input
input wire reset , // Reset input
output reg q
// Q output
);
//-------------Code Starts Here--------always_ff @ ( posedge clk iff reset == 1 or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule //End Of Module dff_async_reset
//----------------------------------------------------// Design Name : dff_sync_reset
// File Name
: dff_sync_reset.sv
// Function
: D flip-flop sync reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module dff_sync_reset (
input wire clk
, // Clock Input
output reg q
// Q output
);
//-------------Code Starts Here--------always_ff @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule //End Of Module dff_sync_reset
//----------------------------------------------------// Design Name : tff_async_reset
// File Name
: tff_async_reset.sv
// Function
: T flip-flop async reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module tff_async_reset (
input
wire data , // Data Input
input
wire clk
, // Clock Input
input
wire reset , // Reset input
output reg
q
// Q output
);
//-------------Code Starts Here--------always_ff @ ( posedge clk iff reset == 1 or negedge reset)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= !q;
end
endmodule //End Of Module tff_async_reset

//----------------------------------------------------// Design Name : tff_sync_reset
// File Name
: tff_sync_reset.sv
// Function
: T flip-flop sync reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module tff_sync_reset (
input wire clk
, // Clock Input
output reg q
// Q output
);
if (~reset) begin
q <= 1'b0;
q <= !q;
end
//----------------------------------------------------// Design Name : tff_sync_reset
// File Name
: tff_sync_reset.sv
// Function
: T flip-flop sync reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module tff_sync_reset (
input wire clk
, // Clock Input
output reg q
// Q output
);
if (~reset) begin
q <= 1'b0;
q <= !q;
end
//----------------------------------------------------// Design Name : dlatch_reset
// File Name
: dlatch_reset.sv
// Function
: DLATCH async reset
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module dlatch_reset (
input wire data
, // Data Input
input wire en
, // LatchInput
output reg q
// Q output
);
//-------------Code Starts Here--------always_latch

if (~reset) begin
q <= 1'b0;
end else if (en) begin
q <= data;
end
endmodule //End Of Module dlatch_reset
8-Bit Simple Up Counter

//----------------------------------------------------// Design Name : up_counter
// File Name
: up_counter.sv
// Function
: Up counter
// Coder
: Deepak
//----------------------------------------------------module up_counter
(
output reg [7:0] out
, // Output of the counter
input wire
enable , // enable for counter
input wire
clk
, // clock Input
input wire
reset
// reset Input
);
//-------------Code Starts Here------always_ff @(posedge clk)
if (reset) begin
out <= 8'b0 ;
end else if (enable) begin
out ++;
end
endmodule
8-Bit Up Counter With Load

//----------------------------------------------------// Design Name : up_counter_load
// File Name
: up_counter_load.sv
// Function
: Up counter with load
// Coder
: Deepak
//----------------------------------------------------module up_counter_load
(
input
wire [7:0] data
, // Parallel load for the counter
input
wire
load
, // Parallel load enable
input
wire
enable
, // Enable counting
input
wire
clk
, // clock input
input
wire
reset
// reset input
);
//-------------Code Starts Here------always_ff @ (posedge clk)
if (reset) begin
out <= 8'b0 ;
end else if (load) begin
out <= data;
out <= ++;
end
endmodule
8-Bit Up-Down Counter

//----------------------------------------------------// Design Name : up_down_counter
// File Name
: up_down_counter.sv
// Function
: Up down counter
// Coder
: Deepak
//----------------------------------------------------module up_down_counter
(
input wire
up_down , // up_down control for counter
input wire
clk
, // clock input
input wire
reset
// reset input
);
//-------------Code Starts Here------always_ff @(posedge clk)
if (reset) begin // active high reset
out <= 8'b0 ;
end else if (up_down) begin
out ++;
end else begin
out --;
end
endmodule
Random Counter (LFSR)

//----------------------------------------------------// Design Name : lfsr
// File Name
: lfsr.sv
// Function
: Linear feedback shift register
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module lfsr (
input
wire
enable , // Enable for counter
input
wire
clk
, // clock input
input
wire
reset
// reset input
);
//------------Internal Variables-------wire
linear_feedback;
//-------------Code Starts Here------assign linear_feedback = !(out[7] ^ out[3]);
always_ff @(posedge clk)
if (reset) begin // active high reset
out <= 8'b0 ;
out <= {out[6],out[5],
out[4],out[3],
out[2],out[1],
out[0], linear_feedback};
end
endmodule // End Of Module counter
Gray Counter
//----------------------------------------------------// Design Name : gray_counter
// File Name
: gray_counter.sv
// Function
: 8 bit gray counter
// Coder
: Deepak
//----------------------------------------------------module gray_counter (
output wire [7:0] out
, // counter out
input wire
enable , // enable for counter
input wire
clk
, // clock
input wire
rst
// active hight reset
);
//------------Internal Variables-------reg [7:0] count;
//-------------Code Starts Here--------always_ff @ (posedge clk)
if (rst) begin
count <= 0;
count <= count + 1;
end
assign out = { count[7], (count[7]
count[5]),(count[5] ^
^ count[6]),(count[6] ^
count[4]), (count[4] ^
count[2]), (count[2] ^
count[0]) };
endmodule
One Hot Counter

//----------------------------------------------------// Design Name : one_hot_cnt
// File Name
: one_hot_cnt.sv
// Function
: 8 bit one hot counter
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module one_hot_cnt (
input
wire
enable
, // enable for counter
input
wire
clk
, // clock input
input
wire
reset
// reset input
);
//-------------Code Starts Here------always_ff @ (posedge clk)
if (reset) begin
out <= 8'b0000_0001 ;
out <= {out[6],out[5],out[4],out[3],
out[2],out[1],out[0],out[7]};
end
endmodule
Divide by 2 Counter
//----------------------------------------------------// Design Name : clk_div
// File Name
: clk_div.sv
// Function
: Divide by two counter
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module clk_div (
input wire clk_in,
input wire enable,
input wire reset,
output reg
clk_out
);
//--------------Code Starts Here----------------------always_ff @ (posedge clk_in)
if (reset) begin
clk_out <= 1'b0;
clk_out <= !clk_out ;
end
endmodule
Divide By 3 Counter
//----------------------------------------------------// Design Name : divide_by_3
// File Name
: divide_by_3.sv
// Function
: Divide By 3
// Coder
: Deepak Kumar Tala
//----------------------------------------------------module divide_by_3 (
input
wire
clk_in
, //Input Clock
input
wire
reset
, // Reset Input
output wire
clk_out
// Output Clock
);
//------------Internal Variables-------reg [1:0] pos_cnt;
reg [1:0] neg_cnt;
//-------------Code Start----------------// Posedge counter
always_ff @ (posedge clk_in)
if (reset) begin
pos_cnt <= 0;
end else begin
pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1;
end
// Neg edge counter
always_ff @ (negedge clk_in)
if (reset) begin
neg_cnt <= 0;
end else begin
neg_cnt <= (neg_cnt == 2) ? 0 : neg_cnt + 1;
end
assign clk_out = ((pos_cnt != 2) && (neg_cnt != 2));
endmodule
Divide By 4.5 Counter

//----------------------------------------------------// Design Name : clk_div_45
// File Name
: clk_div_45.sv
// Function
: Divide by 4.5
// Coder
: Deepak
//----------------------------------------------------module clk_div_45 (
input wire clk_in, // Input Clock
input wire enable, // Enable is sync with falling edge of clk_in
output wire clk_out // Output Clock
);
//--------------Internal Registers---------------------reg
[3:0] counter2
;
reg
[3:0] counter2
;
reg
toggle1
;
reg
toggle2
;
//--------------Code Starts Here----------------------always @ (posedge clk_in)
if (enable == 1'b0) begin
counter1 <= 4'b0;
toggle1 <= 0;
end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 ==
4)) begin
counter1 <= 4'b0;
toggle1 <= ~toggle1;
end else
begin
counter1 <= counter1 + 1;
end
always @ (negedge clk_in)
if (enable == 1'b0) begin
counter2 <= 4'b0;
toggle2 <= 0;
end else if ((counter2 == 3 && ~toggle2) || (toggle2 && counter2 ==
4)) begin
counter2 <= 4'b0;
toggle2 <= ~toggle2;
end else
begin
counter2 <= counter2 + 1;
end
assign
clk_out = (counter1 <3 && counter2 < 3) & enable;
endmodule
Mquina de Moore X Mquina de Estados

Existem dois modelos comuns de sistemas seqenciais sncronos: a Moore ma- chine ea
mquina de Mealy. Estes esto ilustrados na figura 6.2. Ambos os tipos de sistemas so
accionados por um nico relgio. O prximo estado determinado por alguma funo (combinacional) das entradas e estado atual. A diferena entre os dois modelos que, na mquina
de Moore as sadas so apenas uma funo do estado actual, enquanto que na mquina Mealy
as sadas so uma funo do estado actual e das entradas. Ambas as mquinas de Moore e Mealy
so comumente referidos como mquinas de estado. Isto quer dizer que eles tm um estado
interno que muda.
Como foi visto no Captulo 2, a lgica combinacional pode conter perigos. A lgica de estado
prximo da Moore e mquinas Mealy simplesmente um bloco de lgica combinacional com
uma srie de entradas e uma srie de sadas. A existncia de riscos neste prximo lgica Estado
poderia fazer com que o sistema para ir para um estado incorreto. Existem duas maneiras para
evitar tal problema: ou o prximo estado lgica deve incluir a lgica redundante necessria para
suprimir o risco ou a mquina de estado devem ser concebidos de tal modo que um perigo
permitido ocorrer, mas ignorado. A primeira soluo no ideal, como o prximo lgica do
Estado mais complexo; da, a segunda abordagem utilizada. (Note-se que os sistemas
assncronos so suscetveis a riscos e no prximo lgica Estado deve evitar qualquer perigo de
ocorrer, o que uma razo pela qual os sistemas sncronos so geralmente preferidos.) Para
garantir que os sistemas seqenciais so capazes de ignorar os perigos, um relgio usado para
sincronizar dados. Quando o relgio invlido, todos os perigos que ocorrem podem ser
ignorados.
Uma tcnica simples, portanto, a lgica e um sinal de relgio com os sinais do sistema - quando
o relgio est na lgica 0, quaisquer perigos seria ignorado. O sistema , no entanto, ainda
susceptvel a riscos enquanto o relgio alta. comum, por conseguinte, ao utilizar registos que
s so sensveis a sinais de entrada, enquanto o relgio est a mudar. O clock muito curto em
comparao com o perodo do relgio. Portanto, os dados s tem de ser estvel durante a
durao da alterao do relgio, com pequenas tolerncias, antes e depois da borda do relgio.
Estes parmetros de tolerncia de tempo so conhecidos como a configurao e tempo de
espera (TSETUP, Thold), respectivamente, como mostrado na Figura 6.3. Os registros estaduais
para uma mquina de estados sncrona so, portanto, borda desencadeou-D fl ip- fl ops. Outros
tipos de fl ip- fl op pode ser usada para projetar sistemas sncronos, mas eles oferecem algumas
vantagens e no so comuns na lgica programvel.

Exemplos de SystemVerilog

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//----------------------------------------------------// Design Name : encoder_using_if

input wire [15:0] encoder_in , // 16-bit Input

input wire [3:0] binary_in

4 bit binary input

endmodule //End Of Module tff_async_reset

//-------------Code Starts Here--------always_latch

8-Bit Simple Up Counter

8-Bit Up Counter With Load

8-Bit Up-Down Counter

Random Counter (LFSR)

endmodule // End Of Module counter

One Hot Counter

Divide By 4.5 Counter

clk_out = (counter1 <3 && counter2 < 3) & enable;

Mquina de Moore X Mquina de Estados

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