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Fig. 2 shows the status information like the process, edit status etc. of the IC window.
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4. Using the SDL button in the palette menu, go to the SDL menu.
5. From the SDL menu, set the logic source for the cell using Logic > Set palette option. In the dialog box that appears, use the Navigator button to select the nand2/sdl
viewpoint. Be sure to select the correct viewpoint for if you don't, the tools will not be able to recognize your transistors.
6. Once your logic source is selected, open the schematic using the palette menu Logic > Open. The schematic should appear in a window beside the empty cell.
7. At this point, you should be sure the ICgraph window is active (the empty cell's window). If it is not, click on that window to make it active. Notice the new pull down
menu MDK (MOSIS Design Kit) at the right of the menu bar. It has options to generate various pad-frames, set/unset the query on merge mode and select/unselect
"diffusion sharing." Selecting an item will do what that item says. So, for example, if we wish to have ICgraph automatically merge series and parallel transistors, then
we need to select Use Diffusion Sharing from the MDK menu. The session has been setup for Diffusion sharing. Do not alter this.
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8. Now you can place the devices into your cell by automatic placement method for this exercise. To do this, click on Schematic > A-Inst palette menu. At this point, the
tools will locate devices that are of the same type and have connectivity such that diffusion regions may be shared. The devices will be automatically generated based on
the length and width parameters specified on the instances and placed into the open cell. Overflow lines (in yellow) will show you the connectivity points in your circuit.
As you wire the circuit together, these overflows will disappear when you have made the correct connections.
9. Before editing the cell, add rulers to the cell.. The rulers act as a reference thus aiding in easy layout. To add rulers, click the Right Mouse Button in the active IC
window, and select the Add>Ruler: from the pop-up menu. Starting at the lower left as in Fig.4a and Fig. 4b, click and drag the Left Mouse Button and release it at a
point where you want the ruler to end. Similarly, construct the other ruler. To delete a ruler, execute the pull down menu Edit>Delete>Ruler: and click on the ruler to be
deleted.
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10. Now, as the placement algorithm places the devices fairly close, spread out the devices a little. First select the entire device by clicking on the dotted outline. Notice
that when you select a device it is also selected in the schematic window. Both devices and nets may be cross-selected in this manner. Using the Right Mouse Button,
execute the pop-up menu option Edit>Move>Unconstrained and place the cells as shown in Fig.4a. (Place the devices in such a way that, when you are routing the
metals, you can run the VDD rail from 3, 79 to 82, 85 and VSS from 3, 21 to 82, 24. Later you will layout your 3-input Nor cell in the same way. Thus, when you abut
these cells, the power and ground ports will be connected from cell to cell). Once the placement is done, unselect the cell using F2 key.
11. The next step to be performed is routing. There are many methods for accomplishing this task. We will look at a few of them now. The first method is very useful for
wiring metal together. You can do this using Add>Route palette menu (if the menu is not accessible, click the Right Mouse Button on the palette menu area. From the
pop-up menu, choose Show Scroll Bars. Use the scroll bars to access the option.) This will prompt you for a starting and ending point of a route. Make the starting point
on the metal contact between the two P-FETS. The pointer displays route_1 indicating that metal1 is routed. Once you have selected the starting point for the route, a
guide will appear showing you the clearance where you can place the route without any problems. Extend this route down to the contact near the N-FETS, double click to
complete the route. Notice how it is automatically drawn at the routing width specified in the processes file (3 microns for metal 1 and four microns for metal2). If you
need a different width wire, you need to use another method. Click Cancel on the prompt bar or hit Esc key to discontinue routing.
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If you get a dialog box as in Fig. 6, notifying you of an establishment of a connection, then respond Yes to the box if you want the connection to be made.
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21. Now, perform DRC to find out any errors in the layout. Go back to the Session palette and then select ICrules. Click on Check palette menu. OK the dialog box that
appears. ICrules would check for any violation and would print a message in the message area (bottom of the IC Window). If the Results field shows a 0 (zero) then the
layout has passed the design check. Otherwise, fix DRC violation using the Set Scan To > First to see the first violation. The violation is highlighted in the IC window
and the message area displays the violation. Fix the violation by going back to the SDL menu. Once the error is fixed, go back to the ICrules and perform a Check again
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d) The area defined by the polygon that intersects the selected object is removed from the selected object.
iii) Notch out by performing the following steps:
a) Position the cursor inside the selected polygon, then press and hold the Shift-Ctrl-Select (Left Mouse button) button. Alternatively, use Edit>Notch>Out pop up menu
(Right Mouse button).
b) Draw a rectangle that intersects the at least one edge of the selected polygon.
c) Release the Shift-Ctrl-Select button. The area defined by the polygon that is outside the selected object is added to the selected object.
For more complex notches than simple polygons, you can also draw the notching polygon by clicking the Select button at the vertices of the desired polygon and then
double clicking the Select button to complete the polygon to define the notch area. After the notch area is defined, the selected object remains highlighted until you
unselect it.
* Flip & Rotate
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