RIPPLE CARRY ADDER :4 BIT

DELAY:
Timing Summary:
--------------Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 13.521ns
AREA:

Device Utilization Summary

Logic Utilization

[-]

Used Available Utilization Note(s)

Number of 4 input LUTs

1,536

1%

Number of occupied Slices

768

1%

Number of Slices containing only related

logic

100%

0%

1,536

1%

14

124

11%

Number of Slices containing unrelated logic

Total Number of 4 input LUTs
Number of bonded IOBs
Average Fanout of Non-Clock Nets

1.71

RCA 8BIT
AREA :

Device Utilization Summary

Logic Utilization

[-]

Used Available Utilization Note(s)

Number of 4 input LUTs

16

1,536

1%

Number of occupied Slices

12

768

1%

12

12

100%

12

0%

Total Number of 4 input LUTs

16

1,536

1%

Number of bonded IOBs

26

124

20%

Number of Slices containing only related logic

Number of Slices containing unrelated logic

Average Fanout of Non-Clock Nets

1.73

DELAY :
Timing Summary:
--------------Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 19.776ns
POWER :

RCA 16 :
Timing Summary:-------------Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 31.744ns
AREA :

POWER :

RCA 32
AREA :

Device Utilization Summary

Logic Utilization

[-]

Used Available Utilization Note(s)

Number of 4 input LUTs

64

1,536

4%

Number of occupied Slices

48

768

6%

48

48

100%

48

0%

Total Number of 4 input LUTs

64

1,536

4%

Number of bonded IOBs

98

124

79%

Number of Slices containing only related logic

Number of Slices containing unrelated logic

Average Fanout of Non-Clock Nets

1.74

TIMMING
Timing Summary:
--------------Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 55.680ns
POWER :

RCA 64 :
AREA

Device Utilization Summary

Logic Utilization
Number of 4 input LUTs

[-]

Used Available Utilization Note(s)

128

66,560

1%

Number of occupied Slices

96

33,280

1%

Number of Slices containing only related

logic

96

96

100%

96

0%

Total Number of 4 input LUTs

128

66,560

1%

Number of bonded IOBs

194

633

30%

Average Fanout of Non-Clock Nets

1.75

Number of Slices containing unrelated logic

POWER

TIMING
Timing Summary:
--------------Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 103.552ns
RCA 128 :
AREA

Device Utilization Summary

Logic Utilization

[-]

Used Available Utilization Note(s)

Number of 4 input LUTs

256

66,560

1%

Number of occupied Slices

192

33,280

1%

192

192

100%

192

0%

Total Number of 4 input LUTs

256

66,560

1%

Number of bonded IOBs

386

633

60%

Average Fanout of Non-Clock Nets

1.75

Number of Slices containing only related logic

Number of Slices containing unrelated logic

Timing Summary:
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 199.296ns

POWER

BCD 4 BIT
Area

Device Utilization Summary

Logic Utilization
Number of 4 input LUTs

[-]

Used Available Utilization Note(s)

17

66,560

1%

Number of occupied Slices

33,280

1%

Number of Slices containing only related

logic

100%

0%

Total Number of 4 input LUTs

17

66,560

1%

Number of bonded IOBs

13

633

2%

Number of Slices containing unrelated logic

Average Fanout of Non-Clock Nets

2.91

Power

Timing Summary:
--------------Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 15.729ns

Bcd 8
Timing Summary:
--------------Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 25.678ns
Area

Device Utilization Summary

Logic Utilization

[-]

Used Available Utilization Note(s)

Number of 4 input LUTs

34

66,560

1%

Number of occupied Slices

19

33,280

1%

Number of Slices containing only related

logic

19

19

100%

19

0%

Total Number of 4 input LUTs

34

66,560

1%

Number of bonded IOBs

26

633

4%

Number of Slices containing unrelated logic

Average Fanout of Non-Clock Nets

2.74

BCD 16 :
Timing Summary:
--------------Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 44.001ns
Area

Device Utilization Summary

Logic Utilization

[-]

Used Available Utilization Note(s)

Number of 4 input LUTs

68

66,560

1%

Number of occupied Slices

37

33,280

1%

Number of Slices containing only related

logic

37

37

100%

37

0%

Total Number of 4 input LUTs

68

66,560

1%

Number of bonded IOBs

50

633

7%

Number of Slices containing unrelated logic

Average Fanout of Non-Clock Nets

2.83

Bcd32

Device Utilization Summary

Logic Utilization

[-]

Used Available Utilization Note(s)

Number of 4 input LUTs

68

66,560

1%

Number of occupied Slices

37

33,280

1%

Number of Slices containing only related

logic

37

37

100%

37

0%

Total Number of 4 input LUTs

68

66,560

1%

Number of bonded IOBs

50

633

7%

Number of Slices containing unrelated logic

Average Fanout of Non-Clock Nets

Timing Summary:
--------------Speed Grade: -4

2.83

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 44.001ns
Rca 64

Area

Device Utilization Summary

Logic Utilization

[-]

Used Available Utilization Note(s)

Number of 4 input LUTs

268

66,560

1%

Number of occupied Slices

146

33,280

1%

Number of Slices containing only related

logic

146

146

100%

146

0%

Total Number of 4 input LUTs

268

66,560

1%

Number of bonded IOBs

192

633

30%

Average Fanout of Non-Clock Nets

2.74

Number of Slices containing unrelated logic

Timing Summary:
--------------Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 154.147ns

Rca 128

Device Utilization Summary

Logic Utilization

[-]

Used Available Utilization Note(s)

Number of 4 input LUTs

503

66,560

1%

Number of occupied Slices

272

33,280

1%

Number of Slices containing only related

logic

272

272

100%

272

0%

Total Number of 4 input LUTs

503

66,560

1%

Number of bonded IOBs

369

633

58%

Average Fanout of Non-Clock Nets

2.72

Number of Slices containing unrelated logic

Timing Summary:
--------------Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 149.917ns