NuMicro Product Brief

NuMicro M058/M0516 Product Brief
ARM Cortex-M0
32-BIT MICROCONTROLLER
NuMicro Family
M058/M0516BN Product Brief
-1-
Publication Release Date: Mar. 19, 2012

Revision V1.01
TABLE OF CONTENTS
1
GENERAL DESCRIPTION 5
FEATURES 6
BLOCK DIAGRAM 11
SELECTION TABLE 12
PIN CONFIGURATION 13
5.1 QFN 33 pin 13
5.2 LQFP 48 pin 14
TYPICAL APPLICATION CIRCUIT 15
ELECTRICAL CHARACTERISTICS 16
7.1 Absolute Maximum Ratings 16
7.2 DC Electrical Characteristics 17
7.3 AC Electrical Characteristics 21
7.3.1
External Crystal 21
7.3.2
External Oscillator 21
7.3.3
Typical Crystal Application Circuits 22
7.3.4
Internal 22.1184 MHz RC Oscillator 23
7.3.5
Internal 10kHz RC Oscillator 23
7.4 Analog Characteristics 24
7.4.1
Specification of 12-bit SARADC24
7.4.2
Specification of LDO & Power management 25
7.4.3
Specification of Low Voltage Reset 26
7.4.4
Specification of Brown-Out Detector 26
7.4.5
Specification of Power-On Reset (5V) 26
7.4.6
Specification of Temperature Sensor 27
7.4.7
Specification of Comparator 27
7.5 Flash DC Electrical Characteristics 28
PACKAGE DIMENSIONS 29
8.1 LQFP-48 (7x7x1.4mm2 Footprint 2.0mm) 29
8.2 QFN-33 (5X5 mm2, Thickness 0.8mm, Pitch 0.5 mm) 30
REVISION HISTORY31
-2-

Revision V1.01
LIST OF FIGURES
Figure 3-1 NuMicro M051 Series Block Diagram ........................................................................ 11
Figure 4-1 NuMicro Naming Rule ................................................................................................ 12
Figure 5-1 NuMicro M051 Series QFN33 Pin Diagram ............................................................... 13
Figure 5-2 NuMicro M051 Series LQFP-48 Pin Diagram ........................................................... 14
Figure 7-1 Typical Crystal Application Circuit ................................................................................ 22
-3-

Revision V1.01
LIST OF TABLES
Table 4-1 NuMicro M051 Series Product Selection Guide ......................................................... 12
-4-

Revision V1.01
GENERAL DESCRIPTION
The NuMicro M051 series is a 32-bit microcontroller with embedded ARM Cortex-M0 core for
industrial control and applications which need rich communication interfaces. The Cortex-M0 is
the newest ARM embedded processor with 32-bit performance and at a cost equivalent to
traditional 8-bit microcontroller. The NuMicro M051 series includes M052, M054, M058 and
M0516 families.
The M058/M0516 can run up to 50 MHz. Thus it can afford to support a variety of industrial
control and applications which need high CPU performance. The M058/M0516 has 32K/64K-byte
embedded flash, 4K-byte data flash, 4K-byte flash for the ISP, and 4K-byte embedded SRAM.
Many system level peripheral functions, such as I/O Port, EBI (External Bus Interface), Timer,
UART, SPI, I2C, PWM, ADC, Watchdog Timer and Brownout Detector, have been incorporated
into the M058/M0516 in order to reduce component count, board space and system cost. These
useful functions make the M058/M0516 powerful for a wide range of applications.
Additionally, the M058/M0516 is equipped with ISP (In-System Programming) and ICP (In-Circuit
Programming) functions, which allow the user to update the program memory without removing
the chip from the actual end product.
-5-

Revision V1.01
FEATURES
Core
ARM Cortex-M0 core runs up to 50 MHz.
One 24-bit system timer.
Supports low power sleep-mode.
A single-cycle 32-bit hardware multiplier.
NVIC for the 32 interrupt inputs, each with 4-levels of priority.
Supports Serial Wire Debug (SWD) interface and 2 watchpoints/4 breakpoints.
Built-in LDO for Wide Operating Voltage Range: 2.5V to 5.5V
Memory
32KB/64KB Flash memory for program memory (APROM)
4KB Flash memory for data memory (DataFlash)
4KB Flash memory for loader (LDROM)
4KB SRAM for internal scratch-pad RAM (SRAM)
Clock Control
Programmable system clock source
4~24 MHz external crystal input
22.1184 MHz internal oscillator (trimmed to 3% accuracy)
10 kHz low-power oscillator for Watchdog Timer and wake-up in sleep mode
PLL allows CPU operation up to the maximum 50MHz
I/O Port
Up to 40 general-purpose I/O (GPIO) pins for LQFP-48 package
Four I/O modes:
Quasi bi-direction
Push-Pull output
-6-

Revision V1.01
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports high driver and high sink IO mode
Timer
Provides four channel 32-bit timers, one 8-bit pre-scale counter with 24-bit up-timer for
each timer.
Independent clock source for each timer.
24-bit timer value is readable through TDR (Timer Data Register)
Provides one-shot, periodic and toggle operation modes.
Provide event counter function.
Provide external capture/reset counter function equivalent to 8051 Timer2.
Watchdog Timer
Multiple clock sources
Supports wake up from power down or sleep mode
Interrupt or reset selectable on watchdog time-out
PWM
Built-in up to four 16-bit PWM generators; providing eight PWM outputs or four
complementary paired PWM outputs
Individual clock source, clock divider, 8-bit pre-scalar and dead-zone generator for each
PWM generator
PWM interrupt synchronized to PWM period
16-bit digital Capture timers (shared with PWM timers) with rising/falling capture inputs
Supports capture interrupt
UART
-7-

Revision V1.01
Up to two sets of UART device
Programmable baud-rate generator
Buffered receiver and transmitter, each with 15 bytes FIFO
Optional flow control function (CTS and RTS)
Supports IrDA(SIR) function
Supports RS485 function
Supports LIN function
SPI
Up to two sets of SPI device.
Supports master/slave mode
Full duplex synchronous serial data transfer
Provide 3 wire function
Variable length of transfer data from 1 to 32 bits
MSB or LSB first data transfer
Rx latching data can be either at rising edge or at falling edge of serial clock
Tx sending data can be either at rising edge or at falling edge of serial clock
Supports Byte suspend mode in 32-bit transmission
I2C
Supports master/slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial data

on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.
-8-

Revision V1.01
Programmable clocks allow versatile rate control.
Supports multiple address recognition (four slave address with mask option)
ADC
12-bit SAR ADC with 760k SPS
Up to 8-ch single-ended input or 4-ch differential input
Supports single mode/burst mode/single-cycle scan mode/continuous scan mode
Supports 2 complement/un-signed format in differential mode conversion result
Each channel with an individual result register
Supports conversion value monitoring (or comparison) for threshold voltage detection
Conversion can be started either by software trigger or external pin trigger
Analog Comparator
Up to 2 comparator analog modules
External input or internal band gap voltage selectable at negative node
Interrupt when compare result change
Power down wake up
EBI (External Bus Interface) for external memory-mapped device access
Accessible space: 64KB in 8-bit mode or 128KB in 16-bit mode
Supports 8-bit/16-bit data width
Supports byte-write in 16-bit data width
In-System Programming (ISP) and In-Circuit Programming (ICP)
One built-in temperature sensor with 1 resolution
Brown-Out Detector
With 4 levels: 4.3V/3.7V/2.7V/2.2V
Supports Brown-Out interrupt and reset option
96-bit unique ID
-9-

Revision V1.01
LVR (Low Voltage Reset)
Threshold voltage levels: 2.0V
Operating Temperature: -40~85
Packages:
Green package (RoHS)
48-pin LQFP, 33-pin QFN
- 10 -

Revision V1.01
BLOCK DIAGRAM
10K OSC
CONFIG
DATAFLASH 4KB
Cortex-M0
50 MHz
CLK_CTL
P
L
L
LDROM ISP 4KB
APROM
GPIO
P0~P4
SRAM
4KB
22M OSC
EXT. 4~24M
XTAL
LDO
2.5 ~ 5.5V
64KB(M0516)
32KB(M058)
Watch Dog Timer
SPI 0/1
AD[15:0]
Timer 0/1
nCS
nRD
nWR
mclk
ALE
nWRL
nWRH
ADC
EBI
Timer 2/3
UART 0/1
PWM 0~7
I2C
ADC
8ch/12bit
SARADC
760K SPS
PAD Control
POR
BOD
LVR
Analog
Comparator
Figure 3-1 NuMicro M051 Series Block Diagram
- 11 -

Revision V1.01
SELECTION TABLE
NuMicro M051 Series Selection Guide

Part number
APROM
RAM
Data
Flash
LDROM
I/O
Connectivity
Timer
COMP PWM
UART
SPI
I2C
ADC
EBI
ISP
ICP
Package
LQFP48
QFN33
LQFP48
QFN33
M058LBN
32KB
4KB
4KB
4KB
40
4x32-bit
8X12-bit
M058ZBN
32KB
4KB
4KB
4KB
24
4x32-bit
8X12-bit
M0516LBN
64KB
4KB
4KB
4KB
40
4x32-bit
8X12-bit
M0516ZBN
64KB
4KB
4KB
4KB
24
4x32-bit
8X12-bit
Table 4-1 NuMicro M051 Series Product Selection Guide
M0 5X - X X X
CPU core
ARM Cortex M0
Temperature
Part Number
N : - 40 ~ +85
E : - 40 ~+105
C : - 40 ~+125
58 : 32K Flash ROM

516 : 64K Flash ROM
Reserved
Package
L : LQFP 48
Z : QFN 33
Figure 4-1 NuMicro Naming Rule
- 12 -

Revision V1.01
PIN CONFIGURATION
5.1
QFN 33 pin
RXD1, RTS1, P0.1
TXD1, CTS1, P0.0
VDD
AVDD
AIN0, T2, P1.0
RXD1, AIN2, P1.2
TXD1, AIN3, P1.3
CPN0, AIN4, P1.4
32 31 30 29 28 27 26 25
CPP0, AIN5, P1.5
24 P0.4, SPISS1
RST
23 P0.5, MOSI_1
CPN1, RXD, P3.0
22 P0.6, MISO_1
AVSS
CPP1, TXD, P3.1
T0EX, STADC, INT0, P3.2
19 P4.6, ICE_CLK
SDA, T0, P3.4
18 P2.6, PWM6, CPO1
SCL, T1, P3.5
21 P0.7, SCLK1
QFN 33-Pin
20 P4.7, ICE_DAT
33 VSS
9
17 P2.5, PWM5
10 11 12 13 14 15 16
P2.4, PWM4
P2.3, PWM3
P2.2, PWM2
LDO_CAP
VSS
XTAL1
XTAL2
P3.6, CKO, CPO0
Top transparent view
Figure 5-1 NuMicro M051 Series QFN33 Pin Diagram
- 13 -

Revision V1.01
5.2
LQFP 48 pin
PWM2, P4.2
CPN0, SPISS0,AIN4,P1.4
TXD1,AIN3,P1.3
RXD1,AIN2, P1.2
nWRH, T3,AIN1,P1.1
nWRL, T2,AIN0,P1.0
AVDD
VDD
TXD1, CTS1, AD0, P0.0
RXD1, RTS1, AD1, P0.1
TXD, CTS0, AD2, P0.2
RXD, RTS0, AD3, P0.3
48
47
46
45
44
43
42
41
40
39
38
37
CPP0, MOSI_0, AIN5, P1.5
36
P4.1, PWM1, T3EX
MISO_0, AIN6, P1.6
35
P0.4, AD4, SPISS1
SPICLK0, AIN7, P1.7
34
P0.5, AD5, MOSI_1
RST
33
P0.6, AD6, MISO_1
CPN1, RXD, P3.0
32
P0.7, AD7, SPICLK1
AVSS
31
P4.7, ICE_DAT
CPP1, TXD, P3.1
30
P4.6, ICE_CLK
T0EX, STADC, INT0, P3.2
29
P4.5, ALE
T1EX, MCLK, INT1, P3.3
28
P4.4, /CS
SDA, T0, P3.4
10
27
P2.7, AD15, PWM7
SCL, T1, P3.5
11
26
P2.6, AD14, PWM6, CPO1
PWM3, P4.3
12
25
P2.5, AD13, PWM5
48-pin LQFP
P2.1, AD9, PWM1
P4.0, PWM0, T2EX
20
P2.0, AD8, PWM0
24
19
LDO_CAP
P2.4, AD12, PWM4
18
VSS
23
17
XTAL1
P2.3, AD11, PWM3
16
XTAL2
22
15
P3.7, RD
P2.2, AD10, PWM2
14
P3.6, WR, CKO, CPO0
21
13
Figure 5-2 NuMicro M051 Series LQFP-48 Pin Diagram
- 14 -

Revision V1.01
TYPICAL APPLICATION CIRCUIT

DVDD
DVDD
DVDD
LE
OE
L2
FB
AVDD
R1
10K
ALE
11
1
D0
D1
D2
D3
D4
D5
D6
D7
2
5
6
9
12
15
16
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
C1
10uF/10V
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
TANT-A
LE
OE
Reset Circuit
DVSS
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
U2
74F373
AVSS
20
AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
FB
nTICERST
3
4
7
8
13
14
17
18
VCC
11
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
L1
CB3
0.1 uF
CB4
0.1 uF
C2
20p
10
ALE
D0
D1
D2
D3
D4
D5
D6
D7
VCC
20
U1
74F373
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
7
8
13
14
17
18
DVDD
CB2
0.1 uF
GND
CB1
0.1 uF
10
D12MO
ADC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
AA5
AA6
AA7
nRD
ADC Input
CON1
1X2 HEADER
1
2
AD15
AD14
AD13
AD12
DVSS
DVDD
AD11
AD10
AD9
AD8
P11
RXD1
TXD1
nSS0
P42
C3
820pF
1
2
U4
M052_LQFP_48
CB5
0.1 uF
MOSI_0
MISO_0
SCLK0
nTICERST
RXD0
AVSS
TXD0
P32
P33
SDA
SCL
P43
AA8
AA9
AA10
AA11
AA12
BS616LV4017EG70(TSOP-44)
EBI
1
2
3
4
5
6
7
8
9
10
11
12
C4
20p
AVDD
DVDD
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
MOSI_0/AIN5/P1.5
MISO_0/AIN6/P1.6
SCLK0/AIN7/P1.7
RST
RXD/P3.0
AVSS
TXD/P3.1
INT0/P3.2
MCLK/INT1/P3.3
SDA/T0/P3.4
SCL/T1/P3.5
P4.3
XTAL3-1
AD0
AD1
AD2
AD3
D12MI
Crystal
48
47
46
45
44
43
42
41
40
39
38
37
A4
A3
A2
A1
A0
CS
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
P4.2
AIN3/SS0/P1.4
AIN3/TXD1/P1.3
AIN2/RXD1/P1.2
AIN1/T2/P1.1
AIN0/T2/P1.0
AVDD
VDD
P0.0/AD0/CTS1
P0.1/AD1/RTS1
P0.2/AD2/CTS0
P0.3/AD3/RTS0
CB6
0.1 uF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
X1
12MHz
ICEJP1
P4.1
P0.4/AD4/SS1
P0.5/AD5/MOSI_1
P0.6/AD6/MISO_1
M052_54 LQFP 48 P0.7/AD7/SCLK1
P4.7/ICE_DAT
P4.6/ICE_CLK
P4.5/ALE
P4.4/CS
P2.7/AD15/PWM7
P2.6/AD14/PWM6
P2.5/AD13/PWM5
36
35
34
33
32
31
30
29
28
27
26
25
1
3
5
7
9
P41
AD4
AD5
AD6
AD7
TICEDAT
TICECLK
ALE
nCS
AD15
AD14
AD13
P3.6/WR/CKO
P3.7/RD
XTAL2
XTAL1
VSS
LDO_CAP
P2.0/AD8/PWM0
P2.1/AD9/PWM1
P2.2/AD10/PWM2
P2.3/AD11/PWM3
P2.4/AD12/PWM4
P4.0
AA4
AA3
AA2
AA1
AA0
nCS
AD0
AD1
AD2
AD3
DVDD
DVSS
AD4
AD5
AD6
AD7
nWR
DVSS
DVSS
AA15
AA14
AA13
U3
2
4
6
8
10
TICEDAT
TICECLK
nTICERST
HEADER 5X2
HEADER5X2
ICE Interface
SPI
13
14
15
16
17
18
19
20
21
22
23
24
nWR
nRD
D12MO
D12MI
1
2
3
4
UART_RXD
UART_TXD
S1
8
7
6
5
P40
AD12
AD11
AD10
AD9
AD8
RXD0
TXD0
RXD1
TXD1
DVDD
DVDD
CB7
0.1 uF
C5
10uF
TANT-B
SW DIP-4
SWDIP8
RSPI1
4.7K
nSS1
MISO_1
MET22
RSPI2
4.7K
USPI1
W25X16VSSIG
1
2
3
4
CS#
DO
WP#
GND
VCC
HOLD#
CLK
DI
8
7
6
5
DVDD
MET23
SCLK1
MOSI_1
SOIC-8P
UART
C6
1uF
TANT-A
P1
11 VSS
1
6
2
7
3
8
4
9
5
10
VDD
C8 1uF
TANT-A
NET10
NET11
R3
33
R5
33
DB9-M ()
DB9L-HP
C7
1uF
TANT-A
I2C
DVDD
NET3
NET4
NET40
NET5
NET6
NET7
NET8
NET9
C9
1uF
TANT-A
1
2
3
4
5
6
7
8
U5
MAX232A
C1+
V+
C1C2+
C2VT2OUT
R2IN
SOP16/150
VCC
GND
T1OUT
R1IN
R1OUT
T1IN
T2IN
R2OUT
16
15
14
13
12
11
10
9
CB8
0.1 uF
DVDD
R4 33
NET12
NET13
EEPROM
ADDRESS:0H
UART_TXD
UART_RXD
R6 33
1
2
3
4
UI2C1
I2C-EEPROM
A0
A1
A2
GND
VCC
WP
SCL
SDA
RI2C1
4.7K
8
7
6
5
RI2C2
4.7K
CB9
0.1 uF
Title
SCL
SDA
M052_54 Application Circuit

Size
Document Number
Date:
Thursday , August 19, 2010
24LC64
SOIC8\1.27\5.6MM
- 15 -
Rev
Application.dsn
1.0
Sheet
of

Revision V1.01
ELECTRICAL CHARACTERISTICS
7.1
Absolute Maximum Ratings

SYMBOL
PARAMETER
MIN
MAX
UNIT
VDD VSS
-0.3
+7.0
VIN
VSS-0.3
VDD +0.3
1/tCLCL
24
MHz
TA
-40
+85
TST
-55
+150
120
mA
Maximum Current out of VSS
120
mA
Maximum Current sunk by a I/O pin
35
mA
Maximum Current sourced by a I/O

pin
35
mA
Maximum Current sunk by total I/O

pins
100
mA
Maximum Current sourced by total

I/O pins
100
mA
DC Power Supply
Input Voltage
Oscillator Frequency
Operating Temperature
Storage Temperature
Maximum Current into VDD
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
- 16 -

Revision V1.01
7.2
DC Electrical Characteristics
(VDD -VSS=2.5~5.5V, TA = 25C, FOSC = 50 MHz unless otherwise specified.)

SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
5.5
VDD =2.5V ~ 5.5V up to 50 MHz
Operation voltage
VDD
2.5
LDO Output Voltage
VLDO
1.7
1.8
1.9
VDD 2.5V
Band Gap Analog Input
VBG
-5%
1.20
+5%
VDD =2.5V ~ 5.5V
Analog Operating
Voltage
AVDD
VDD
Analog Reference
Voltage
Vref
AVDD
Operating Current
Normal Run Mode
@ 50 MHz
Operating Current
Normal Run Mode
@ 22Mhz
Operating Current
Normal Run Mode
@ 12Mhz
IDD1
20.6
mA
VDD = 5.5V@50MHz,
enable all IP and PLL, XTAL=12MHz
IDD2
14.4
mA
VDD =5.5V@50MHz,
disable all IP and enable PLL,
XTAL=12MHz
IDD3
18.9
mA
VDD = 3.3V@50MHz,
enable all IP and PLL, XTAL=12MHz
IDD4
12.8
mA
VDD = 3.3V@50MHz,
disable all IP and
XTAL=12MHz
IDD5
6.2
mA
VDD = 5.5V@22MHz,
enable all IP and IRC22M,
disable PLL
IDD6
3.4
mA
VDD =5.5V@22MHz,
disable all IP and enable IRC22M,
disable PLL
IDD7
6.1
mA
VDD = 3.3V@22MHz,
disable PLL
IDD8
3.4
mA
VDD = 3.3V@22MHz,
disable PLL
IDD9
5.3
mA
VDD = 5.5V@12MHz,
enable all IP and
XTAL=12MHz
IDD10
3.7
mA
VDD = 5.5V@12MHz,
disable all IP and disable PLL,
XTAL=12MHz
IDD11
4.0
mA
VDD = 3.3V@12MHz,
enable all IP and disable PLL,
XTAL=12MHz
IDD12
2.3
mA
VDD = 3.3V@12MHz,
disable all IP and disable PLL,
XTAL=12MHz
- 17 -
enable
disable
PLL,
PLL,

Revision V1.01
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
Operating Current
Normal Run Mode
@ 4 MHz
Operating Current
Normal Run Mode
@10Khz
Operating Current
Idle Mode
@ 50 MHz
Operating Current
Idle Mode
@ 22Mhz
Operating Current
Idle Mode
TYP.
MAX.
UNIT
IDD13
3.4
mA
VDD = 5.5V@4MHz,
enable all IP and
XTAL=4MHz
disable
PLL,
IDD14
2.6
mA
VDD = 5.5V@4MHz,
disable all IP and
XTAL=4MHz
disable
PLL,
IDD15
2.0
mA
VDD = 3.3V@4MHz,
enable all IP and
XTAL=4MHz
disable
PLL,
IDD16
1.3
mA
VDD = 3.3V@4MHz,
disable all IP and
XTAL=4MHz
disable
PLL,
IDD17
98.7
uA
VDD = 5.5V@10KHz,
enable all IP and IRC10K,
disable PLL
IDD18
97.4
uA
VDD = 5.5V@10KHz,
disable all IP and enable IRC10K,
disable PLL
IDD19
86.4
uA
VDD = 3.3V@10KHz,
disable PLL
IDD20
85.2
uA
VDD = 3.3V@10KHz,
disable PLL
IIDLE1
16.2
mA
VDD = 5.5V@50 MHz, enable all IP and

PLL, XTAL=12 MHz
IIDLE2
10.0
mA
VDD =5.5V@50 MHz, disable all IP and

enable PLL, XTAL=12 MHz
IIDLE3
14.6
mA
VDD = 3V@50 MHz, enable all IP and PLL,

XTAL=12 MHz
IIDLE4
8.5
mA
VDD = 3V@50 MHz, disable all IP and

enable PLL, XTAL=12 MHz
IIDLE5
4.3
mA
VDD = 5.5V@22MHz,
disable PLL
IIDLE6
1.5
mA
VDD =5.5V@22MHz,
disable PLL
IIDLE7
4.2
mA
VDD = 3.3V@22MHz,
disable PLL
IIDLE8
1.4
mA
VDD = 3.3V@22MHz,
disable PLL
IIDLE9
4.3
mA
VDD = 5.5V@12MHz,
enable all IP and
XTAL=12MHz
- 18 -
disable
PLL,

Revision V1.01
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
@ 12 MHz
Operating Current
Idle Mode
@ 4 MHz
Operating Current
Idle Mode
@10Khz
Standby Current
Power-down Mode
(Deep Sleep Mode)
IIDLE10
2.6
mA
VDD = 5.5V@12MHz,
disable all IP and
XTAL=12MHz
disable
PLL,
IIDLE11
2.9
mA
VDD = 3.3V@12MHz,
enable all IP and
XTAL=12MHz
disable
PLL,
IIDLE12
1.3
mA
VDD = 3.3V@12MHz,
disable all IP and
XTAL=12MHz
disable
PLL,
IIDLE13
3.0
mA
VDD = 5.5V@4MHz,
enable all IP and
XTAL=4MHz
disable
PLL,
IIDLE14
2.3
mA
VDD = 5.5V@4MHz,
disable all IP and
XTAL=4MHz
disable
PLL,
IIDLE15
1.7
mA
VDD = 3.3V@4MHz,
enable all IP and
XTAL=4MHz
disable
PLL,
IIDLE16
1.0
mA
VDD = 3.3V@4MHz,
disable all IP and
XTAL=4MHz
disable
PLL,
IIDLE17
97.8
uA
VDD = 5.5V@10KHz,
disable PLL
IIDLE18
96.5
uA
VDD = 5.5V@10KHz,
disable PLL
IIDLE19
85.5
uA
VDD = 3.3V@10KHz,
disable PLL
IIDLE20
84.4
uA
VDD = 3.3V@10KHz,
disable PLL
IPWD1
10
VDD = 5.5V, No load @ Disable BOV

function
IPWD2
10
VDD = 3.0V, No load @ Disable BOV

function
Input Current P0/1/2/3/4

(Quasi-bidirectional
mode)
IIN1
-75
+15
VDD = 5.5V, VIN = 0V or VIN= VDD
Input Leakage Current

P0/1/2/3/4
ILK
-1
+1
VDD = 5.5V, 0<VIN< VDD
Input Low Voltage

P0/1/2/3/4 (TTL input)
VIL1
-0.3
0.8
-0.3
0.6
VDD
+0.2
Input High Voltage

P0/1/2/3/4 (TTL input)
VIH1
2.0
- 19 -
V
V
VDD = 4.5V
VDD = 2.5V
VDD = 5.5V

Revision V1.01
SPECIFICATION
PARAMETER
Input Low Voltage

XT1[*2]
SYM.
VIL3
TEST CONDITIONS
MIN.
TYP.
MAX.
1.5
VDD
+0.2
0.8
0.4
3.5
VDD
+0.2
2.4
VDD
+0.2
UNIT
VDD =3.0V
V
VDD = 4.5V
VDD = 2.5V
VDD = 5.5V
Input High Voltage

XT1[*2]
VIH3
Negative going threshold

(Schmitt input), /RST
VILS
-0.5
0.2 VDD
Positive going threshold

(Schmitt input), /RST
VIHS
0.7 VDD
VDD
+0.5
Internal /RST pin pull up

resistor
RRST
40
150
Negative going threshold

(Schmitt input),
P0/1/2/3/4
VILS
-0.5
0.3 VDD
Positive going threshold

(Schmitt input),
P0/1/2/3/4
VIHS
0.7 VDD
VDD
+0.5
ISR11
-300
-370
-450
VDD = 4.5V, VS = 2.4V
ISR12
-50
-70
-90
VDD = 2.7V, VS = 2.2V
ISR13
-40
-60
-80
VDD = 2.5V, VS = 2.0V
ISR21
-20
-24
-28
mA
VDD = 4.5V, VS = 2.4V
ISR22
-4
-6
-8
mA
VDD = 2.7V, VS = 2.2V
ISR23
-3
-5
-7
mA
VDD = 2.5V, VS = 2.0V
Source Current
P0/1/2/3/4 (Quasibidirectional Mode)
Source Current
P0/1/2/3/4 (Push-pull
Mode)
VDD = 3.0V
ISK11
10
16
20
mA
Sink Current P0/1/2/3/4

(Quasi-bidirectional and
Push-pull Mode)
VDD = 4.5V, VS = 0.45V
ISK12
10
13
mA
VDD = 2.7V, VS = 0.45V
ISK13
12
mA
VDD = 2.5V, VS = 0.45V
Brown-Out voltage with

BOV_VL [1:0] =00b
VBO2.2
2.0
2.2
2.4
VDD =5.5V

BOV_VL [1:0] =01b
VBO2.7
2.5
2.7
2.9
VDD =5.5V

BOV_VL [1:0] =10b
VBO3.8
3.5
3.7
3.9
VDD =5.5V

BOV_VL [1:0] =11b
VBO4.5
4.1
4.3
4.5
VDD =5.5V
VBH
30
150
mV
Hysteresis range of BOD

voltage
VDD = 2.5V~5.5V
Notes:
1. /RST pin is a Schmitt trigger input.
2. XTAL1 is a CMOS input.
3. Pins of P0, P1, P2, P3 and P4 can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5V, 5he transition current
reaches its maximum value when Vin approximates to 2V .
- 20 -

Revision V1.01
7.3
AC Electrical Characteristics
7.3.1
External Crystal
t CLCL
t CLCH
t CLCX
tCHCL
Note:
t CHCX
Duty cycle is 50%.

PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
Clock High Time
tCHCX
20
nS
Clock Low Time
tCLCX
20
nS
Clock Rise Time
tCLCH
10
nS
Clock Fall Time
tCHCL
10
nS
7.3.2
CONDITION
External Oscillator
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Input clock frequency
External crystal
12
24
MHz
Temperature
-40
85
VDD
2.5
5.5
Operating current
12 MHz@ VDD = 5V
mA
- 21 -

Revision V1.01
7.3.3
Typical Crystal Application Circuits

CRYSTAL
C1
C2
Optional
4 MHz ~ 24 MHz
(Depend on crystal specification)
C1
XTAL1
XTAL2
C2
Figure 7-1 Typical Crystal Application Circuit
- 22 -

Revision V1.01
7.3.4
Internal 22.1184 MHz RC Oscillator

PARAMETER
CONDITION
MIN.
TYP.
Center Frequency
22.1184
7.3.5
MHz
-3
+3
-5
+5
VDD =5V
500
uA
CONDITION
MIN.
TYP.
MAX.
UNIT
2.5
5.5
Operating current
=5V
UNIT
VDD=2.5V~5.5V
DD
Calibrated Internal Oscillator

Frequency
MAX.
Internal 10kHz RC Oscillator

PARAMETER
Supply voltage
[1]
Center Frequency
10
kHz
-30
+30
VDD=2.5V~5.5V
-50
+50
VDD =5V
uA
DD =5V
Calibrated Internal Oscillator

Frequency
Operating current
Notes:
1. Internal operation voltage comes from LDO.
- 23 -

Revision V1.01
7.4
Analog Characteristics
7.4.1
Specification of 12-bit SARADC

PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
Resolution
12
Bit
Differential nonlinearity error
DNL
1.2
LSB
Integral nonlinearity error
INL
1.2
LSB
Offset error
EO
+3
+5
LSB
Gain error (Transfer gain)
EG
-4
-6
Monotonic
Guaranteed
ADC clock frequency
FADC
16
MHz
Conversion time
TADC
13
Clock
Sample rate
FS
760
K SPS
VLDO
1.8
VADD
5.5
IDD
0.5
mA
IDDA
1.5
mA
Input voltage range
VIN
AVDD
Capacitance
CIN
pF
Supply voltage
Supply current (Avg.)
- 24 -

Revision V1.01
7.4.2
Specification of LDO & Power management

RAMETER
MIN
TYP
MAX
UNIT
NOTE
Input Voltage
2.5
5.5
VDD input voltage
Output Voltage
-10%
1.8
+10%
LDO output voltage
Temperature
-40
25
85
1u
Resr=1ohm
Note:
1.
It is recommended a 100nF bypass capacitor is connected between VDD and the closest VSS
pin of the device.
2.
For ensuring power stability, a 1uF or higher capacitor must be connected between LDO pin
and the closest VSS pin of the device.
- 25 -

Revision V1.01
7.4.3
Specification of Low Voltage Reset

PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Operation voltage
2.5
5.5
Temperature
-40
25
85
Quiescent current
VDD =5.5V
uA
Temperature=25
1.7
2.0
2.3
Temperature=-40
2.3
Temperature=85
1.8
Threshold voltage
Hysteresis
7.4.4
Specification of Brown-Out Detector

Parameter
Condition
Min.
Typ.
Max.
Unit
Operation voltage
2.5
5.5
Quiescent current
AVDD =5.5V
140
Temperature
-40
25
85
BOV_VL[1:0]=11
4.1
4.3
4.5
BOV_VL [1:0]=10
3.5
3.7
3.9
BOV_VL [1:0]=01
2.5
2.7
2.9
BOV_VL [1:0]=00
2.0
2.2
2.4
30m
150m
Brown-Out voltage
Hysteresis
7.4.5
Specification of Power-On Reset (5V)

Parameter
Condition
Min.
Typ.
Max.
Unit
Temperature
-40
25
85
Reset voltage
V+
Quiescent current
Vin>reset voltage
nA
- 26 -

Revision V1.01
7.4.6
Specification of Temperature Sensor

PARAMETER
MIN.
TYP.
MAX.
UNIT
1.62
1.8
1.98
Temperature
-40
85
Gain
-1.72
-1.76
-1.80
mV/
717
725
733
mV
Supply voltage
CONDITIONS
[1]
Offset
Temp=0
Note[1]: Internal operation voltage comes from LDO.
7.4.7
Specification of Comparator
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Temperature
-40
25
85
VDD
2.4
5.5
VDD current
40
80
uA
Input offset voltage
10
20
mV
Output swing
0.1
VDD -0.1
Input common mode range
0.1
VDD -0.1
DC gain
70
dB
Propagation delay
@VCM=1.2 V and
VDIFF=0.1 V
200
ns
Hysteresis
@VCM=0.2 V ~ VDD -0.2V
10
mV
us
@CINP=1.3 V
Stable time
CINN=1.2 V
- 27 -

Revision V1.01
7.5 Flash DC Electrical Characteristics

SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
100000
UNIT
Nendu
Endurance
Tret
Retention time
Terase
Page erase time
19
20
21
ms
Tmess
Mess erase time
30
40
50
ms
Tprog
Program time
38
40
42
us
VDD
Supply voltage
1.62
1.8
1.98
Idd1
Read current
0.25
mA
Idd2
Program/Erase current
mA
Ipd
Power down current
20
uA
Temp=85
cycles
10
[1]
year
[2]
1. Number of program/erase cycles.

2. VDD is source from chip LDO output voltage.
3. Guaranteed by design, not test in production.
- 28 -

Revision V1.01
PACKAGE DIMENSIONS
8.1
LQFP-48 (7x7x1.4mm2 Footprint 2.0mm)

H
36
25
37
24
48
13
12
Controlling dimension : Millimeters
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Y
0
Dimension in inch
Dimension in mm
Min Nom Max
Min Nom Max
0.002 0.004
0.006
0.05
0.053 0.055
0.057
1.35
1.40
1.45
0.006 0.008
0.010
0.15
0.20
0.25
0.004 0.006
0.008
0.10
0.15
0.20
0.272 0.276
0.280
6.90
7.00
7.10
0.272 0.276
0.280
6.90
7.00
7.10
0.020 0.026
0.35
0.50
0.65
0.014
0.10
0.15
0.350
0.354
0.358
8.90
9.00
9.10
0.350
0.354
0.358
8.90
9.00
9.10
0.018
0.024
0.030
0.45
0.60
0.75
1.00
0.039
0.004
0
- 29 -
0.10
0

Revision V1.01
8.2
QFN-33 (5X5 mm2, Thickness 0.8mm, Pitch 0.5 mm)
- 30 -

Revision V1.01
REVISION HISTORY
VERSION
DATE
PAGE
V1.0
Oct 20, 2011
V1.01
Mar. 19, 2012
7.3.4
DESCRIPTION
Initial issued
Updated the Center Frequency of 22Mhz RC spec
- 31 -

Revision V1.01
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, Insecure Usage.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customers risk, and in the event that third parties lay
claims to Nuvoton as a result of customers Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
- 32 -

Revision V1.01

NuMicro Product Brief

Hochgeladen von

Dokumentinformationen

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

NuMicro Product Brief

Hochgeladen von

Copyright:

Verfügbare Formate

NuMicro M058/M0516 Product Brief

Publication Release Date: Mar. 19, 2012

NuMicro M058/M0516 Product Brief

TYPICAL APPLICATION CIRCUIT 15

Publication Release Date: Mar. 19, 2012

NuMicro M058/M0516 Product Brief

Publication Release Date: Mar. 19, 2012

NuMicro M058/M0516 Product Brief

Publication Release Date: Mar. 19, 2012

NuMicro M058/M0516 Product Brief

Publication Release Date: Mar. 19, 2012

NuMicro M058/M0516 Product Brief

ARM Cortex-M0 core runs up to 50 MHz.

One 24-bit system timer.

Supports low power sleep-mode.

A single-cycle 32-bit hardware multiplier.

NVIC for the 32 interrupt inputs, each with 4-levels of priority.

Supports Serial Wire Debug (SWD) interface and 2 watchpoints/4 breakpoints.

Built-in LDO for Wide Operating Voltage Range: 2.5V to 5.5V

32KB/64KB Flash memory for program memory (APROM)

4KB Flash memory for data memory (DataFlash)

4KB Flash memory for loader (LDROM)

4KB SRAM for internal scratch-pad RAM (SRAM)

Programmable system clock source

4~24 MHz external crystal input

22.1184 MHz internal oscillator (trimmed to 3% accuracy)

PLL allows CPU operation up to the maximum 50MHz

Up to 40 general-purpose I/O (GPIO) pins for LQFP-48 package

Four I/O modes:

Publication Release Date: Mar. 19, 2012

NuMicro M058/M0516 Product Brief

Input only with high impendence

TTL/Schmitt trigger input selectable

I/O pin can be configured as interrupt source with edge/level setting

Supports high driver and high sink IO mode

Independent clock source for each timer.

24-bit timer value is readable through TDR (Timer Data Register)

Provides one-shot, periodic and toggle operation modes.

Provide event counter function.

Provide external capture/reset counter function equivalent to 8051 Timer2.

Multiple clock sources

Supports wake up from power down or sleep mode

Interrupt or reset selectable on watchdog time-out

PWM interrupt synchronized to PWM period

Supports capture interrupt

Publication Release Date: Mar. 19, 2012

NuMicro M058/M0516 Product Brief

Up to two sets of UART device

Programmable baud-rate generator

Buffered receiver and transmitter, each with 15 bytes FIFO

Optional flow control function (CTS and RTS)

Supports IrDA(SIR) function

Supports RS485 function

Supports LIN function

Up to two sets of SPI device.

Supports master/slave mode

Full duplex synchronous serial data transfer

Provide 3 wire function

Variable length of transfer data from 1 to 32 bits

MSB or LSB first data transfer

Supports Byte suspend mode in 32-bit transmission

Supports master/slave mode

Bidirectional data transfer between masters and slaves

Multi-master bus (no central master).