Fall 2014

Computer Architecture
Course Code: CS-207 / EE-205
Credit Hours: 3
Pre-Requisite: Computer Logic Design
Instructor: Aftab Alam (Email: aftab.alam@gift.edu.pk)
Class Timings: Saturday 12:00 01:15 pm
1:30 02:45 pm
Venue: F-6
Office Hours: 10:00 11:00 am (Saturday)
03:00 03:30 pm (Saturday)

Course Objectives
A computer system comprises of many layers of application software, system software, firmware and
hardware. This course will explore the computer firmware and hardware below the computer languages and
operating systems.
During the initial phase of this course, students will be introduced with the internal working and design of a
simple hypothetical microprocessor. Both (hardwired control and micro-programmed control) types of
processors will be discussed and designed in this part of the course. Introduction to ISA (Instruction Set
Architecture) and Computer Arithmetic will also be covered at this stage of the course.
We will then shift to the other text book by Patterson & Hennessy from where will learn assembly language
programming for ARM processor. Finally we will concentrate on some advanced techniques (e.g., pipelining
and cache memories etc.) used to enhance the performance of processors. For this purpose ARM processors
architecture will be discussed as an example architecture.
At the end of the course, students will be able to
understand the internal working of a P
design a P if Instruction Set is provided
microprogram a P
understand the concepts of pipelining and superscalar architectures
understand the need and working of different levels of memory
interfacing memory to the P
interfacing I/O to the P

Text Books

1. M. Morris Mano, Computer System Architecture (3rd Edition 1993, Prentice Hall)
2. David A. Patterson, John L. Hennessy, Computer Organization & Design: The Hardware/Software
Interface ARM Edition (4th Edition 2010, Morgan Kaufmann)

Fall 2014
Topics to be covered
Basics
Internal Organization of a processor
Fetch-Decode-Execute Cycle
External Interface of a processor
Register Transfer and Microoperations
RTL (Register Transfer Language)
Register Transfer
Bus and memory transfers
Arithmetic, Logic and Shift -operations
Basic Computer Organization and Design
Instruction Codes
Computer Registers
Computer Instructions
Timing and Control
Instruction Cycle
Memory Reference Instructions
Input-Output and Interrupt
Complete Computer Description
Design of Basic Computer
Design of Accumulator Logic
Micropgrammed Control
Control Memory
Address Sequencing
-program example
Design of Control Unit
Computer Arithmetic
Addition and Subtraction
Logical Operations and Constructing an ALU
Multiplication and Division Algorithms
Floating-Point Arithmetic Operations

10 %
10 %
20 %

Number of weeks

Text1
(Chapter 4)

Text1
(Chapter 5)

Text1
(Chapter 7)

Text1
(Chapter 10)

Text2
(Chapter 3)

Instructions: Language of the Computer

ARM Assembly Language
Assessing and Understanding Performance
Introduction
CPU Performance and Its Factors
Evaluating Performance
The Processor: Datapath and Control
Building a Datapath
A Simple Implementation Scheme
An Overview of Pipelining
Pipeline Datapath and Control
Data Hazards: Forwarding versus Stalling
Control Hazards
Exceptions
Large and Fast: Exploiting Memory Hierarchy
Introduction
The Basics of Caches
Measuring and Improving Cache Performance
Virtual Memory
A common framework for Memory Hierarchies
Evaluation Criteria:
Assignments
Project
Midterm

Book

Text2
(Chapter 2)
Text2
(Chapter 4)

Text2
(Chapter 4)

Text2
(Chapter 5)

Quizzes

10 %

Final

50 %