Addressing Modes

The method used to identify the location of an operand.

General details
Almost always, one operand is held in a register.

Addressing mode refers to the other operand.

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Various addressing modes provided for different purposes.

Effective address the actual address of the operand after all

address computations of the addressing mode have been
performed.

In assembly language, different notations are used to specify

addressing mode.

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Size of data transfer

Memory organized as set of bytes (8 bits). A 32-bit processor would
have 32-bit registers. May be several sizes of transfer allowed:

8 bits from memory to least significant 8 bits of register or vice

versa.
16 bits from two consecutive memory locations to least
significant 16 bits of register or vice versa (uncommon in RISCs)
32 bits from four consecutive memory locations to full 32 bits of
register or vice versa.

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Size of data transfer

Size of transfer needs to be specified.

In assembly language, different operation mnemonics or different

notations used to specify size of transfer.

Example
ADD means add 32 bit numbers
ADDB means add 8 bit numbers

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Fundamental Addressing Modes

Direct Addressing (also called Absolute Addressing)

Immediate Addressing

Register (Direct) Addressing

Register Indirect Addressing

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Direct (or Absolute) Addressing

The operand is in memory and the memory address of the operand
is held in instruction:

Instruction
Operation

Memory address

Memory location
Operand

This was the method used to describe the formats previously.

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Direct (Absolute) Addressing Example

LD R2,[100] ;R2=contents of memory, address is 100
Processor
Instruction
LD

100

Registers

Memory
100

R2

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Another Direct (Absolute) Addressing Example

ST [100], R2 ;memory whose address is 100 = R2
Processor
Instruction
ST

100

Registers

Memory
100

R2

Mnemonic for this instruction may be MOV (move) or ST (store),

depending upon the manufacturers notation, see later.
Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Size of data transfer

Example
LD means load 32 bit number to register
ST store 32 bit number to memory

LB means load 8 bit number to register

SB stote 8 bit number to memory

Mnemonic for LD and ST instruction may be MOV (move)

depending upon the manufacturers notation and size may be
indicated in other ways.
Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Immediate Addressing
The operand is held in the instruction:
Instruction
Operation

Operand

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Immediate Addressing Example

MOV R2,123

;R2 = 123

Processor
Instruction
MOV
2
123
Registers

R2

Useful for constants. For example int x = 123;

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Immediate addressing used in compiled code

Useful for constants.

For example:
High level code

Assembly language statements

int x = 123;

MOV R1,123

a = b + 34;

ADD R3, R4, 34

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Register Direct Addressing

The operand is held in a register which is specified in instruction.

Instruction
Operation

Register no.

Register
Operand

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Register (direct) Addressing Example

MOV R3, R2

;R3 = R2

Processor
Instruction
MOV
3

Registers

R3
R2

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Register direct addressing used in compiled code

Useful for integer variables.

For example:
High level code

Assembly language statements

x = y;

MOV R1,R2

a = b + c;

ADD R3, R4, R5

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Register Indirect Addressing

The operand is held in memory. The address of the operand
location is held in a register which is specified in instruction.
Instruction
Operation

Register no.

Register
Memory address

Memory location
Operand

Useful for accessing different memory locations such as list of

consecutive locations. Contents of register can be incremented
after each access to point to the next location.
Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Register Indirect Addressing Example

LD R3,[R2]

;R3=contents of memory, address in R2

[ ] read as contents of memory Processor

Instruction
LD
3
Memory

Registers

120
R3
R2

120

In this example, R2 holds the number 120

.
(For clarity here and later, omitted that memory transfer has 32 bits (4 consecutive bytes) if 32-bit registers.
Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Register indirect addressing used in compiled code

In C, for pointers. For example:
High level code
int *b;
int a; a,

Assembly language statements

ptr, a pointer
integer variable in memory, say location 120

b = &a;

b = address of a

MOV R1,120

*b = 123;

location pointed by b = 123

LD [R1],123

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Register Indirect Addressing plus Offset

Similar to register indirect addressing except an offset held in the
instruction is added to register contents to form the effective
address:

Instruction
Operation

Register no.

Address
Register

Offset

Operand
Memory location

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Register Indirect Addressing Plus Offset

Example
LD R3,100[R2]

;R3=contents of memory, address

;in R2 + 100
Processor
Instruction
LD
3

Memory

100

Registers

220
R3
R2

120

+
In this example,
R2 holds the number 120
Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Register Indirect Addressing Variation

Index Register Addressing
Register indirect addressing in which register seen as an index
into a list (one dimensional array).
Register holds number of locations from starting point (first item in
list). Starting point given in instruction.

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Index Register Addressing Example

Memory

C code
i
R2
100
Instruction

3
2
1
0

x = a[i];

a[i]
Assembly language

LB R1,100[R2]

a[0]
Load byte

Here, compiler uses R1 for x, R2 for i and starting address for array
a is location 100. (a[] assumed a character array in figure. If a[] is
an integer array, would use LD and need to multiply index by 4.
Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Implied Addressing
Some operations have an implicit location for the operand and its
address need not be specified.

We will come across such

operations later.

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Specifying addressing mode in machine

instruction
Can be specified:

Within operation field (or is implied in operation) or

In a separate mode field

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Addressing Mode Specified in Separate Field

Instruction

Operation

Addressing mode

Actual encoding can be more complex that this.

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Size of Transfer Specified in Separate Field

Instruction

Operation

Size of transfer

Again, this detail is not shown in the following.

Actual encoding can be much more complex that this (e.g. Pentium
highly complex).

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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Quiz
1. Identify the addressing mode of each of the following hypothetical
machine instructions.

LD R2, [R3]
LD R2, [100]
LD R2, 100[R3]
MOV R2, 6

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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2. Which machine instruction addressing mode would be

appropriate for implementing the high level language statement:

x = 5;
if x is held in a register, say R1? Give an illustrative example.

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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3. What does the following assembly language code sequence do?

LD R10, 100[R2]
LD R11, 104[R2]
ST 100[R2],R11
ST 104[R2],R10

(This is not an efficient sequence for a pipelined processor. It can be written better -- we
will see why much later.)

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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4. What would be the decimal value in register R1 after the following

sequence?
Comments
SUB R1, R1, R1

; R1 = R1 - R1

ADD R1, R1, 5

; R1 = R1 + 5

DIV R1, R1, 2

; R1 = R1 / 2

MUL R1, R1, 2

; R1 = R1 * 2

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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5. Write an assembly language sequence for the following high

level language sequence, using register indirect addressing. Make
your own asssignment of registers to variables, but state them.

char a[5], b[5];

.
.
.
i = 2;
a[i-1] = b[i+1];

Barry Wilkinson 2008. This material is for sole and exclusive use of students enrolled at UNC-Charlotte. It is not to be sold, reproduced, or generally distributed.

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