2. In the decimal numbering system, what is the MSD?

A.The middle digit of a stream of numbers

B. The digit to the right of the decimal point
C. The last digit on the right
D.The digit with the most weight
7. What are the symbols used to represent digits in the binary number system?
A.0,1
B. 0,1,2
C. 0 through 8
D.1,2
The output of an AND gate is LOW ________.
A.all the time
B. when any input is LOW
C. when any input is HIGH
D.when all inputs are HIGH
Give the decimal value of binary 10010.
A.610
C. 1810

B. 910
D.2010

The output of a NOT gate is HIGH when ________.

A.the input is LOW
B. the input is HIGH
C. the input changes from LOW to HIGH
D.voltage is removed from the gate
The output of an OR gate is LOW when ________.
A.all inputs are LOW
B. any input is LOW
C. any input is HIGH
D.all inputs are HIGH
A flip-flop has ________.
A.one stable state
B. no stable states
C. two stable states
D.none of the above

Convert the fractional binary number 0000.1010 to decimal.

A.0.625
B. 0.50
C. 0.55
D.0.10

Convert the fractional decimal number 6.75 to binary.

A.0111.1100
B. 0110.1010
C. 0110.1100
D.0110.0110

Give the decimal value of binary 10000110.

A.13410
C. 11010

B. 14410
D.12610

Convert the fractional binary number 0001.0010 to decimal.

A.1.40
B. 1.125
C. 1.20
D.1.80
How many binary bits are necessary to represent 748 different numbers?
A.9
B. 7
C. 10
D.8
How many unique symbols are used in the decimal number system?
A.One
B. Nine
C. Ten
D.Unlimited

If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the
output is HIGH, the gate is a(n):
A.AND
B. NAND
C. NOR
D.OR
The output of an OR gate with three inputs, A, B, and C, is LOW when ________.
A.A = 0, B = 0, C = 0
B. A = 0, B = 0, C = 1
C. A = 0, B = 1, C = 1
D.all of the above
Which of the following logical operations is represented by the + sign in Boolean algebra?
A.inversion
B. AND
C. OR
D.Complementation

Output will be a LOW for any case when one or more inputs are zero for a(n):
A.OR gate
B. NOT gate
C. AND gate
D.NOR gate
The format used to present the logic output for the various combinations of logic inputs to a gate
is called a(n):
A.Boolean constant
B. Boolean variable
C.truth table
D.input logic function

If a 3-input AND gate has eight input possibilities, how many of those possibilities will result in
a HIGH output?
A.1
B. 2
C. 7
D.8
What does the small bubble on the output of the NAND gate logic symbol mean?
A.open collector output
B. Tristate
C. The output is inverted.
D.none of the above
How many inputs of a four-input AND gate must be HIGH in order for the output of the logic
gate to go HIGH?
A.any one of the inputs
B. any two of the inputs
C. any three of the inputs
D.all four inputs

Logically, the output of a NOR gate would have the same Boolean expression as a(n):
A.NAND gate immediately followed by an inverter
B. OR gate immediately followed by an inverter
C. AND gate immediately followed by an inverter
D.NOR gate immediately followed by an inverter

The output of an exclusive-OR gate is HIGH if ________.

A.all inputs are LOW
B. all inputs are HIGH
C. the inputs are unequal
D.none of the above

How many input combinations would a truth table have for a six-input AND gate?
A.32
B. 48
C. 64
D.128
(2^6)

The logic expression for a NOR gate is ________.

A.
B.
C.
D.
With regard to an AND gate, which statement is true?
A.An AND gate has two inputs and one output.
B. An AND gate has two or more inputs and two outputs.
C. If one input to a 2-input AND gate is HIGH, the output reflects the other input.
D.A 2-input AND gate has eight input possibilities.

Which of the following gates is described by the expression

A.OR
B. AND
C. NOR
D.NAND
Derive the Boolean expression for the logic circuit shown below:

A.
B.
C.
D.

The commutative law of Boolean addition states that A + B = A B.

A.True
B.False
Applying DeMorgan's theorem to the expression
A.
B.
C.
D.

, we get ________.

How many gates would be required to implement the following Boolean expression before
simplification? XY + X(X + Z) + Y(X + Z)
A.1
B. 2
C. 4
D.5
AC + ABC = AC
A.True

B.False

When
are the inputs to a NAND gate, according to De Morgan's theorem, the output
expression could be:
A.X = A + B
B.
C. X = (A)(B)
D.
Which Boolean algebra property allows us to group operands in an expression in any order
without affecting the results of the operation [for example, A + B = B + A]?
A.associative
B. commutative
C. Boolean
D.distributive

Use Boolean algebra to find the most simplified expression for

F = ABD + CD + ACD + ABC + ABCD.
A.F = ABD + ABC + CD
B. F = CD + AD
C. F = BC + AB
D.F = AC + AD
The NAND or NOR gates are referred to as "universal" gates because either:
A.can be found in almost all digital circuits
B. can be used to build all the other types of gates
C. are used in all countries of the world
D.were the first gates to be integrated

Which of the examples below expresses the commutative law of multiplication?

A.A + B = B + A
B. AB = B + A
C. AB = BA
D.AB = A B

Implementing the expression AB + CDE using NAND logic, we get:

A.(A)
C. (C)

Implementing the expression

B. (B)
D.(D)

with NOR logic, we get:

A.(A)
C. (C)
To implement the expression
A.three AND gates and three inverters
B. three AND gates and four inverters
C. three AND gates
D.one AND gate

B. (B)
D.(D)
, it takes one OR gate and ________.

How many AND gates are required to implement the Boolean expression,
?
A.1
B. 2
C. 3
D.4
The inverter can be produced with how many NAND gates?
A.1
B. 2
C. 3
D.4

Implementing the expression

A.(A)
C. (C)

Implementing the expression

using NAND logic, we get:

B. (B)
D.(D)

using NAND logic, we get:

A.(A)
C. (C)

B. (B)
D.(D)

Implementation of the Boolean expression

A.three AND gates, one OR gate
B. three AND gates, one NOT gate, one OR gate
C. three AND gates, one NOT gate, three OR gates
D.three AND gates, three OR gates

results in ________.

How many 2-input NOR gates does it take to produce a 2-input NAND gate?
A.1
B. 2
C. 3
D.4
logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is a(n):
A.Ex-NOR gate
B. OR gate
C. Ex-OR gate
D.NAND gate
Identify the type of gate below from the equation
A.Ex-NOR gate
B. OR gate
C. Ex-OR gate
D.NAND gate

The timing network that sets the output frequency of a 555 astable circuit contains ________.
A.three external resistors are used
B. two external resistors and an external capacitor are used
C. an external resistor and two external capacitors are used
D.no external resistor or capacitor is required

What is another name for a one-shot?

A.Monostable
C. Bistable

B. Multivibrator
D.Astable

Which of the following is correct for a gated D flip-flop?

A.The output toggles if one of the inputs is held HIGH.
B. Only one of the inputs can be HIGH at a time.
C. The output complement follows the input when enabled.
D.Q output follows the input D when the enable is HIGH
A 555 operating as a monostable multivibrator has an R1 of 1 M . Determine C1 for a pulse
width of 2 s.
A.1.8 F
B. 18 F
C. 18 pF
D.18 nF
Which of the following describes the operation of a positive edge-triggered D flip-flop?
A.If both inputs are HIGH, the output will toggle.
B. The output will follow the input on the leading edge of the clock.
C. When both inputs are LOW, an invalid state exists.
The input is toggled into the flip-flop on the leading edge of the clock and is passed to the
D.
output on the trailing edge of the clock.
What is the hold condition of a flip-flop?
A.both S and R inputs activated
B. no active S or R input
C. only S is active
D.only R is active
In a 555 timer, three 5 k resistors provide a trigger level of ________.
A.1/4 VCC and a threshold level 1/2 VCC
B. 1/3 VCC and a threshold level 3/4 VCC
C. 1/3 VCC and a threshold level 2/3 VCC
D.1/4 VCC and a threshold level 2/3 VCC
What is one disadvantage of an S-R flip-flop?
A.It has no enable input.
B. It has an invalid state.
C. It has no clock input.
D.It has only a single output.

The output pulse width for a 555 monostable circuit with R1 = 3.3 k
________.
A.7.3 s
B. 73 s
C. 7.3 ms
D.73 ms

and C1 = 0.02

F is

Use Formula T = 1.1 RC

The output of a gated S-R flip-flop changes only if the:

A.flip-flop is set
B. control input data has changed
C. flip-flop is reset
D.input data has no change

The pulse width of a one-shot circuit is determined by ________.

A.a resistor and capacitor
B. two resistors
C. two capacitors
D.none of the above

If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
A.No change will occur in the output.
B. An invalid state will exist.
C. The output will toggle.
D.The output will reset.

What is the function of the comparators in the 555 timer circuit?

A.to compare the output voltages to the internal voltage divider
B. to compare the input voltages to the internal voltage divider
C. to compare the output voltages to the external voltage divider
D.to compare the input voltages to the external voltage divider

What does the discharge transistor do in the 555 timer circuit?

A.charge the external capacitor to stop the timing
B. charge the external capacitor to start the timing over again
C. discharge the external capacitor to stop the timing
D.discharge the external capacitor to start the timing over again

The internal circuitry of the 555 timer consists of ________, an R-S flip-flop, a transistor switch,
an output buffer amplifier, and a voltage divider.
A.a comparator
B. a voltage amplifier
C. two comparators
D.a peak detector

With most monostable multivibrators, what is the Q output when no input trigger has occurred?
A.LOW
B. +5 V
C. SET
D.HIGH
An astable multivibrator requires:
A.balanced time constants
B. a pair of matched transistors
C. no input signal
D.dual J-K flip-flops

What is the difference between an astable multivibrator and a monostable multivibrator?

A.The astable is free running.
B. The astable needs to be clocked.
C. The monostable is free running.
D.none of the above
Determine tHI and tLO for the circuit given below.

A.tHI = 7.95
B. tHI = 6.24
C. tHI = 3.97
D.tHI = 3.21

s, tLO = 6.24
s, tLO = 7.95
s, tLO = 3.21
s, tLO = 3.97

s
s
s
s

USE TIME CONSTANT FORMULAS OF ASTABLE MULTIVIBRATORS

The output of the astable circuit ________.

A.constantly switches between two states
B. is LOW until a trigger is received
C. is HIGH until a trigger is received
D.floats until triggered

A monostable 555 timer has the following number of stable states:

A.0
B. 1
C. 2
D.3
What is the duty cycle of the waveform at the output of the circuit given below?

A.78%
C. 50%

B. 56%
D.44%

What is another name for a bistable multivibrator?

A.an on-off switch
B. an oscillator
C. a flip-flop

An astable 555 timer has the following number of stable states:

A.0
B. 1
C. 2
D.3
What is the output pulse width of the waveform at the output of the circuit in the given figure?

A.1.65 ms
B. 18.2 ms
C. 4.98 ms
D.54.6 ms