Static Logic Circuits :

based on static, or steady-state, behavior of simple nMOS or CMOS

structures
all valid output levels in static gates are associated with steady-state
operating points of the circuit in question.
static logic gate generates its output corresponding to the applied
input voltages after a certain time delay, and it can preserve its
output level (or state) as long as the power supply is provided.
require a large number of transistors to implement a function,
and cause a considerable time delay.

Dynamic logic circuits :

Used in high-density, high-performance digital implementations
where reduction of circuit delay and silicon area is a major
objective
The operation of all dynamic logic gates depends on temporary
(transient) storage of charge in parasitic node capacitances, instead
on steady-state circuit behaviour.
Require periodic updating of internal node voltage levels, since
stored charge in a capacitor discharges
So, dynamic logic circuits require periodic clock signals in order to
control charge refreshing.
The capability of temporarily storing a state, i.e., a voltage level, at
a capacitive node allows us to implement very simple sequential
circuits with memory functions.

use of common clock signals throughout the system enables us to

synchronize the operations of various circuit blocks.
the dynamic logic implementation of complex functions generally
requires less number of transistors and so a smaller silicon area
than does the static logic implementation.
implementation in a smaller area will, in many cases, consume less
power than the static logic
Disadvantages of dynamic logic are clocking synchronization and
timing and difficult to design
The dynamic logic has two phases,
Precharge : clock applied to charge the capacitance
Evaluate : clock to discharge the capacitance depending on the
condition of logic inputs, and the value of logic function is obtained

Basic Principle of Pass

Transistor Circuits
D-latch : if CK = 1 Q(n+1) = D;
if CK = 0 Q(n+1) = Q(n) --- no change
Static CMOS logic implementation

No. of transistors =
2+2*6+4*2 = 22

Dynamic logic implementation (dynamic D-latch)

No. of transistors = 3

Logic "1" Transfer

MP will operate in saturation throughout this cycle since

VDS = VGS. Consequently, VDS > VGS -VT,n

Logic "0" Transfer

Cx discharges from its max.
Vx (t=0) = Vmax = VDD -

VT,n to Vx = 0
So, Vx (t > 0) < VDD -VT,n
i.e., VDS < VGS -VT,n
MP will operate in linear throughout this cycle

Synchronous Dynamic Circuit Techniques

Consider the generalized view of a multi-stage synchronous circuit
shown in Fig,

To drive the pass transistors in this system, two non-overlapping

clock signals,
and , are used.

only one of the two clock signals can be active, as illustrated in Fig.
9.15.
When clock , is active, the input levels of Stage 1 (and also of
Stage 3) are applied through the pass transistors, while the input
capacitances of Stage 2 retain their previously set logic levels.
During the next phase, when clock
is active, the input level of
Stage 2 will be applied through the pass transistors, while the input
capacitances of Stage 1 and Stage 3 retain their logic levels.
This allows us simple dynamic memory function at each stage
input, and at the same time, synchronous operation by controlling
the signal flow in the circuit using the two periodic clock signals.
This signal timing scheme is also called two-phase clocking and is
one of the most widely used timing strategies.

depletion-load nMOS, enhancement-load nMOS, or CMOS logic

circuits can be used for implementing the combinational logic.
Example 1: depletion-load dynamic shift register circuit, in which
the input data are inverted once and transferred, or shifted into the
next stage during each clock phase,

operation : During the active phase of the input voltage level Vin
is transferred into the input capacitance Cin1.
Thus, the valid output voltage level of the first stage is determined
as the inverse of the current input during this cycle.
When
becomes active during the next phase, the output voltage
level of the first stage is transferred into the second stage input
capacitance Cin2, and the valid output voltage level of the second
stage is determined, first-stage input capacitance continues to retain
its previous level via charge storage.
When
becomes active again, the original data bit written into the
register during the previous cycle is transferred into the third stage,
and the first stage can now accept the next data bit.

Example 1.1:

Example 2 : enh.-load dynamic shift register circuit : difference is

that, instead of biasing the load transistors with a constant gate
voltage, we apply the clock signal to the gate of the load transistor
as well.
Example 2.1: ratioed dynamic logic : where in each stage the input
pass transistor and the load transistor are driven by opposite clock
phases,
and .

When
is active, the input voltage level Vin is transferred into the
first-stage input capacitance Cin1 through the pass transistor. In this
phase, the enhancement-type nMOS load transistor of the first-stage
inverter is not active.
During the next phase (active ), the load transistor is turned on.
Since the input logic level is still stored in Cin1, the output of the
first inverter stage attains its valid logic level.
At the same time, the input pass transistor of the second stage is
also turned on, which transfers this new output level into the input
capacitance Cin2 of the second stage.
When clock
becomes active again, the valid output level across
Cout2 is determined, and transferred into Cin3. Also, a new input level
can be input into Cin1, during this phase.
Since the power supply current flows only when the load devices
are activated by the clock signal, the overall power consumption of
dynamic enhancement-load logic is generally lower than for
depletion-load nMOS logic.

General circuit structure of ratioed synchronous dynamic logic,

Example 2.2: ratioless dynamic logic : where in each stage the

input pass transistor and the load transistor are driven by the same
clock phase.

General circuit structure of ratioless synchronous dynamic logic,

Dynamic CMOS circuit techniques

CMOS Transmission Gate Logic
each transmission gate is actually controlled by the
clock signal and its complement. As a result, two-phase clocking in
CMOS transmission
gate logic requires that a total of four clock signals are generated
and routed throughout the circuit.

Dynamic CMOS Logic (Precharge-Evaluate Logic)

A dynamic CMOS circuit technique which allows us to
significantly reduce the number of transistors used to implement

any logic function.

The circuit operation is based on first precharging the output node
capacitance and subsequently, evaluating the output level according
to the applied inputs.
Both of these operations are scheduled by a single clock signal,
which drives one nMOS and one pMOS transistor in each dynamic
stage.
Example : NAND2 gate : out = (AB)

domino CMOS logic

Cascading problem in Precharge-Evaluate Logic :

When is low (precharge phase) pMOS of stage1, 2 are ON so C1,

2 both charge and so Vout1 and Vout2 goes to high, the external inputs
are applied during this phase.
The input variables of the first stage are assumed to be such that the
output Vout1 will drop to logic "0" during the evaluation phase (A =
B = 1), and so Vout2 should be 0 nand 1 = 1, but
When the evaluation phase begins, both output voltages Vout1 and
Vout2 are logic-high (C1, 2 both charged). The output of the first
stage (Vout1) drops to its correct logic level (0) after a certain time
when C1 discharges (as A = B = 1 and is high, so C1 has
discharge path).

Also due to Vout1 and C1 is high at the beginning of the evaluation

phase and is high so all nMOS of stage 2 are ON so C2
discharges, so Vout2 becomes low which should not be.
To overcome this we add an inverter at the output of each stage,

Domino CMOS logic gates allow a significant reduction in the

number of transistors required to realize any complex Boolean
function. The implementation of the 8-input Boolean function, Z =
AB + (C + D)(C + D) + GH, using standard CMOS and domino
CMOS,