Sie sind auf Seite 1von 8

1 A flip-flop is said to be falling (or negative) edge triggered when

the flip-flop output changes only after the falling (or negative) edge of the
clock.
the change is based on the flip-flop inputs values that were present
right at the falling (or negative) edge of the clock signal.
Based on this information, answer the following questions.
(a) Fill in the timing diagram for a falling-edge-triggered S-R flip-flop.
Assume Q begins at 0.

(b) Fill in the timing diagram for a falling-edge-triggered J-K flip-flop.


Assume Q begins at 0.
(c) Repeat part b with the assumption that Q=1, but clock, J and K
are the same
Solution:

(d) Find the input for a rising-edge-triggered D flip-flop that would produce the output Q as
shown. Fill in the timing diagram
(e) Repeat part d for a rising edge triggered T flip flop
Solution

2 Draw a timing diagram for the circuit showing the clock X, Q1, Q2, Q3 and Z. Use the
input sequence X = 01100 and assume that X changes midway between falling and rising
clock edges. Also, assume that the initial state of the circuit is Q1Q2Q3 = 000.
Solution:

3 A sequential circuit has three D flip flops A,B and C and one input X. The circuit is
described by the following input equations:
DA = (BC + BC)X + (BC + BC)X
DB = A
DC = B
(a) Derive the state table for the circuit
Solution:

4 Construct a JK flip-flop using a D Flip-flop, a 2-to-1 line multiplexer and an inverter

5 A PN flip-flop has four operations: clear to 0, no change, complement, and set to 1, when
inputs P and N are 00, 01, 10, and 11, respectively.
a) Tabulate the characteristic table.
b) Derive the characteristic equation.
c) Tabulate the excitation table.
d) Show how the PN flip-flop can be converted to a D flip-flop.
a)

P
0
0
1
1

N Q(t+1)
0
0
1 Q(t)
0 Q(t)
1
1

b)

Q(t+1) = PQ + NQ

c)

Q(t) Q(t+1)
0 0
0 1
1 0
1 1

P
0
1
X
X

N
X
X
0
1

d) by connecting P and N together: Q(t+1)= DQ+DQ=D


6 A sequential circuit with two D Flip-Flops, A and B; two inputs, x and y; and one output,
z, is specified by the following next-state and output equations:
A(t+1) = xy + xA
B(t+1) = xB + xA
z=B
a) Draw the logic diagram of the circuit.

b) List the state table for the sequential circuit.


c) Draw the corresponding state diagram.

Present State Inputs Next State Output


AB
xy
AB
z
00
00
00
0
00
01
10
0
00
10
00
0
00
11
00
0
01
00
01
1
01
01
11
1
01
10
00
1
01
11
00
1
10
00
00
0
10
01
10
0
10
10
11
0
10
11
11
0
11
00
01
1
11
01
11
1
11
10
11
1
11
11
11
1

7 A combinational circuit is defined by the following three Boolean functions:


F1(x,y,z)=xyz+xz F2(x,y,z)=xyz+xy F3(x,y,z)=xyz+xy
a. Design the combinational circuit that implements the functions.
b. Design the combinational circuit that implements the functions with a
decoder and external gates.
8

8 Draw a circuit for F using only one 4-to-1 multiplexer and one NOT gates
9 the following truth table defines function F.
w

Derive a minimal sum-of-products expression for F using a Karnaugh map (show


your Karnaugh map and show the algebraic expression).
(b) Draw a logic gate diagram for this minimal sum-of-products expression.

(c) If you could change any one function value (one of the 16 in the table above) to
a "don't care", which change would minimize the minimal sum-of-products
expression the farthest?
(d) Draw the Karnaugh map corresponding to the change suggested in your answer
to part c.

10 Design a combinational circuit with three inputs and one output. The output
is 1
when the binary value of the inputs is less than 3. The output is 0 otherwise.

draw circuit diagram for this

Das könnte Ihnen auch gefallen