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System Verilog Interview Questions and answers

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System Verilog Interview Questions and


answers

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System Verilog Interview Questions and answers

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ming explicit. The clocking block is a key element in a cycle-based methodology, which enables
users to write testbenches at a higher level of abstrac on. Rather than focusing on signals and
transi ons in me, the test can be dened in terms of cycles and transac ons. The clocking block
separates the ming and synchroniza on details from the structural, func onal, and procedural
elements of a testbench.
Q. What is the dierence between mailbox and queue?
A mailbox is a communica on mechanism that allows messages to be exchanged between
processes. Data can be sent to a mailbox by one process and retrieved by another.
A queue is a variable-size, ordered collec on of homogeneous elements. A queue supports
constant me access to all its elements as well as constant me inser on and removal at the
beginning or the end of the queue.
Mailbox are FIFO queue, which allows only atomic opera ons. They can be bounded/unbounded.
A bounded mailbox can suspend the thread (while wri ng if full, while reading if empty) via
get/put task. Thats why mailbox is well suited for communica on between threads.
Q. What are the ways to avoid race condi on between testbench and RTL using SystemVerilog?
Program block
Clocking block
Enforcement of design signals being driven in non-blocking fashion from program block
Q. What data structure you used to build scoreboard?
mailboxes
Q. Explain Event regions in SV?

Q. What are the advantages of linkedlist over the queue?


Queue has a certain order. It's hard to insert the data within the queue. But

Linkedlist can easily insert the data in any loca on.

Q.How to check weather a handles is holding object or not?


It is basically checking if the object is initialized or not. In SystemVerilog all uninitialized object handles
have a special value of null, and therefore whether it is holding an object or not can be found out by
comparing the object handle to null. So the code will look like
if(My_usb_packet == null) begin.// This loop will get exited if the handle is not holding any object
end else begin// Hurray ... the handle is holding an object
end

Q. What is the use of packages?


In Verilog declara on of data/task/func on within modules are specic to the module only. They
can't be shared between two modules. Agreed, we can achieve the same via cross module
referencing or by including the les, both of which are known to be not a great solu on.
The package construct of SystemVerilog aims in solving the above issue. It allows having global
data/task/func on declara on which can be used across modules. It can contain module/class
/func on/task/constraints/covergroup and many more declara ons (for complete list please refer
sec on 18.2 of SV LRM 3.1a)
The content inside the package can be accessed using either scope resolu on operator (::), or
using import (with op on of referencing par cular or all content of the package).
Q. What are bi-direc onal constraints?
Constraints by-default in SystemVerilog are bi-direc onal. That implies that the constraint solver
doesn't follow the sequence in which the constraints are specied. All the variables are looked
simultaneously. Even the procedural looking constrains like if ... else ... and -> constrains, both if
and else part are tried to solve concurrently. For example (a==0) -> (b==1) shall be solved as all the
possible solu on of (!(a==0) || (b==1)).
Q. What is solvebefore constraint?
in the case where the user want to specify the order in which the constraints solver shall solve the
constraints, the user can specify the order via solve before construct.
Q. Without using randomize method or rand,generate an array of unique values?

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int UniqVal[10];
foreach(UniqVal[i]) UniqVal[i] = i;
UniqVal.shue();
Q. Explain about pass by ref and pass by value?
Pass by value is the default method through which arguments are passed into functions and tasks.
Each subroutine retains a local copy of the argument. If the arguments are changed within the
subroutine declaration, the changes do not affect the caller. In pass by reference functions and tasks
directly access the specified variables passed as arguments.Its like passing pointer of the variable.

Q. What is the dierence between bit[7:0] sig_1; byte sig_2;


byte is signed whereas bit [7:0] is unsigned.
Q. What is the dierence between program block and module
Program block is newly added in SystemVerilog. It serves these purposes
It separates testbench from DUT
It helps in ensuring that testbench doesn't have any race condi on with DUT
It provides an entry point for execu on of testbench
It provides syntac c context (via program ... endprogram) that species scheduling in the
Reac ve Region.
Having said this the major dierence between module and program blocks are
Program blocks can't have always block inside them, modules can have.
Program blocks can't contain UDP, modules, or other instance of program block inside
them. Modules don't have any such restric ons.
Inside a program block, program variable can only be assigned using blocking assignment
and non-program variables can only be assigned using non-blocking assignments. No such
restric ons on module

Program blocks get executed in the re-ac ve region of scheduling queue, module blocks
get executed in the ac ve region
A program can call a task or func on in modules or other programs. But a module can not
call a task or func on in a program.

Q. How to implement always block logic in class ?


class Base;
integer a,b;
task always_task();
fork
forever
begin
@(a,b);
$display(" a is %d : b is %d at %t ",a,b,$ me);
end
join_none
endtask
endclass
& In program block
forever begin
fork
begin : reset_logic
@ (negedge reset_);
data <= '0;
end : reset_logic
begin : clk_logic
@ (posedge clk);
if(!reset_) data <= '0;
else
data <= data_next;
end : clk_logic

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System Verilog Interview Questions and answers

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join_any
disable fork
end
Q. Write a clock generator without using always block.
Use forever within an ini al block.
Q. What is cross coverage?
Cross allows keeping track of information which is received simultaneous on
more than one cover point. Cross coverage is specified using the cross

construct.

Q. Describe the dierence between Code Coverage and Func onal Coverage Which is more
important and Why we need them?
Code Coverage indicates the how much of RTL has been exercised. The Func onal Coverage
indicates which features or func ons has been executed. Both of them are very important. With
only Code Coverage, it may not present the real features coverage. On the other hand, the
func onal coverage may miss some unused RTL coverage.
Q. How to kill a process in fork/join?
The kill() task terminates the given process and all its sub-processes, that is, processes spawned
using fork statements by the process being killed. If the process to be terminated is not blocked
wai ng on some other condi on, such as an event, wait expression, or a delay then the process
shall be terminated at some unspecied me in the current me step.
Q. Dierence between Associa ve array and Dynamic array?
Dynamic arrays are useful for dealing with contiguous collections of variables whose number changes
dynamically. e.g. int array[];
When the size of the collection is unknown or the data space is sparse, an associative array is a
better option. In associative array, it uses the transaction names as the keys in associative array.

e.g. int array[string];


Q.What is coverage driven verification?
Coverage Driven Verification is a result oriented approach to functional verification. The manager and
verification terms define functional coverage points, and then work on the detail of process. Used
effectively coverage driven verification focuses the Verification team on measurable progress toward
an agreed and comprehensive goal.
Q. how to randomize dynamic arrays of objects?
class ABC;
// Dynamic array
rand bit [7:0] data [];
// Constraints
constraint cc {
// Constraining size
data.size inside {[1:10]};
// Constraining individual entry
data[0] > 5;
// All elements
foreach(data[i])
if(i > 0)
data[i] > data[i-1];
}
endclass : ABC
Q. What is scope randomization?

Scope randomiza on ins SystemVerilog allows assignment of unconstrained or constrained


random value to the variable within current scope by passing the variable as an argument to the
randomize func on.
Q. What is polymorphism?
Polymorphism allows an en ty to take a variety of representa ons. Polymorphism
means the ability to request that the same Opera ons be performed by a wide range of dierent

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