EET Project

Signature Analyzer

Coordinator Teacher:
Andrei Ternauciuc

Students:
Radu Drago
Retezan Adrian
ran Adrian

List of contents
1. Brief History ................................................................................................... 3
2. Task ................................................................................................................. 4
3. Functional principle ........................................................................................ 4
4. Logic diagram ................................................................................................. 4
5. Signature generation ....................................................................................... 7
6. Electronic diagram implementation ................................................................ 8
7. Conclusions ..................................................................................................... 8
8. Bibliography.................................................................................................... 9

1. Brief History
First signature analyzers serial type were introduced by Hewlett-Packard
company in 1977.

William R. Hewlett and David Packard were classmates in an engineering

course at Stanford University. The two decide to start their own business
together. They decide that the company name to be represented by their
names initials, but they could not agree which one to be the first one. So
they played heads or tails. After a few months, the HP company was born.
Their company, which started in a small rented garage in Palto Alto, came
today to have a turnover of tens of billions of dollars.

2. Task
Creating a serial type signature analyzer, using the next polynom
for implementation:
G( x) x16 x12 x 9 x 7 1 using CMOS technology.

3. Functional Principle
Signature analyzer testing principle is based on information flow length
compression inside a node or bus equipment. The compression result is called
signature, and the tool that implements this method is called signature analyzer.
Depending on the number of nodes that can collect and analyze information
flow, signature analyzers can be either serial or parallel.

4. Logic diagram

The testing unit (TU) may consist of a fitted plate, but it also can be a complex
equipment. We collect the information flow from the important lines in order for
the testing unit to function.
Collection of this flow, which is the signature analyzers input data, is done via
data block probes (DBP). This block must identify the logic level of taken data,
without overcharging the buses from which it collects the data and without
affecting in any way the received stream. Depending on the embodiment of
DBP, a signature analyzer can be used for testing equipment with components
made in a specific technology (TTL, CMOS, etc.)
Collection of information flow from the buses of the tested unit is made under
the control signals "Start", "Stop" and "Clock". They are all taken from the TU
via the block control probes (BCP), which may have basically the same
hardware structure as that of the DBP. Frequently, the "Start" signal of signature
analyzer signifies that the TU processor is in a Wait state, what allows to start a
self-test program. "Stop" signal may mean leaving the Wait state and the "Tact"
signal is related to working frequency of TU. Therefore, it should be noted that
the mentioned signals doesnt usually have the same meaning for the signature
analyzer and tested unit.
For fine control of the duration of data collection, we are given the possibility to
select the active fronts for the three control signals: "Start", "Stop" and "Clock"
through selective blocking fronts (SBF). This block generates a signal called
window (ERF), which allows access to data from TU while active.
After a possible temporary storage buffer, the collected information from the TU
buses is transmitted through the window control block to the central part of
information processing within the analyzer.

Tact

t
Start

t
Stop

t
FER

t
Data

Date culese pentru noua semnatura

It can be seen from the figure the method for generating the window in
accordance with the choice of front active control signals. It should be noted that
the length of the window depends on the chosen active fronts.
For MT, information taken is loaded (serial or parallel, depending on the
analyzer type) in pseudorandom sequence generator (PRSG), which constitutes
the main element of the algorithm for compressing information flow and
signature generation. To understand the principle of operation of the signature
analyzer is enough to note that, after processing PRSG, we get a constant length
information, called signature, which is stored in memory current signature
register (MCSR). Usually, this information is generated on 16-bit, which
decodes into groups of 4 bits and is displayed as four alphanumeric characters,
through the block decoding and display (BDD). The displayed signature allows
immediate decision regarding the accuracy of TUs functionality.
The generated signature will be stable as long as the window and the
information collected from the TU buses will be repeatable. In principle, this is
true, because the collected data is the result of a running self-test program
specifically designed for the TU. However, due to an inappropriate choice of
one or more of the control signals, it is possible to get in a position to generate
different signatures from a test cycle to another, to generate an unstable
signature. To grasp this and take appropriate measures, signature analyzer is
equipped with unstable signature detection facility. To this end, before starting a
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new test cycle, the current signature is transferred to another register called the
register of memorizing previous signature (rmps).
After a further test cycle, the current signature is compared with the previous
one by means of an unstable signature detection unit (USDU). If a difference
appears, unstable signature block display (USBD) will display a warning that the
operation is not stable.
5. Signature generation
Signature analyzer functionality is based on the use of pseudorandom
sequences. Such sequences are generated by shift registers accomplished by
exclusive-OR circuits.
A signature generator is implemented on the basis of irreducible polynomials
generating cyclic codes with debris. The generator starts from the polynom:
G( x) x16 x12 x 9 x 7 1

The following figure shows the generation and comparison of a 16-bit

signatures structure. It was considered that the correct signature was obtained
and stored, and the given decision is the kind of CORRECT / DEFECT.

Test
16

15

14

13

12

11

10

6. Electronic diagram implementation

The general electronic diagram implemented in Circuit Maker.

7. Conclusions
Signature analyzers are designed to facilitate the testing process in
production and service. We can quickly check the functionality of the circuit
or equipment by simply comparing the signatures collected from point test
with the correct signature, written in the service manual.
Advantages:
- small costs;
- real-time processing;
8

- simple programming;
- automatic detection of certain types of faults (short circuits, interruptions);
- good adaptation to mass production;
Disadvantages:
- big costs in poorly made circuits cases;
- high workload;
- difficulties in obtaining the correct signature;
8. Bibligraphy
Vasiu R., Testarea echipamentelor electronice, Ed. Orizonturi Universitare,
Timisoara, 2001
http://www.siliconvalleyhistorical.org/#!hewlett-packard-companyhistory/c38e
http://www.radio-electronics.com/info/t_and_m/signature-analyzeranalyser/basics-tutorial.php