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VLSI II
PRACTICAL LABORATORY SESSION No. 1
First Name
Family
Name
Date
Evaluation
Document
Visa
Evaluation
Design
Visa
1. OBJECTIVES
During this first practical exercise session, you will get familiar with the working environment
and software that you will use throughout the next few weeks. You will first learn how to
properly configure and run the Design Framework, after what you will start doing schematic
entry while learning the basics of using the software.
Note that this document contains important information that will help save you lots of trouble
during the remaining exercise sessions, so it is your best interest to read it from start to finish,
even though the manipulations may seem very simple.
The Command Interpreter Window (CIW) is the main window that gives access to the
different tools through menu commands, or through direct entering of commands in the
scripting language named SKILL. It is also the windows where information and error
messages are reported.
The Library Manager is the tool to manage your design data such as circuit schematics,
layouts, simulation testbenches etc...
Virtuoso is the platform for creating and simulating your designs. It consists of the
Schematic Editor, the Layout Editor, and the Analog Design Environment (ADE)
which is the graphical front-end to the circuit simulator.
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Assura is the suite for full-custom layout verification and parasitics extraction. It allows
to check your layout against your schematic using the LVS (Layout vs Schematic) tool,
to verify that your layout is compliant with the foundrys design rules using the DRC
(Design Rules Check) tool, and to extract from your layout a detailed schematic
containing parasistics for accurate post-layout simulation with the RCX (Parasitics
Extraction) tool.
It is extremely important to always start the tools from your project directory. Because
your project directory will contain many configuration files, the tools will not work as
expected when run from a different place. Even worse, it may override other configuration
files, especially when run from your home directory this is a common mistake.
Since this is our first time running the design framework, we need to specify the technology
to be used (-tech option). We chose the c35b4 technology, which stands for
0.35m CMOS with 4 metal layers. The software can run in different modes (-mode
option), but we will allways chose the front-to-back (fb) mode for our needs. The trailing &
runs the command in the background, so that the terminal does not freeze.
At this point, the software should start and the CIW window should appear, followed by the
Library Manager.
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9 A window will pop up prompting you to select a process option to use. Select the C35B4M6
option.
9 A text window displaying information about the design kit will also pop up. You dont need to
read its content. Select FileOff At Startup from the window menu to keep this window from
showing up every time at startup.
typing exit in the command prompt at the bottom of the CIW window.
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By default, a number of libraries will be available to you: some are the tools default, and some
are provided by the foundry design kit. Following is a list with a brief description of the most
important ones:
analogLib contains many elements useful for simulation such as voltage and
current sources, ideal resistors, capacitors and inductors, switches etc These
cells are mostly used to create simulation testbenches.
CORELIB contains standard logic cells from the foundry design kit.
In the next steps, we will create a new library for your designs, and experiment some features of
the library manager.
9 Make sure you are in your project directory, and start the software.
edatp0> cd ~/vlsi2007_analog
vlsi2007_analog> ams_cds m fb &
Now that the tool has been configured, specifying the technology(-tech) is not necessary
anymore. We still must specify the mode (-mode, abbreviated as m).
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Creating cellviews
9 Now create a cellview in your new library. Select VLSITP in
the Library field, and then choose FileNewCellView
from the menu. Enter test as the cell name, and schematic as
the view name.
Notice the Tool field. When changing the tool, the view
name changes. This is because different tools are
associated with different views : schematic editor,
symbol editor, layout editor (Virtuoso), etc Each
view type has a standard name (i.e. schematic for a
circuit schematic) but they can be changed.. It is however advised to keep the default
names to avoid problems.
9 A cell named test is created, with one view named schematic, and the schematic editor appears
to edit your new cellview.
9 Choose DesignCheck And Save from the schematic editor menu, to have the cellview data
written to the disk. Then close the schematic editor.
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In the next steps, we will create a simple schematic shown on the figure below, while learning to
use the graphics editor.
Creating instances
The term instance denotes the occurrence of a cell inside of another. A cell can be instanciated
multiple times in another. Instances define a hierarchical relationship between cells, where the
containing cell is higher in the hierarchy than the instanciated cell.
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9 Choose AddInstance from the menu, or use the keyboard shortcut for this command by
simply pressing i on the keyboard.
Most commands have a keyboard shortcut, or bindkey. They are shown on the right of the command
name on the menus. Learn to use these bindkeys to save you a lot of time.
9 An option form appears, which prompts you for the library / cell / view name of the cellview
you wish to instantiate. Type PRIMELIB / nmos4 / symbol, or, alternatively, click on the
Browse button and select this cell in the library manager.
9 Use the nmos4 and pmos4 cells from the PRIMLIB library for N- and P- MOS
transistors.
9 Set appropriate size of transistors. Select the object (being one of the transistors in your
design) with the left mouse button. Use either the EditPropertiesObjects pull-down
menu or press q.
9 A pop-up window will appear as show in the previous Figure. Set the gate width and
length as provided in Figure 5.
9 Repeat this process until you have modified all the transistors in the design
9 When you are done, Check and Save your schematic. Correct any errors or warnings,
Notice how you can add more instance as long as you do not cancel the command. Many commands
work in this way: activating the commands bring you into a new mode that lasts until you press
Escape. Some dont, and work only once.
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Creating pins
Pins define the connections between a cell and its environment. Pins have a name and a
direction (input, output or inputOutput). The direction is used to check for wrong connections
(i.e. two outputs shorted together, or floating inputs). inputOutput pins are typically used for
power supplies.
9 Choose AddPin from the menu. The option form appears, prompting you to enter the name of
the pin as well as different options (see figure below). Enter vin as the pin name, and place the
pin on the schematic. Once this is done, return to the option form and enter the name vo for the
second pin. Change the pin direction to output and place the pin on your schematic. Then press
Escape or click Cancel on the form. Repeat this work for the rest of pins.
Choose AddWire Name from then menu. In the option form, type ABC as the wire name and
place it anywhere on the wire which connects the three inverters together.
If your label is not placed on a wire, you will be prompted to click on a wire to which the label
should be attached..
then drag the inverter to a new location and left click again to execute the move.
Multiple objects can be selected at the same time. Left-click and drag the mouse to select multiple
objects. Hold the Shift key whick clicking to add objects to the selection, and the Ctrl key to remove
objects from the selection.
9 Choose EditUndo or press u to cancel the move. Then press Ctrl+d to clear the selection.
Then press Shift+m to start a new move. Click on an inverter, then drag it to a new location and
release it. Press u to undo the move, and click on another inverter then move it. Undo the move
again and press Escape.
Commands that work on objects, such as move, stretch or delete,need a selection to work on. If an
object or a set of object is selected before applying the command, it will operate on this existing
selection. If not, you are prompted to select objects first.
Notice two differences : when there is an exisiting selection, you need to select a reference point.
Also, when there is an existing selection, you can move the object only once before the command
exits, while you can move multiple objects when there is no prior selection. Thus, in one case you can
apply multiple actions, sqeuentially, to a set of selected objects, and in the other case you can apply
the same action to a number of sequentially selected objects. Remember Ctrl+d to clear the selection.
9 Repeat the same manipulations with the Stretch command instead (EditStretch or m).
Observe that with the stretch command, wires connected to the instance are rerouted to keep the
connections, while with the move command, the selected objects were moved regardless of the
connections.Stretch also allows to reshape existing wires.
9 When moving or stretching an object, try pressing the F3 key before releasing the object to its
new location. In the option form showing up, there are buttons for rotating and mirroring the
instance. Try these.
Many commands have an option form which does not allways show up automatically. Use the F3 key
to show or hide this option form.
Deleting objects
The Delete command (EditDelete or Del) works in the same way as Move or Stretch with respect to the
selection. Objects can be accidentally deleted if they are selected prior to pressing Del.
Symbols can be created manually by choosing the Composer-Symbol tool when creating a new
cellview, then drawing the shapes and pins. However, it is also possible and much more
convenient to have them generated automatically. A square box with pins is generated, that can
then be modified if wanted it provides a good starting point.
9 From the Schematic Editor menu, choose DesignCreate Cellview->From Cellview.
9 In the first form coming up, all options should be set correctly. Press Ok.
9 In the second form, you get a chance to specify the location of the pins on your symbols. It is
common to have input pins on the left, output pins on the right, and power/ground pins on the
top and bottom of the symbol. When you are done, press Ok.
9 Do any changes you like to your symbol, then Check and Save it.
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9 When you are done, Check and Save your schematic. Correct any errors or warnings, until no
more are reported.
9 Create a symbol for the DiffPari2.
9 Create another new schematic in your VLSITP library. Name it ADC2.
Checkpoint Please call an assistant and show him/her that you have reached
Visa
this point before working on further steps
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9 For the DC source use vdc component from analogLib library, and set the DC voltage
property to 3.3V.
9 For the load capacitors shown in the schematic, use the cap element from analogLib,
and edit the capacitance property to enter the provided value in the schematic (50 fF).
9 For the ground symbol, use gnd cell symbol view from analogLib library. gnd symbol
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will provide the zero reference voltage level for your simulation.
9 Use AddWire Name or pres l to place labels accordingly on to input/output signals
as shown in Figure 86.
9 Check and Save your design.
Parameter
Value
DC voltage: V2
vdc V
DC Voltage: V0
3.3 V
DC Voltage: V1
0.0 V
DC Current: I0
100u A
Table. 1.
Checkpoint Please call an assistant and show him/her that you have reached
Visa
this point before working on further steps
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DC ANALYSIS
Setup a DC analysis in order to simulate the voltage transfer curve (VTC) of the NAND2 gate.
This analysis allows you to verify the DC characteristics of the design, like switching threshold,
noise margins, logic levels, etc.
9 Use AnalysisChoose in order to select the type of the simulation you would like to
run.
9 In the pop-up window, edit the necessary properties as shown in Figure 10.
9 Use SessionSave State to save your simulation setup so you can reload it at a future
time
9 To run simulation use SimulationNetlist and Run command from the Analog Design
Environment window.
This command will generate the netlist of your design automatically and run the specified simulation
setup on this netlist. The progress of the simulation is displayed on the screen as a text window. As
soon as the simulation is completed, a Waveform Window appears with all the selected signals
displayed in a single graph.
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5. CREATING LAYOUT
THE LAYOUT EDITOR
As mentioned in the laboratory session no.1 there are different tools used for graphical editing.
The tool used as a layout editor is called Virtuoso Layout Editor. To start a tool you create a
new cellview in your library. The goal of this session will be to draw a layout for DiffPair gate
and check it for Design Rules.
9 Now create a cellview in your new library. Select VLSITP library and DiffPair cell and
choose FileNewCellView.
9 Select layout as the view name.
Notice the Tool field. There it should be written Viruoso for a layout editor.
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All available layers and their related design rules are provided in the AMS 0.35um technology
Design Rule Manual (DRM) confidential yellow notebook. Minimum spacing between
various layers and minimum width specification of all layers are the most critical rules to be
respected.
For each layer that you can observe in LSW - Layer Selection Window (Figure 13)
there is a separate page in DRM containing a certain number of rules. Most important
layers are NTUB, DIFF, POLY1, PPLUS, NPLUS, CONT and MET1 (see Figure
12).
Each rule in DRM consists of a Rule code, Description and Value. For example
look at the page 21 at the rule with the code CO.S.1. Description is: Minimum CONT
spacing and Value is 0.3um.
In the following online Layout tutorial for any of the drawing steps a page and a Rule
code will be given.
Wafer Cross-Section
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step involved design rules are listed with their names and pages in DRM.
Short list of the most important keyboard shortcuts is given in the following table.
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Checkpoint Please call an assistant and show him/her that you have reached
Visa
this point before working on further steps
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9 Once you have a DRC clean layout, run the LVS tool (Assura -> LVS). LVS tool is to
compare the netlist of your main schematic to the netlist which is extracted from layout.
You should find the reason for each mismatch report and try to solve it on your layout.
9 Once your LVS is clean, create an extracted view (Assura -> RCX) of the layout. In this
way the netlist extracted from your layout will be created. Now, you can re-run your
simulation with the new netlist includes parasitic effects raised in layout.
9 Then run a post layout simulation using the same simulation environment that you used
for the pre layout simulation. For this purpose you just need to change the set-up of your
ADE. In ADE just add av_extracted in Setup -> Environment menu as the first item
on the switch view list:
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Checkpoint Please call an assistant and show him/her that you have reached
Visa
this point before working on further steps
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