Verilog Programs

SATHYABAMA UNIVERSITY
DEPARTMENT OF VLSI DESIGN
EXPT NO: 01
DATE:23-1-08
LOGIC GATES
AIM: To develop the source code for logic gates using VHDL and VERILOG and to obtain the simulation,
synthesis, place and route and implementation into FPGA.
ALGORITHM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the OUTPUT: by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.
LOGIC DIAGRAM:
AND GATE:
LOGIC DIAGRAM:
TRUTH TABLE:
A
Y=AB
0
0
1
1
0
1
0
1
0
0
0
1
NOT GATE:
NAND GATE:
LOGIC DIAGRAM:
TRUTH TABLE
TRUTH TABLE:
A
Y=A
0
0
0
1
NOR GATE:
LOGIC DIAGRAM:
XNOR GATE:
LOGIC DIAGRAM:
TRUTH TABLE:
OR GATE:
LOGICDIAGRAM
TRUTH TABLE:
Y=A+B
0
0
1
1
0
1
0
1
0
1
1
1
LOGICDIAGRAM
XOR GATE:
LOGICDIAGRAM
Y=(AB)
0
0
1
1
0
1
0
1
1
1
1
0
TRUTH TABLE
Y=(A+B)
0
0
1
1
0
1
0
1
1
0
0
0
0
0
1
1
0
1
0
1
TRUTH
VLSI DESIGN LABORATORY
0
0
1
1
0
1
0
1
0
1
1
0
TABLE:
1
0
0
1
PAGE NO.
VHDL CODE:
--Design
: LOGIC GATES
--Description : To implement LOGIC GATES
--Author
: CH UDAY KUMAR REDDY
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logicgates is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic_vector(6 downto 0));
end logicgates;
architecture Behavioral of logicgates is
begin
c(0)<= a and b;
c(1)<= a or b;
c(2)<= a nand b;
c(3)<= a nor b;
c(4)<= a xor b;
c(5)<= a xnor b;
c(6)<= not a;
end Behavioral;
VERILOG CODE:
module LOGICGATESverilog(a, b, c);
input a;
input b;
OUTPUT: [6:0] c;
assign c[0]= a & b;
assign c[1]= a | b;
assign c[2]= ~(a & b);
assign c[3]= ~(a | b);
assign c[4]= a ^ b;
assign c[5]= ~(a ^ b);
assign c[6]= ~ a;
endmodule
TEST BENCH:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY logicgatetb_vhd IS
END logicgatetb_vhd;
ARCHITECTURE behavior OF logicgatetb_vhd IS
PAGE NO.
COMPONENT logicgates
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL c : std_logic_vector(6 downto 0);
BEGIN
uut: logicgates PORT MAP(
a => a,
b => b,
c => c
);
tb : PROCESS
BEGIN
a<='0'; b<='0';
wait for 100 ps;
a<='0'; b<='1';
wait for 100 ps;
a<='1'; b<='0';
wait for 100 ps;
a<='1'; b<='1';
wait for 100 ps;
END PROCESS;
END;
OUTPUT: GRAPH:
SYNTHESIS RTL SCHEMATIC:
PAGE NO.
SYSNTHESIS REPORT:
Device utilization summary:
--------------------------Selected Device : 3s400tq144-5
Number of Slices:
Number of 4 input LUTs:
Number of bonded IOBs:
3 out of 3584 0%
6 out of 7168 0%
9 out of 97 9%
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Timing Summary:
--------------Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum OUTPUT: required time after clock: No path found
Maximum combinational path delay: 7.985ns
Timing Detail:
-------------All values displayed in nanoseconds (ns)
PAGE NO.
Timing constraint: Default path analysis

Total number of paths / destination ports: 13 / 7
------------------------------------------------------------------------Delay:
7.985ns (Levels of Logic = 3)
Source:
a (PAD)
Destination:
c<5> (PAD)
Place and root report:
Constraints file: logicgates.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
"logicgates" is an NCD, version 3.1, device xc3s400, package tq144, speed -5
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "ADVANCED 1.35 2005-01-22".
Device Utilization Summary:
Number of External IOBs
Number of LOCed IOBs
Number of Slices
Number of SLICEMs
9 out of 97
0 out of 9
9%
0%
3 out of 3584 1%
0 out of 1792 0%
Overall effort level (-ol): Standard (set by user)

Placer effort level (-pl): Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): Standard (set by user)
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:989697) REAL time: 3 secs
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs
Phase 3.2
Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs
Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 3 secs
Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 3 secs
Phase 6.8.
Phase 6.8 (Checksum:98a1bf) REAL time: 3 secs
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 sec
Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 3 secs
Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 3 secs
Writing design to file logicgates.ncd
Total REAL time to Placer completion: 3 secs
Total CPU time to Placer completion: 1 secs
PAGE NO.
Starting Router
Phase 1: 19 unrouted;
REAL time: 3 secs

REAL time: 3 secs
REAL time: 3 secs
REAL time: 3 secs
Total REAL time to Router completion: 3 secs

Total CPU time to Router completion: 1 secs
Generating "PAR" statistics.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 4 secs
Total CPU time to PAR completion: 2 secs
Peak Memory Usage: 74 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file logicgates.ncd
PAR done!
RESULT:
The OUTPUT:s of LOGIC GATES (and, or, not, nand, nor, xor, xnor) are verified by
synthesizing and simulating the VHDL and VERILOG source code.
EXPT NO: 02
DATE:28-1-08
PAGE NO.
ADDERS AND SUBTRACTORS

AIM: To develop the source code for adders and subtractors using VHDL and VERILOG and to obtain the
simulation, synthesis, place and route and implementation into FPGA.
ALGORITHM:
LOGIC DIAGRAM:
HALF ADDER:
LOGIC DIAGRAM:
TRUTH TABLE:
SUM
CARRY
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
FULL ADDER:
LOGIC DIAGRAM:
TRUTH TABLE:
A
SUM
CARRY
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
HALF SUBTRACTOR:
PAGE NO.
LOGIC DIAGRAM:
TRUTH TABLE
A
DIFFERENCE
BORROW
0
0
1
1
0
1
0
1
0
1
1
0
0
1
0
0
FULL SUBTRACTOR:
LOGIC DIAGRAM:
TRUTH TABLE:
A
DIFFERENCE
BORROW
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
0
0
1
FULL ADDER USING TWO HALF ADDERS:

LOGIC DIAGRAM:
TRUTH TABLE:
A
SUM
CARRY
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
FULL SUBTRACTOR USING TWO HALF SUBTRACTORS:

LOGIC DIAGRAM:
TRUTH TABLE:
PAGE NO.
HALF ADDER
VHDL CODE:
--Design
--Description
--Author
--Roll no
--Version
DIFFERENCE
BORROW
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
0
0
1
: HALF ADDER
: To implement HALF ADDER
: 28SVL132
: Xilinx- 7.1i
library IEEE;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity halfadder is
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end halfadder;
architecture Behavioral of halfadder is
begin
sum<= a xor b;
carry<= a and b;
end Behavioral;
VERILOG CODE:
module halfadder(a, b, sum, carry);
input a;
input b;
OUTPUT: sum;
OUTPUT: carry;
assign sum = a ^ b;
assign carry = a & b;
endmodule
TEST BENCH:
PAGE NO.
LIBRARY ieee;
ENTITY halfaddertb_vhd IS
END halfaddertb_vhd;
ARCHITECTURE behavior OF halfaddertb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT halfadder
PORT(
a : IN std_logic;
b : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;
--Inputs
--OUTPUT:s
SIGNAL sum : std_logic;
SIGNAL carry : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: halfadder PORT MAP(
a => a,
b => b,
sum => sum,
carry => carry
);
tb : PROCESS
BEGIN
a<='0'; b<='0';
a<='0'; b<='1';
a<='1'; b<='0';
a<='1'; b<='1';
END PROCESS;
wait for 100 ps;

wait for 100 ps;
wait for 100 ps;
wait for 100 ps;
END;
OUTPUT: GRAPH:
PAGE NO.
10
SYNTHESIS REPORT:
Number of Slices:
1 out of 3584 0%
2 out of 7168 0%
4 out of 97 4%
TIMING REPORT
Clock Information:
Timing Summary:
--------------Speed Grade: -5
PAGE NO.
11

Timing Detail:
------------------------------------------------------------------------Delay:
Source:
a (PAD)
Destination:
carry (PAD)
FULL ADDER
VHDL CODE:
--Design
--Description
--Author
--Roll no
--Version
: FULL ADDER
: To implement FULL ADDER
: 28SVL132
: Xilinx- 7.1i
library IEEE;
--library UNISIM;
entity fulladder is
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fulladder;
architecture Behavioral of fulladder is
signal w,x,y,z:std_logic;
begin
w<= a xor b;
sum<= w xor c;
x<= a and b;
y<= b and c;
z<= c and a;
carry <= x or y or z;
end Behavioral;
VERILOG CODE:
module fulladder(a, b, cin, sum, carry);
PAGE NO.
12
input a;
input b;
input cin;
OUTPUT: sum;
OUTPUT: carry;
assign sum = a ^ b ^ cin;
assign carry = ( a & b) | ( b & cin) | ( cin & a);
endmodule
TEST BENCH:
LIBRARY ieee;
ENTITY fulladdertb_vhd IS
END fulladdertb_vhd;
ARCHITECTURE behavior OF fulladdertb_vhd IS
COMPONENT fulladder
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
);
END COMPONENT;
--Inputs
SIGNAL c : std_logic := '0';
--OUTPUT:s
BEGIN
uut: fulladder PORT MAP(
a => a,
b => b,
c => c,
sum => sum,
carry => carry
);
tb : PROCESS
BEGIN
PAGE NO.
13
a<='0'; b<='0'; c<='0';

wait for 100 ps;
a<='0'; b<='0'; c<='1'; wait for 100 ps;
a<='0'; b<='1'; c<='0';
wait for 100 ps;
a<='0'; b<='1'; c<='1';
wait for 100 ps;
a<='1'; b<='0'; c<='0';
wait for 100 ps;
a<='1'; b<='0'; c<='1';
wait for 100 ps;
a<='1'; b<='1'; c<='0';
wait for 100 ps;
a<='1'; b<='1'; c<='1';
wait for 100 ps;
END PROCESS;
END;
OUTPUT: GRAPH:
SYSNTHESIS REPORT:
PAGE NO.
14

Number of Slices:
TIMING REPORT
1 out of 3584 0%
2 out of 7168 0%
5 out of 97 5%

Clock Information:
Timing Summary:
--------------Speed Grade: -5
Timing Detail:
------------------------------------------------------------------------Delay:
Source:
a (PAD)
Destination:
carry (PAD)
Data Path: a to carry
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
2 0.715 1.040 a_IBUF (a_IBUF)
LUT3:I0->O
1 0.479 0.681 Mxor_sum_Xo<1>1 (sum_OBUF)
OBUF:I->O
4.909
sum_OBUF (sum)
---------------------------------------Total
7.824ns (6.103ns logic, 1.721ns route)
(78.0% logic, 22.0% route)
HALF SUBTRACTOR
VHDL CODE:
--Design
: HALF SUBSTRACTOR
--Description : To implement HALF SUBSTRACTOR
--Author
--Roll no
: 28SVL132
PAGE NO.
15
--Version
: Xilinx- 7.1i
library IEEE;
--library UNISIM;
entity halfsubstractor is
b : in std_logic;
difference : out std_logic;
barrow : out std_logic);
end halfsubstractor;
architecture Behavioral of halfsubstractor is
signal abar:std_logic;
begin
abar<= not a;
difference<= a xor b;
barrow <= abar and b;
end Behavioral;
VERILOG CODE:
module halfsub(a, b, diff, barr);
input a;
input b;
OUTPUT: diff;
OUTPUT: barr;
wire abar;
assign abar = ~a;
assign diff = a ^ b;
assign barr = abar & b;
endmodule
TEST BENCH:
LIBRARY ieee;
ENTITY HALFSUBTB_vhd IS
END HALFSUBTB_vhd;
ARCHITECTURE behavior OF HALFSUBTB_vhd IS
COMPONENT halfsubstractor
PAGE NO.
16
PORT(
a : IN std_logic;
b : IN std_logic;
diff : OUT std_logic;
barrow : OUT std_logic
);
END COMPONENT;
--Inputs
--OUTPUT:s
SIGNAL diff : std_logic;
SIGNAL barrow : std_logic;
BEGIN
uut: halfsubstractor PORT MAP(
a => a,
b => b,
diff => diff,
barrow => barrow
);
tb : PROCESS
BEGIN
a<='0'; b<='0';
a<='0'; b<='1';
a<='1'; b<='0';
a<='1'; b<='1';
END PROCESS;
wait for 100 ps;

wait for 100 ps;
wait for 100 ps;
wait for 100 ps;
END;
OUTPUT: GRAPH:
PAGE NO.
17
SYSNTHESIS REPORT:
Number of Slices:
1 out of 3584 0%
2 out of 7168 0%
4 out of 97 4%
=========================================================================
TIMING REPORT
Clock Information:
Timing Summary:
--------------Speed Grade: -5
Timing Detail:
=========================================================================
------------------------------------------------------------------------Delay:
Source:
a (PAD)
PAGE NO.
18
Destination:
difference (PAD)
FULL SUBSTRACTOR
VHDL CODE:
--Design
--Description
--Author
--Roll no
--Version
: FULL SUBSTRACTOR
: FULL SUBSTRACTOR
: 28SVL132
: Xilinx- 7.1i
library IEEE;
entity fullsubstractor is
b : in std_logic;
c : in std_logic;
difference : out std_logic;
barrow : out std_logic);
end fullsubstractor;
architecture Behavioral of fullsubstractor is
signal abar,w,x,y,z:std_logic;
begin
abar<= not a;
w<= a xor b;
difference <= w xor c;
x<= abar and b;
y<= abar and c;
z <= b and c;
barrow <= x or y or z;
end Behavioral;
VERILOG CODE:
module fullsub(a, b, c, diff, barr);
input a;
input b;
input c;
OUTPUT: diff;
OUTPUT: barr;
wire abar;
assign abar = ~a;
assign diff = a ^ b ^ c;
assign barr = (abar&b) | (b&c) | (c&abar);
endmodule
TEST BENCH:
LIBRARY ieee;
PAGE NO.
19
ENTITY fulladdertb_vhd IS
END fulladdertb_vhd;
ARCHITECTURE behavior OF fulladdertb_vhd IS
COMPONENT fullsubstractor
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
diff : OUT std_logic;
barrow : OUT std_logic
);
END COMPONENT;
--Inputs
--OUTPUT:s
SIGNAL barrow : std_logic;
BEGIN
uut: fullsubstractor PORT MAP(
a => a,
b => b,
c => c,
diff => diff,
barrow => barrow
);
tb : PROCESS
BEGIN
a<='0'; b<='0'; c<='0';
wait for 100 ps;
a<='0'; b<='0'; c<='1'; wait for 100 ps;
a<='0'; b<='1'; c<='0';
wait for 100 ps;
a<='0'; b<='1'; c<='1';
wait for 100 ps;
a<='1'; b<='0'; c<='0';
wait for 100 ps;
a<='1'; b<='0'; c<='1';
wait for 100 ps;
a<='1'; b<='1'; c<='0';
wait for 100 ps;
a<='1'; b<='1'; c<='1';
wait for 100 ps;
END PROCESS;
END;
OUTPUT: GRAPH:
PAGE NO.
20
SYNTHESIS REPORT:
Number of Slices:
1 out of 3584 0%
2 out of 7168 0%
PAGE NO.
21
5 out of
97
5%
=========================================================================
TIMING REPORT
Clock Information:
Timing Summary:
--------------Speed Grade: -5
Timing Detail:
------------------------------------------------------------------------Delay:
Source:
a (PAD)
Destination:
difference (PAD)
FULL ADDER USING TWO HALF ADDERS
VHDL SOURCE CODE:
--Design
: FULL ADDER USING TWO HALF ADDERS
--Description : FULL ADDER USING TWO HALF ADDERS
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity Fulladd is
port (a,b,c : in std_logic;
sum,carry: out std_logic);
end Fulladd;
architecture structural of Fulladd is
component halfadd is
Port ( A : in std_logic;
B : in std_logic;
S : out std_logic;
PAGE NO.
22
C : out std_logic);
end component;
component orgate is
port(x,y : in std_logic;
z: out std_logic);
end component;
signal p,q,r: std_logic;
begin
h1:halfadd port map(a,b,p,q);
h2:halfadd port map(p,c,sum,r);
o1:orgate port map(r,q,carry);
end structural;
VERILOG SOURCE CODE:
module Fulladd(a,b,c,sum,carry);
input a,b,c;
OUTPUT: sum,carry;
wire p,q,r;
halfadd
h1(a,b,p,q),
h2(p,c,sum,q);
or
o1(carry,q,r);
endmodule
TEST BENCH(VHDL) :
LIBRARY ieee;
ENTITY full_adder_vhd IS
END full_adder_vhd;
ARCHITECTURE behavior OF full_adder_vhd IS
COMPONENT fulladd
PORT(a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
END COMPONENT;
--Inputs
--OUTPUT:s
PAGE NO.
23
BEGIN
uut: fulladd PORT MAP(
a => a,
b => b,
c => c,
sum => sum,
carry => carry);
tb : PROCESS
BEGIN
a<='0';b<='0';c<='1';wait for 200 ps;
a<='0';b<='1';c<='0';wait for 200 ps;
a<='0';b<='0';c<='1';wait for 200 ps;
a<='1';b<='0';c<='1';wait for 200 ps;
a<='1';b<='1';c<='0';wait for 200 ps;
END PROCESS;
END;
SIMULATION OUTPUT:
PAGE NO.
24
SYNTHESIS REPORT:
=========================================================================
Macro Statistics
# Xors
:2
1-bit xor2
:2
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
1 out of 3584 0%
2 out of 7168 0%
5 out of 97 5%
=========================================================================
TIMING REPORT
Clock Information:
Timing Summary:
--------------Speed Grade: -5
PAGE NO.
25

FULL SUBTRACTOR USING TWO HALF SUBTRACTORS
VHDL SOURCE CODE:
--Design
--Description
--Author
--Roll no
--Version
: FULL SUBTRACTOR USING TWO HALF SUBTRACTORS

: FULL SUBTRACTOR USING TWO HALF SUBTRACTORS
: 28SVL132
: Xilinx- 7.1i
library IEEE;
entity fullsub is
Port ( a,b,c : in std_logic;
bor,diff : out std_logic);
end fullsub;
architecture structural of fullsub is
component halfsub1 is
b : in std_logic;
diff : out std_logic;
borr : out std_logic);
end component;
component orgate is
port ( x,y : in std_logic;
z: out std_logic);
end component;
signal p,q,r: std_logic;
begin
h1:halfsub1 port map(a,b,p,q);
h2:halfsub1 port map (p,c,diff,r);
o1: orgate port map(q,r,bor);
end structural;
module fsub_2hs( diff,bor, a,b,c);
OUTPUT: diff;
OUTPUT: bor;
input a,b,c;
wire p,q,r;
halfsub hs1(p,q,a,b);
halfsub hs2(diff,r,p,c);
or o1(bor,r,q);
endmodule
PAGE NO.
26
TEST BENCH(VHDL):
LIBRARY ieee;
ENTITY full_subtractor_vhd IS
END full_subtractor_vhd;
ARCHITECTURE behavior OF full_subtractor_vhd IS
COMPONENT fullsub
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
bor : OUT std_logic;
diff : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL bor : std_logic;
BEGIN
uut: fullsub PORT MAP(
a => a,
b => b,
c => c,
bor => bor,
diff => diff
);
tb : PROCESS
BEGIN
wait for 100 ns;
END PROCESS;
a<='1','0' after 10 ns, '1' after 20 ns,'1' after 30 ns;
b<='1','0' after 10 ns, '0' after 20 ns,'1' after 30 ns;
c<='1','0' after 10 ns, '1' after 20 ns,'0' after 30 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
27
SYNTHESIS REPORT:
=========================================================================
Macro Statistics
# Xors
:2
1-bit xor2
:2
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
1 out of 3584 0%
2 out of 7168 0%
5 out of 97 5%
=========================================================================
TIMING REPORT
PAGE NO.
28
Clock Information:
Timing Summary:
--------------Speed Grade: -5
RIPPLE CARRY ADDER
PAGE NO.
29
FAST ADDERS:
CARRY SELECT ADDER:
LOGIC DIAGRAM:
CARRY LOOKAHEAD ADDER:

LOGIC DIAGRAM:
CARRY SKIP ADDER:
PAGE NO.
30
LOGIC DIAGRAM:
RIPPLE CARRY ADDER

VHDL CODE:
--Design
: RIPPLE CARRY ADDER
--Description : RIPPLE CARRY ADDER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
--library UNISIM;
entity rca is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
cin : in std_logic;
sum : out std_logic_vector(7 downto 0);
cout : out std_logic);
end rca;
architecture structural of rca is
component fulladder
port (a,b,c: in std_logic;
sum,carry: out std_logic);
end component;
signal c1,c2,c3,c4,c5,c6,c7:std_logic;
begin
f1:fulladder port map(a(0),b(0),cin,sum(0),c1);
f2:fulladder port map(a(1),b(1),c1,sum(1),c2);
f8:fulladder port map(a(7),b(7),c7,sum(7),cout);
PAGE NO.
31
end structural;
VERILOG CODE:
module rca(a, b, cin, sum, cout);
input [7:0] a;
input [7:0] b;
input cin;
OUTPUT: [7:0] sum;
OUTPUT: cout;
wire c1,c2,c3,c4,c5,c6,c7;
fulladder
fulladder
fulladder
fulladder
fulladder
fulladder
fulladder
fulladder
f1(a[0],b[0],cin,sum[0],c1);
f2(a[1],b[1],c1,sum[1],c2);
f3(a[2],b[2],c2,sum[2],c3);
f4(a[3],b[3],c3,sum[3],c4);
f5(a[4],b[4],c4,sum[4],c5);
f6(a[5],b[5],c5,sum[5],c6);
f7(a[6],b[6],c6,sum[6],c7);
f8(a[7],b[7],c7,sum[7],cout);
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
ENTITY riple_carry_vhd IS
END riple_carry_vhd;
ARCHITECTURE behavior OF riple_carry_vhd IS
COMPONENT ripplecarry
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
cin : IN std_logic;
sum : OUT std_logic_vector(7 downto 0);
cout : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL cin : std_logic := '0';
SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');
--OUTPUT:s
SIGNAL sum : std_logic_vector(7 downto 0);
SIGNAL cout : std_logic;
BEGIN
PAGE NO.
32
uut: ripplecarry PORT MAP(

a => a,
b => b,
cin => cin,
sum => sum,
cout => cout
);
tb : PROCESS
BEGIN
wait for 100 ns;
END PROCESS;
a<="00000000","00010001" after 10 ns,"11111111" after 20 ns;
a<="01100110","11010001" after 10 ns,"11111111" after 20 ns;
END;
OUTPUT: GRAPH:
SYNTHESIS REPORT:
PAGE NO.
33

Number of Slices:
10 out of 3584 0%
17 out of 7168 0%
26 out of 97 26%
TIMING REPORT
Clock Information:
Timing Summary:
--------------Speed Grade: -5
Timing Detail:
------------------------------------------------------------------------Delay:
Source:
cin (PAD)
Destination:
cout (PAD)
CARRY SELECT ADDER
VHDL CODE:
--Design
: CARRY SELECT ADDER
--Description : CARRY SELECT ADDER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
--library UNISIM;
PAGE NO.
34
entity csela is
cin : in std_logic;
end csela;
architecture structural of csela is
component rcafourbit is
port (a,b: in std_logic_vector(3 downto 0);
cin: in std_logic;
sum: out std_logic_vector(3 downto 0);
cout: out std_logic);
end component;
component mux2 is
port (a,b,s: in std_logic;
z: out std_logic);
end component;
signal s0,s1,s2,c0,c1:std_logic;
signal s3,s4:std_logic_vector(3 downto 0);
begin
s1 <= '0';
s2 <= '1';
r1:rcafourbit port map (a(3downto 0),b(3 downto 0),cin,sum(3 downto 0),s0);
r2:rcafourbit port map (a(7downto 4),b(7 downto 4),s1,s3(3 downto 0),c0);
r3:rcafourbit port map (a(7downto 4),b(7 downto 4),s2,s4(3 downto 0),c1);
m1:mux2 port map (s3(3),s4(3),s0,sum(7));
m5:mux2 port map (c0,c1,s0,cout);
end structural;
VERILOG CODE:
module csa(a, b, cin, sum, cout);
input [7:0] a;
input [7:0] b;
input cin;
OUTPUT: [7:0] sum;
OUTPUT: cout;
wire c1,c2,c3;
wire [3:0]s1,s2;
rcafourbit
r1(a[3:0],b[3:0],cin,sum[3:0],c1),
r2(a[7:4],b[7:4],1'b0,s1[3:0],c2),
r3(a[7:4],b[7:4],1'b1,s2[3:0],c3);
muxtwo
m1(s1[3],s2[3],c1,sum[7]),
m2(s1[2],s2[2],c1,sum[6]),
m3 (s1[1],s2[1],c1,sum[5]),
ss
PAGE NO.
35
m4(s1[0],s2[0],c1,sum[4]);
endmodule
TEST BENCH(VHDL) :
LIBRARY ieee;
ENTITY cs_adder_vhd IS
END cs_adder_vhd;
ARCHITECTURE behavior OF cs_adder_vhd IS
COMPONENT csa
PORT(
cin : IN std_logic;
);
END COMPONENT;
BEGIN
uut: csa PORT MAP(
a => a,
b => b,
cin => cin,
sum => sum,
cout => cout
);
tb : PROCESS
BEGIN
cin<='0'; wait for 100ps;
END PROCESS;
a<="00000000","00101001" after 100 ps,"00010010" after 200 ps,"11110010" after 300 ps;
b<="01001000","10101101" after 100 ps,"00000010" after 200 ps,"11111111" after 300 ps;
END;
OUTPUT: GRAPH:
PAGE NO.
36
SYSNTHESIS REPORT:
Number of Slices:
12 out of 3584 0%
20 out of 7168 0%
26 out of 97 26%
TIMING REPORT
Clock Information:
PAGE NO.
37

Timing Summary:
--------------Speed Grade: -5
Timing Detail:
=========================================================================
------------------------------------------------------------------------Delay:
Source:
cin (PAD)
Destination:
sum<6> (PAD)
CARRY LOOK AHEAD ADDER
VHDL SOURCE CODE:
--Design
: CARRY LOOK AHEAD ADDER
--Description : CARRY LOOK AHEAD ADDER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
--library UNISIM;
entity cla is
cin : in std_logic;
end cla;
architecture Behavioral of cla is
signal tsum:std_logic_vector(8 downto 1);
signal tc:std_logic_vector(8 downto 1);
PAGE NO.
38
signal p:std_logic_vector(8 downto 1);

signal g:std_logic_vector(8 downto 1);
begin
tsum <= a xor b;
g <= a and b;
p <= a or b;
process (g,p,tc,tsum)
begin
tc(1) <= g(1) or (p(1) and cin);
for i in 2 to 8 loop
tc(i) <= g(i) or (p(i) and tc(i));
end loop;
end process;
sum(1) <= tsum(1) xor cin;
sum( 8 downto 2) <= tsum(8 downto 2) xor tc(8 downto 2);
cout <= tc(8);
end Behavioral;
module carrylookaheadadder(a, b, cin, sum, cout);
input [7:0] a;
input [7:0] b;
input cin;
OUTPUT: [7:0] sum;
OUTPUT: cout;
reg [7:0] tc;
wire [7:0] p,tsum,g;
integer i;
assign tsum = a ^ b;
assign g = a & b;
assign p = a | b;
always @ (g or p or tsum) begin
tc[0]=cin;
tc[1]=g[0]|(p[0]+cin);
for (i=1;i<8;i=i+1)
tc[i] = g[i] | (p[i] & tc[i]);
end
assign sum[0] = tsum[0] ^ cin;
assign sum[7:1] = tsum[7:1] ^ tc[7:1];
assign cout = tc[7];
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
ENTITY carrylook_vhd IS
END carrylook_vhd;
PAGE NO.
39
ARCHITECTURE behavior OF carrylook_vhd IS

COMPONENT carry_look
PORT(
cin : IN std_logic;
);
END COMPONENT;
--Inputs
--OUTPUT:s
BEGIN
uut: carry_look PORT MAP(
a => a,
b => b,
cin => cin,
sum => sum,
carry => carry
);
tb : PROCESS
BEGIN
END PROCESS;
a<="00000000","00101001" after 100 ps,"00010010" after 200 ps,"11110010" after 300 ps;
b<="01001011","10101101" after 100 ps,"11100010" after 200 ps,"11111111" after 300 ps;
END;
SIMULATION OUTPUT:
PAGE NO.
40
SYNTHESIS REPORT:
Number of Slices:
9 out of 3584 0%
15 out of 7168 0%
26 out of 97 26%
TIMING REPORT
Clock Information:
Timing Summary:
--------------Speed Grade: -5
PAGE NO.
41
Timing Detail:
=========================================================================
------------------------------------------------------------------------Delay:
Source:
a<8> (PAD)
Destination:
sum<8> (PAD)
CARRY SKIP ADDER
VHDL SOURCE CODE:
--Design
: CARRY SKIP ADDER
--Description : CARRY SKIP ADDER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
--library UNISIM;
entity csa is
cin : in std_logic;
end csa;
architecture Behavioral of csa is
component rcafourbit is
port (a,b: in std_logic_vector(3 downto 0);
cin : in std_logic;
sum: out std_logic_vector(3 downto 0);
end component;
component orgate
port (a,b: in std_logic;
c:out std_logic);
end component;
component andgate5
port (p,q,r,s,t: in std_logic;
u: out std_logic);
end component;
signal p:std_logic_vector(7 downto 0);
PAGE NO.
42
signal s0,s1,s2,s3,s4 : std_logic;

begin
q1:rcafourbit port map (a(3 downto 0),b(3 downto 0),cin,sum(3 downto 0),s3);
process (a,b)
begin
for i in 0 to 7 loop
p(i) <= a(i) xor b(i);
end loop;
end process;
a1:andgate5 port map (p(0),p(1),p(2),p(3),cin,s0);
a2:andgate5 port map (p(4),p(5),p(6),p(7),s2,s1);
r1:orgate port map (s3,s0,s2);
q2:rcafourbit port map (a(7 downto 4),b(7 downto 4),s2,sum(7 downto 4),s4);
r2:orgate port map (s4,s1,cout);
end Behavioral;
module csa(a, b, cin, s, c8);
input [8 :1]a, b; input cin; OUTPUT: [8 :1]s; OUTPUT: c8;
wire cout, c4, cout1;
ripple
r1(a[4 :1], b[4:1], cin, s[4 :1], cout),
r2(a[8 :5], b[8:5], c4, s[8 :5], cout1);
skip
s1(a[4:1], b[4:1], cin, cout, c4),
s2(a[8:5], b[8:5], c4, cout1, c8);
endmodule
VERILOG CODE FOR SKIP CIRCUIT:
module skip(a,b,cin, ccout, cout);
input [4:1]a, b;
input cin, ccout;
OUTPUT: cout;
reg [4:1]p;
reg cskip, pout;
reg cout;
always
@(a, b, cin, ccout) begin
p[1] = a[1] ^ b[1];
p[2] = a[2] ^ b[2];
p[3] = a[3] ^ b[3];
p[4] = a[4] ^ b[4];
pout = p[1] & p[2] & p[3] & p[4];
cskip = pout & cin;
cout = ccout | cskip;
end
endmodule
VERILOG CODE FOR RIPPLE CARRY ADDER:
PAGE NO.
43
module ripple(a, b, cin, s, cout);

input [3:0] a, b;
input cin;
OUTPUT: cout;
OUTPUT: [3:0]s;
wire c0,c1,c2;
FADD
f1(a[0], b[0], cin, s[0],c0),
f2(a[1], b[1], c0, s[1],c1),
f3(a[2], b[2], c1, s[2],c2),
f4(a[3], b[3], c2, s[3],cout);
endmodule
TEST BENCH:
LIBRARY ieee;
ENTITY csatb_vhd IS
END csatb_vhd;
ARCHITECTURE behavior OF csatb_vhd IS
COMPONENT csa
PORT(
cin : IN std_logic;
);
END COMPONENT;
--Inputs
--OUTPUT:s
BEGIN
uut: csa PORT MAP(
a => a,
b => b,
cin => cin,
sum => sum,
cout => cout
);
PAGE NO.
44
tb : PROCESS
BEGIN
a <= "10000110"; b <= "00010011"; cin <= '0';
a <= "10110110"; b <= "00000011"; cin <= '0';
a <= "10000110"; b <= "01110010"; cin <= '0';
wait for 100 ps;

wait for 100 ps;
wait for 100 ps;
END PROCESS;
END;
OUTPUT:
SYNTHESIS REPORT:
Number of Slices:
16 out of 3584 0%
27 out of 7168 0%
26 out of 97 26%
TIMING REPORT
PAGE NO.
45

Clock Information:
Timing Summary:
--------------Speed Grade: -5
Timing Detail:
------------------------------------------------------------------------Delay:
Source:
b<0> (PAD)
Destination:
cout (PAD)
RESULT:
Thus the OUTPUT:s of Adders,Subtractors and Fast Addres are verified by synthesizing and
simulating the VHDL and VERILOG code.
EXPT NO: 03
DATE:11-2-08
PAGE NO.
46
ENCODERS AND DECODERS

AIM:
To develop the source code for encoders and decoders by using VHDL/VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.
ALGORITHM:
LOGIC DIAGRAM:
ENCODER:
LOGIC DIAGRAM:
TRUTH TABLE:
D0
D1
D2
D3
D4
D5
D6
D7
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DECODERS:
LOGIC DIAGRAM:
TRUTH TABLE:
PAGE NO.
47
Z(0)
Z(1)
Z(2)
Z(3)
VHDL SOURCE CODE:

--Design
: ENCODER
--Description : To implement ENCODER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity encoder is
Port ( d : in std_logic_vector(0 to 7);
x : out std_logic;
y : out std_logic;
z : out std_logic);
end encoder2;
architecture Behavioral of encoder is
begin
process (d)
begin
x<=d(4) or d(5) or d(6) or d(7);
y<=d(2) or d(3) or d(6) or d(7);
z<=d(1) or d(3) or d(5) or d(7);
end process;
end Behavioral;
module encoder_behavioral(d, x, y, z);
input [7:0] d;
OUTPUT: x;
OUTPUT: y;
OUTPUT: z;
reg x,y,z;
always
@ (d[7:0]) begin
x=d[4]|d[5]|d[6]|d[7];
y=d[2]|d[3]|d[6]|d[7];
PAGE NO.
48
z=d[1]|d[3]|d[5]|d[7];
end
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
ENTITY test_encoder_vhd IS
END test_encoder_vhd;
ARCHITECTURE behavior OF test_encoder_vhd IS
COMPONENT encoder2
PORT(
d : IN std_logic_vector(0 to 7);
x : OUT std_logic;
y : OUT std_logic;
z : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL d : std_logic_vector(0 to 7) := (others=>'0');
--OUTPUT:s
SIGNAL x : std_logic;
SIGNAL y : std_logic;
SIGNAL z : std_logic;
BEGIN
uut: encoder2 PORT MAP(
d => d,
x => x,
y => y,
z => z
);
tb : PROCESS
BEGIN
wait for 100 ns;
END PROCESS;
d<="00000000","00010000" after 10 ns, "00000010" after 20 ns,"00000100" after 30 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
49
SYNTHESIS REPORT:
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
2 out of 3584 0%
3 out of 7168 0%
11 out of 97 11%
=========================================================================
TIMING REPORT
PAGE NO.
50
Clock Information:
Timing Summary:
--------------Speed Grade: -5
DECODER
VHDL SOURCE CODE:
--Design
--Description
--Author
--Roll no
--Version
: DECODER
: To implement DECODER
: 28SVL132
: Xilinx- 7.1i
library IEEE;
entity decoder2to4 is
Port ( a,b,en_l : in std_logic;
z0,z1,z2,z3 : out std_logic);
end decoder2to4;
architecture Behavioral of decoder2to4 is
begin
process(a,b,en_l)
begin
z0<=not((not a)and (not b) and en_l);
z1<=not((not a)and b and en_l);
z2<=not(a and (not b) and en_l);
z3<=not(a and b and en_l);
end process;
end Behavioral;
module decoder2_4(z0,z1,z2,z3, a,b,en);
OUTPUT: z0,z1,z2,z3;
input a,b,en;
reg z0,z1,z2,z3;
always@ (a,b,en)
begin
PAGE NO.
51
z0=~((~ a)& (~ b) & en);

z1=~((~ a)& b & en);
z2=~(a & (~ b) & en);
z3=~(a & b & en);
end
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
ENTITY encoder2_4_vhd IS
END encoder2_4_vhd;
ARCHITECTURE behavior OF encoder2_4_vhd IS

COMPONENT decoder2to4
PORT(
a : IN std_logic;
b : IN std_logic;
en_l : IN std_logic;
z0 : OUT std_logic;
z1 : OUT std_logic;
z2 : OUT std_logic;
z3 : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL en_l : std_logic := '0';
--OUTPUT:s
SIGNAL z0 :
SIGNAL z1 :
SIGNAL z2 :
SIGNAL z3 :
std_logic;
std_logic;
std_logic;
std_logic;
BEGIN
uut: decoder2to4 PORT MAP(
a => a,
b => b,
en_l => en_l,
z0 => z0,
z1 => z1,
z2 => z2,
PAGE NO.
52
z3 => z3
);
tb : PROCESS
BEGIN
wait for 100 ns;
END PROCESS;
a<='0','0' after 10 ns,'1' after 20 ns, '1' after 30 ns, '0' after 40 ns;
b<='0','1' after 10 ns,'0' after 20 ns, '1' after 30 ns;
en_l<='1','0' after 40ns,'1' after 60ns;
END;
SIMULATION OUTPUT:
SYNTHESIS REPORT:
PAGE NO.
53
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
5 out of 3584 0%
8 out of 7168 0%
11 out of 97 11%
=========================================================================
TIMING REPORT
Clock Information:
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of Encoders and Decoders are verified by synthesizing and simulating the
VHDL and VERILOG code.
PAGE NO.
54
EXPT NO: 04
DATE:13-2-08
MULTIPLEXER AND DEMULTIPLEXER
AIM:
To develop the source code for multiplexer and demultiplexer by using VHDL/VERILOG and
obtain the simulation, synthesis, place and route and implement into FPGA.
ALGORITHM:
LOGIC DIAGRAM:
MULTIPLEXER:
LOGIC DIAGRAM:
TRUTH
TABLE:
1
2
8
D1
1
2
8
D2
1
2
8
D3
1
2
8
S1
SELECT INPUT
2
3
1
S1
S0
D0
D1
D2
D3
4
5
OUTPUT:
D0
S0
DEMULTIPLEXER:
LOGIC DIAGRAM:
`
TRUTH
TABLE:
PAGE NO.
55
1
2
S0
S1
D
1
1
1
1
2
3
Din
4
5
2
3
4
5
2
3
4
5
2
3
4
5
INPUT
S0
S1
0
0
0
1
1
0
1
1
Y0
1
0
0
0
OUTPUT:
Y1
Y2
0
0
1
0
0
1
0
0
Y0
Y1
Y2
Y3
Enable
VHDL SOURCE CODE:

--Design
: MULTIPLEXER
--Description : To implement MULTIPLEXER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity mux is
Port ( s : in std_logic_vector(1 downto 0);
i : in std_logic_vector(3 downto 0);
y : out std_logic);
end mux;
architecture dataflow of mux is
signal s1bar, s0bar, p, q, r, t : std_logic;
begin
y<= p or q or r or t;
p<= i(0) and s1bar and s0bar;
s1bar<= not s(1);
s0bar<= not s(0);
q<= i(1) and s1bar and s(0);
r<= i(2) and s(1) and s0bar;
t<= i(3) and s(1) and s(0);
end dataflow;
module mux(s, i, y);
input [1 : 0]s;
input [3 : 0]i;
PAGE NO.
56
Y3
0
0
0
1
OUTPUT: y;
wire s0bar, s1bar, p, q, r, t;
assign s0bar = ~ s[0];
assign s1bar = ~ s[1];
assign p= s0bar & s1bar &i[0];
assign q= s[0] & s1bar &i[1];
assign r= s0bar & s[1] &i[2];
assign t= s[0] & s[1] &i[3];
assign y = p | q | r | t;
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
ENTITY amux_vhd IS
END amux_vhd;
ARCHITECTURE behavior OF amux_vhd IS
COMPONENT mux
PORT(
s : IN std_logic_vector(1 downto 0);
i : IN std_logic_vector(3 downto 0);
y : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');
SIGNAL i : std_logic_vector(3 downto 0) := (others=>'0');
--OUTPUT:s
BEGIN
uut: mux PORT MAP(
s => s,
i => i,
y => y
);
tb : PROCESS
BEGIN
s <="00";i <="0001"; wait for 200 ps;
s <="01";i <="0010"; wait for 200 ps;
s <="10";i <="0100"; wait for 200 ps;
PAGE NO.
57
s <="11";i <="1000"; wait for 200 ps;

END PROCESS;
END;
SIMULATION OUTPUT:
SYNTHESIS REPORT:
=========================================================================
*
Final Report
*
=========================================================================
PAGE NO.
58
Number of Slices:

1 out of 3584 0%
2 out of 7168 0%
7 out of 97 7%
=========================================================================
TIMING REPORT
Clock Information:
Timing Summary:
--------------Speed Grade: -5
DEMULTIPLEXER
VHDL SOURCE CODE
--Design
: DEMULTIPLEXER
--Description : To implement DEMULTIPLEXER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity demux2 is
Port ( d : in std_logic;
s : in std_logic_vector(0 to 1);
y : out std_logic_vector(0 to 3));
end demux2;
architecture Behavioral of demux2 is
begin
process(d,s(0),s(1))
variable s1bar,s0bar:std_logic;
begin
s1bar:=not(s(1));
s0bar:=not(s(0));
y(0)<=d and s0bar and s1bar;
y(1)<=d and s0bar and s(1);
y(2)<=d and s(0) and s1bar;
y(3)<=d and s(0) and s(1);
end process;
end Behavioral;
module dmux(i,a,b,d);
PAGE NO.
59
input i,a,b;
OUTPUT:[3:0]d;
wire ibar,abar,bbar;
assign# 0.1 ibar=~i;
assign# 0.1 abar=~a;
assign# 0.1 bbar=~b;
assign#0.1 d[0]=~(abar & bbar & ibar);
assign#0.1 d[1]=~(abar & b & ibar);
assign#0.1 d[2]=~(a & bbar & ibar);
assign#0.1 d[3]=~(a & b & ibar);
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
ENTITY demux_test_vhd IS
END demux_test_vhd;
ARCHITECTURE behavior OF demux_test_vhd IS
COMPONENT demux2
PORT(
d : IN std_logic;
s : IN std_logic_vector(0 to 1);
y : OUT std_logic_vector(0 to 3)
);
END COMPONENT;
--Inputs
SIGNAL d : std_logic := '0';
SIGNAL s : std_logic_vector(0 to 1) := (others=>'0');
--OUTPUT:s
SIGNAL y : std_logic_vector(0 to 3);
BEGIN
uut: demux2 PORT MAP(
d => d,
s => s,
y => y
);
tb : PROCESS
BEGIN
d<='1'; wait for 100 ps;
END PROCESS;
s(0)<='1','1' after 10 ns,'0' after 20 ns, '0' after 30 ns;
s(1)<='1','0' after 10 ns,'1' after 20 ns, '0' after 30 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
60
SYNTHESIS REPORT:
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
2 out of 3584 0%
4 out of 7168 0%
7 out of 97 7%
=========================================================================
TIMING REPORT
Clock Information:
------------------
PAGE NO.
61
No clock signals found in this design

Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of Multiplexers and Demultiplexers are verified by synthesizing and
EXPT NO: 05
DATE:15-2-08
CODE CONVERTERS AND COMPARATOR
AIM:
To develop the source code for code converters and comparator by using VHDL/VERILOG and
obtained the simulation, synthesis, place and route and implement into FPGA.
ALGORITHM:
BINARY
Step4: Check the syntax and debug the errors if found, obtain the
0000
synthesis is report.
0001
0010
0011
0100
0101
LOGIC DIAGRAM:
0110
CODE CONVERTER (BINARY TO GRAY):
0111
1000
LOGIC DIAGRAM:
1001
TRUTH TABLE:
GRAY
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
PAGE NO.
62
VHDL SOURCE CODE

--Design
--Description
--Author
--Roll no
--Version
: BINARY TO GRAY CONVERTER

: To implement BINARY TO GRAY CONVERTER
: 28SVL132
: Xilinx- 7.1i
library IEEE;
entity bintogray is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end bintogray;
architecture structural of bintogray is
component xorgate
port (a, b: in std_logic;
c : out std_logic);
end component;
component notgate
port (a: in std_logic;
b : out std_logic);
end component;
signal s1 : std_logic;
begin
n1 : notgate port map ( b(0), s1);
n2 : notgate port map ( s1, g(0));
x1 : xorgate port map ( b(0), b(1), g(1));
x2 : xorgate port map ( b(1) , b(2), g(2));
x3 : xorgate port map ( b(2) , b(3), g(3));
end structural;
module bintogray(a, b);
input [3 :0]a;
OUTPUT: [3 : 0]b;
wire s;
not
n1(s, a[0]),
n2(b[0], s);
xor
x1(b[1], a[0], a[1]),
x2(b[2], a[1], a[2]),
x3(b[3], a[2], a[3]);
endmodule
TEST BENCH(VHDL):
PAGE NO.
63
LIBRARY ieee;
ENTITY bin2gray_test_vhd IS
END bin2gray_test_vhd;
ARCHITECTURE behavior OF bin2gray_test_vhd IS
COMPONENT bintogray
PORT(
g : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
--OUTPUT:s
SIGNAL g : std_logic_vector(3 downto 0);
BEGIN
uut: bintogray PORT MAP(
b => b,
g => g
);
tb : PROCESS
BEGIN
wait for 100 ns;
END PROCESS;
b<="0000","0001" after 1 ns,"0010" after 2 ns,"0011" after 3 ns, "0100" after 4 ns,"0101" after 5
ns;
END;
SIMULATION OUTPUT:
PAGE NO.
64
SYNTHESIS REPORT:
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
2 out of 3584 0%
3 out of 7168 0%
8 out of 97 8%
=========================================================================
TIMING REPORT
Clock Information:
Timing Summary:
--------------Speed Grade: -5
CODE CONVERTER (BCD TO EXCESS 3):
PAGE NO.
65
LOGIC DIAGRAM:
TRUTH TABLE:
BCD
EXCESS 3
VHDL SOURCE CODE:

--Design
: BCD TO EXCESS 3
--Description : To implement BCD TO EXCESS 3
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity bcd2ex3 is
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic_vector(0 to 3));
end bcd2ex3;
architecture Behavioral of bcd2ex3 is
begin
process(a,b,c,d)
variable bbar,cbar,s0,s1,s2,s3:std_logic;
begin
bbar:=not(b);
cbar:=not(c);
s3:=c or d;
s0:=b and s3;
s1:=bbar and s3;
s2:=cbar and b and (not(d));
y(0)<=a or s0;
y(1)<=s1 or s2;
y(2)<=c xnor d;
y(3)<=not(d);
end process;
end Behavioral;
BCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
EXCESS 3
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100

module bcdtoex(a,b);
input [3 :0]a;
OUTPUT: [3:0]b;
PAGE NO.
66
wire s1, s2, s3, s4, s5, s6, s7, a1bar, a2bar, a3bar;
not
n1(a1bar, a[1]),
n2(a2bar, a[2]),
n3(a3bar, a[3]),
n4(s7, a3bar),
n5(b[0], s7),
n6(b[1], s6);
or
r1(s1, a[3], a[2]),
r2(b[2], s2, s3),
r3(b[3], a[0], s4, s5);
xor
x1(s6, a[3], a[2]);
and
a1(s2, s1, a1bar),
a2(s3, a[1], a2bar, a3bar),
a3(s4, a[1], a[3]),
a4(s5, a[1], a[2]);
endmodule
TEST BENCH(VHDL) :
LIBRARY ieee;
ENTITY bcd_ex3_vhd IS
END bcd_ex3_vhd;
ARCHITECTURE behavior OF bcd_ex3_vhd IS
COMPONENT bcd2ex3
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
y : OUT std_logic_vector(0 to 3)
);
END COMPONENT;
--Inputs
SIGNAL a :
SIGNAL b :
SIGNAL c :
SIGNAL d :
std_logic := '0';
std_logic := '0';
std_logic := '0';
std_logic := '0';
--OUTPUT:s
SIGNAL y : std_logic_vector(0 to 3);
BEGIN
PAGE NO.
67

uut: bcd2ex3 PORT MAP(
a => a,
b => b,
c => c,
d => d,
y => y
);
tb : PROCESS
BEGIN
wait for 100 ns;
END PROCESS;
a<='0','1' after 1 ns, '0' after 2 ns,'1' after 3 ns,'0' after 4 ns;
b<='1','0' after 1 ns, '1' after 2 ns,'0' after 3 ns,'1' after 4 ns;
c<='1','0' after 1 ns, '0' after 2 ns,'1' after 3 ns,'0' after 4 ns;
d<='0','1' after 1 ns, '0' after 2 ns,'0' after 3 ns,'0' after 4 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
68
SYNTHESIS REPORT:
-------------------------=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
2 out of 3584 0%
3 out of 7168 0%
8 out of 97 8%
=========================================================================
TIMING REPORT
Clock Information:
Timing Summary:
--------------Speed Grade: -5
4 BIT COMPARATOR:
PAGE NO.
69
VHDL SOURCE CODE:

--Design
: 4 BIT COMPARATOR
--Description : To implement 4 BIT COMPARATOR
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity comp is
Port ( a,b : in std_logic_vector(3 downto 0);
x,y,z : out std_logic);
end comp;
architecture Behavioral of comp is
begin
process(a,b)
begin
if(a=b) then
x<='1';y<='0';z<='0';
elsif(a<b)then
x<='0';y<='1';z<='0';
else
x<='0';y<='0';z<='1';
end if;
end process;
end Behavioral;
VERILOG SOURCE CODE

module comp1(x,y,z, a,b);
input [3:0] a,b;
OUTPUT: x,y,z;
reg x,y,z;
always@(a,b)
begin
if(a==b)
begin
x=1'b1;y=1'b0;z=1'b0;
end
else if(a<b)
PAGE NO.
70
begin
x=1'b0;y=1'b1;z=1'b0;
end
else
begin
x=1'b0;y=1'b0;z=1'b1;
end
end
endmodule
TEST BENCH(VHDL)
LIBRARY ieee;
ENTITY comp_test_vhd IS
END comp_test_vhd;
ARCHITECTURE behavior OF comp_test_vhd IS
COMPONENT comp
PORT(
x : OUT std_logic;
y : OUT std_logic;
z : OUT std_logic
);
END COMPONENT;
SIGNAL x : std_logic;
BEGIN
uut: comp PORT MAP(
a => a,
b => b,
x => x,
y => y,
z => z
);
tb : PROCESS
BEGIN
wait for 100 ps;
END PROCESS;
a<="1001","0101" after 10 ns,"1000" after 20 ns,"1111" after 30 ns;
b<="0001","0101" after 10 ns,"1001" after 20 ns,"1100" after 30 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
71
SYNTHESIS REPORT:
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
5 out of 3584 0%
9 out of 7168 0%
PAGE NO.
72

11 out of 97 11%
=========================================================================
TIMING REPORT
.
Clock Information:
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of Code converters and comparator are verified by synthesizing and
EXPT NO: 06
DATE:21-2-08
DESIGN OF FLIP FLOPS
AIM:
To develop the source code for flip flops by using VHDL/VERILOG and Obtained the simulation,
synthesis, place and route and implement into FPGA.
ALGORITHM:
PAGE NO.
73
LOGIC DIAGRAM:
SR FLIPFLOP:
LOGIC DIAGRAM:
TRUTH TABLE:
Q(t)
0
0
0
0
1
1
1
1
CP
1
S
0
0
1
1
0
0
1
1
Q(t+1)
0
1
0
1
0
1
0
1
0
0
1
X
1
0
1
X
JK FLIPFLOP:
LOGIC DIAGRAM:
TRUTH TABLE:
1
2
8
1
2
8
CP
Q(t)
Q(t+1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
1
0
D FLIPFLOP:
LOGIC DIAGRAM:
1
1
2
TRUTH TABLE:
3
CP
1
2
1
3
Q(t)
Q(t+1)
0
0
1
1
0
1
0
1
0
1
0
1
T FLIPFLOP:
PAGE NO.
74
LOGIC DIAGRAM:
1
2
8
CP
TRUTH TABLE:
VHDL
SOURCE
CODE
--Design
--Description : To implement SR FLIPFLOP
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
1
2
8
Q(t)
Q(t+1)
0
0
1
1
0
1
0
1
0
1
1
0
: SR FLIPFLOP
library IEEE;
entity srff is
Port ( s,r,clk,rst : in std_logic;
q,qbar : inout std_logic);
end srff;
architecture Behavioral of srff is
begin
process(s,r,clk,rst,q,qbar)
begin
if(rst='1')then
q<='0'; qbar<='1';
elsif(clk='1' and clk'event)then
if(s='0' and r='0') then
q<=q; qbar<=qbar;
elsif(s='0' and r='1')then
q<='0'; qbar<='1';
elsif(s='1' and r='0')then
q<='1'; qbar<='0';
else
q<='X'; qbar<='X';
end if;
end if;
end process;
end Behavioral;
module srff(s, r, clk, rst, q, qbar);
input s, r, clk, rst;
OUTPUT: q, qbar;
reg q, qbar;
always @(posedge clk) begin
if (rst == 1'b1) begin
PAGE NO.
75
q = 1'b0; qbar = 1'b0;

end
else if( s == 1'b0 && r == 1'b0) begin
q = q; qbar = qbar;
end
else if (s == 1'b0 && r == 1'b1) begin
q = 1'b0; qbar = 1'b1;
end
else if (s == 1'b1 && r == 1'b0) begin
q = 1'b1; qbar = 1'b0;
end
else begin
q = 1'b0; qbar = 1'b1;
end
end
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
ENTITY srf_vhd IS
END srf_vhd;
ARCHITECTURE behavior OF srf_vhd IS
COMPONENT srff
PORT(
s : IN std_logic;
r : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic;
qbar : INOUT std_logic
);
END COMPONENT;
SIGNAL s : std_logic := '0';
SIGNAL r : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL q : std_logic;
SIGNAL qbar : std_logic;
BEGIN
uut: srff PORT MAP(
s => s,
r => r,
clk => clk,
PAGE NO.
76
rst => rst,

q => q,
qbar => qbar
);
tb : PROCESS
BEGIN
clk<='0';wait for 200 ps;
END PROCESS;
rst<='1','0' after 10 ns;
s<='1','0' after 1 ns, '1' after 2 ns,'0' after 3 ns;
r<='1','0' after 1 ns, '0' after 2 ns,'1' after 3 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
77
SYNTHESIS REPORT:
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
1 out of 3584 0%
2 out of 7168 0%
5 out of 97 5%
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk
| BUFGP
|2 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
Minimum input arrival time before clock: 3.529ns
Maximum OUTPUT: required time after clock: 6.216ns
Maximum combinational path delay: No path found
JK FLIP FLOP
PAGE NO.
78
VHDL SOURCE CODE:

--Design
: JK FLIPFLOP
--Description : To implement JK FLIPFLOP
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity jkff is
Port ( j,k : in std_logic;
clk,rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end jkff;
architecture Behavioral of jkff is
begin
process (j, k, clk, rst, q, qbar)
begin
if (rst = '1') then
q <= '0';
qbar <= '0';
else if (clk = '1' and clk'event) then
if (j = '0' and k = '0' ) then
q <= q; qbar <= qbar;
elsif (j = '0' and k = '1' ) then
q <='0'; qbar <= '1';
elsif (j = '1' and k = '0' ) then
q <='1'; qbar <= '0';
else
q <= not(q); qbar <= not(qbar);
end if;
end if;
end if;
end process;
end Behavioral;
module jkff(j, k, clk, rst, q, qbar);
input j, k, clk, rst;
OUTPUT: q, qbar;
reg q, qbar;
always @(posedge clk) begin
q = 1'b0; qbar = 1'b0;
end
else if( j == 1'b0 && k == 1'b0) begin
q = q; qbar = qbar;
end
else if (j == 1'b0 && k == 1'b1) begin
q = 1'b0; qbar = 1'b1;
end
PAGE NO.
79
else if (j == 1'b1 && k == 1'b1) begin

q = ~q; qbar = ~qbar;
end
else begin
q = 1'b1; qbar = 1'b0;
end
end
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
ENTITY jk_ff_vhd IS
END jk_ff_vhd;
ARCHITECTURE behavior OF jk_ff_vhd IS
COMPONENT jjkkff
PORT(
j : IN std_logic;
k : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
);
END COMPONENT;
--Inputs
SIGNAL j : std_logic := '0';
SIGNAL k : std_logic := '0';
--BiDirs
BEGIN
uut: jjkkff PORT MAP(
j => j,
k => k,
clk => clk,
rst => rst,
q => q,
qbar => qbar
);
tb : PROCESS
BEGIN
PAGE NO.
80

END PROCESS;
j<='1','0' after 1 ns, '1' after 2 ns,'0' after 3 ns;
k<='1','0' after 1 ns, '0' after 2 ns,'1' after 3 ns;
END;
SIMULATION OUTPUT:
SYNTHESIS REPORT:
=========================================================================
Macro Statistics
# Registers
:2
1-bit register
:2
# Multiplexers
:2
1-bit 4-to-1 multiplexer
:2
=========================================================================
*
Final Report
*
=========================================================================
---------------------------
PAGE NO.
81
Selected Device : 3s400tq144-5

Number of Slices:
Number of Slice Flip Flops:
Number of GCLKs:
2 out of 3584 0%
2 out of 7168 0%
3 out of 7168 0%
6 out of 97 6%
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|2 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
Minimum period: 2.085ns (Maximum Frequency: 479.513MHz)
D FLIP FLOP
VHDL SOURCE CODE:
--Design
--Description
--Author
--Roll no
--Version
: D FLIPFLOP
: To implement D FLIPFLOP
: 28SVL132
: Xilinx- 7.1i
library IEEE;
entity dff is
clk : in std_logic;
reset : in std_logic;
q : out std_logic;
qbar : out std_logic);
end dff;
architecture adff of dff is
signal qt, qbart : std_logic;
begin
PAGE NO.
82
p1 : process (d, clk, reset)

begin
if (reset = '1') then
qt <= '0';
qbart <= '0';
elsif (clk = '1' and clk'event) then
qt <= ((not clk) and qt) or (clk and d);
qbart <= not qt;
end if;
end process p1;
q <= qt;
qbar <= qbart;
end adff;
module dff(data, clk, rst, q, qbar);
input data,clk,rst;
OUTPUT: q, qbar;
reg q, qbar;
always @(posedge clk)begin
if(rst == 1'b1)begin
q = 1'b0; qbar = 1'b1;
end
else begin
q = data; qbar = ~ data;
end
end
endmodule
TEST BENCH:
LIBRARY ieee;
ENTITY ddflip_vhd IS
END ddflip_vhd;
ARCHITECTURE behavior OF ddflip_vhd IS
COMPONENT dff
PORT(
d : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
q : OUT std_logic;
qbar : OUT std_logic
);
END COMPONENT;
--Inputs
PAGE NO.
83
SIGNAL reset : std_logic := '0';

--OUTPUT:s
BEGIN
uut: dff PORT MAP(
d => d,
clk => clk,
reset => reset,
q => q,
qbar => qbar
);
tb : PROCESS
BEGIN
clk <='1'; wait for 50 ps;
clk <='0'; wait for 50 ps;
END PROCESS;
reset <='1','0' after 100 ps,'1' after 600 ps;
d <='0','0' after 100 ps,'1' after 200 ps ,'1' after 300 ps;
END;
SIMULATION OUTPUT:
PAGE NO.
84
SYNTHESIS REPORT:
=========================================================================
Macro Statistics
# Registers
:2
1-bit register
:2
=========================================================================
*
Final Report
*
=========================================================================
Final Results
Number of Slices:
2 out of 3584 0%
3 out of 7168 0%
5 out of 97 5%
Number of GCLKs:
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
-----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|3 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
T FLIP FLOP
PAGE NO.
85
VHDL SOURCE CODE

--Design
: T FLIPFLOP
--Description : To implement T FLIPFLOP
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity tff2 is
Port ( clk : in std_logic;
reset : in std_logic;
t : in std_logic;
end tff2;
architecture Behavioral of tff2 is
begin
process (clk,reset,t)
begin
if(reset='1')then
q<='0';
qbar<='1';
if(t='0')then
q<=q;
qbar<=qbar;
else
q<=not(q);
qbar<=not(qbar);
end if;
end if;
end process;
end Behavioral;
module tff(t, clk, rst, q, qbar);
input t,clk,rst;
OUTPUT: q, qbar;
reg q,qbar;
always @ (posedge clk) begin
q = 1'b0; qbar =1'b1;
end
else begin
q =~t; qbar = t;
end
end
endmodule
TEST BENCH(VHDL):
PAGE NO.
86
LIBRARY ieee;
ENTITY t_ff_vhd IS
END t_ff_vhd;
ARCHITECTURE behavior OF t_ff_vhd IS
COMPONENT tff
PORT(
clk : IN std_logic;
rst : IN std_logic;
t : IN std_logic;
);
END COMPONENT;
--Inputs
SIGNAL t : std_logic := '0';
--BiDirs
BEGIN
uut: tff PORT MAP(
clk => clk,
rst => rst,
t => t,
q => q,
qbar => qbar
);
tb : PROCESS
BEGIN
clk <='0'; wait for 5 ns;
END PROCESS;
rst <='1','0' after 15 ps;
t <='1','0' after 20 ns,'1' after 30 ns ,'0' after 40 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
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SYNTHESIS REPORT:
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of GCLKs:
1 out of 3584 0%
2 out of 7168 0%
1 out of 7168 0%
5 out of 97 5%
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
PAGE NO.
88
clk
| BUFGP
|2 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of Flip Flops are verified by synthesizing and simulating the VHDL and
VERILOG code.
EXPT NO: 07
DATE:25-2-08
PAGE NO.
89
DESIGN OF REGISTER USING LATCHES AND FLIP FLOPS

AIM:
To develop the source code for register and latches using flip-flops by using VHDL/VERILOG
and Obtained the simulation, synthesis, place and route and implement into FPGA.
ALGORITHM:
STEP 1: Define the specification and initialize the design.
STEP 2: Declare the name of the entity and architecture by using VHDL source code.
STEP 3: Write the source code in VERILOG.
STEP 4: Check the syntax and debug the error is found. Obtain the SYNTHESIS REPORT.
STEP 5: Verify the OUTPUT: by simulating the source code.
STEP 6: Write the all-possible combination of input using the test bench.
STEP 7: Obtain the place and route report.
LOGIC DIAGRAM:
REGISTER:
LATCHES:
VHDL SOURCE CODE:

--Design
--Description
--Author
--Roll no
--Version
: REGISTER USING FLIP FLOPS

: To implement REGISTER USING FLIP FLOPS
: 28SVL132
: Xilinx- 7.1i
-----8 bit register in D flip flop in behavioral model----library IEEE;

entity regs_d is
Port ( clk,rst : in std_logic;
d : in std_logic_vector(7 downto 0);
PAGE NO.
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q,qbar : inout std_logic_vector(7 downto 0));

end regs_d;
architecture Behavioral of regs_d is
begin
process(clk,rst,d)
begin
if(clk='1' and clk'event)then
if(rst='1')then
q<=(others=>'0');
qbar<=(others=>'1');
else
q<=d;
qbar<=not d;
end if;
end if;
end process;
end Behavioral;
module regs(clk,rst, d, q);
input clk,rst;
input [7:0] d;
OUTPUT: [7:0] q;
reg [7:0]q;
always@(posedge clk or posedge rst)
begin
if (rst)
q=8'h00;
else
q=d;
end
endmodule
TEST BENCH(VHDL) :
LIBRARY ieee;
ENTITY reg_ff_vhd IS
END reg_ff_vhd;
ARCHITECTURE behavior OF reg_ff_vhd IS
COMPONENT regs_d
PORT(
clk : IN std_logic;
rst : IN std_logic;
d : IN std_logic_vector(7 downto 0);
q : INOUT std_logic_vector(7 downto 0);
qbar : INOUT std_logic_vector(7 downto 0)
);
PAGE NO.
91
END COMPONENT;
--Inputs
SIGNAL d : std_logic_vector(7 downto 0) := (others=>'0');
--BiDirs
SIGNAL q : std_logic_vector(7 downto 0);
SIGNAL qbar : std_logic_vector(7 downto 0);
BEGIN
uut: regs_d PORT MAP(
clk => clk,
rst => rst,
d => d,
q => q,
qbar => qbar
);
tb : PROCESS
BEGIN
END PROCESS;
rst <='1','0' after 15 ps;
d<="00010001","00001111" after 20 ns,"11110000" after 30 ns,"11111111" after 40 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
92
SYNTHESIS REPORT:
=========================================================================
Macro Statistics
# Registers
:2
8-bit register
:2
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of GCLKs:
9 out of 3584 0%
16 out of 7168 0%
26 out of 97 26%
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
| 16 |
-----------------------------------+------------------------+-------+
PAGE NO.
93
Timing Summary:
--------------Speed Grade: -5
LATCHES
VHDL SOURCE CODE:
--Design
--Description
--Author
--Roll no
--Version
: REGISTER USING LATCHES

: To implement REGISTER USING LATCHES
: 28SVL132
: Xilinx- 7.1i
library IEEE;
entity dlatch_reg is
Port ( en,rst : in std_logic;
d : in std_logic_vector(7 downto 0);
q,qbar : inout std_logic_vector(7 downto 0));
end dlatch_reg;
architecture Behavioral of dlatch_reg is
begin
process(en,d,rst)
begin
if(rst='1')then
q<=(others=>'0');
qbar<=(others=>'1');
elsif(en='1')then
q<=d;
qbar<=not d;
end if;
end process;
end Behavioral;
VERILOG SOURCE CODE
module dff_latches(dout, din, en,rst);
OUTPUT: [7:0] dout;
input [7:0] din;
input en,rst;
reg [7:0]dout;
always@(en or rst)
begin
if(rst)
dout<=8'h00;
else if(en)
PAGE NO.
94
dout<=din;
end
endmodule
TEST BENCH(VHDL) :
LIBRARY ieee;
ENTITY tb_latch_vhd IS
END tb_latch_vhd;
ARCHITECTURE behavior OF tb_latch_vhd IS
COMPONENT dlatch_reg
PORT(
en : IN std_logic;
rst : IN std_logic;
d : IN std_logic_vector(7 downto 0);
q : INOUT std_logic_vector(7 downto 0);
qbar : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL en : std_logic := '0';
SIGNAL d : std_logic_vector(7 downto 0) := (others=>'0');
--BiDirs
SIGNAL q : std_logic_vector(7 downto 0);
SIGNAL qbar : std_logic_vector(7 downto 0);
BEGIN
uut: dlatch_reg PORT MAP(
en => en,
rst => rst,
d => d,
q => q,
qbar => qbar
);
tb : PROCESS
BEGIN
wait for 100 ns;
END PROCESS;
en<='1','0' after 10 ns, '1' after 20 ns, '0' after 30 ns;
rst<='1','0' after 100 ps;
d<="01010101","11110000" after 10 ns,"11111111" after 20 ns,"00001111" after 30 ns;
PAGE NO.
95
END;
SIMULATION OUTPUT:
SYNTHESIS REPORT:
=========================================================================
Macro Statistics
# Latches
:2
8-bit latch
:2
=========================================================================
*
Final Report
*
=========================================================================
Selected Device : 3s400tq144-5
Number of Slices:
Number of GCLKs:
9 out of 3584 0%
16 out of 7168 0%
26 out of 97 26%
1 out of 8 12%
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
PAGE NO.
96
-----------------------------------+------------------------+-------+
en
| BUFGP
| 16 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of 8-bit register using flip flops and latches are verified by synthesizing and
EXPT NO: 08
DATE:27-2-08
PAGE NO.
97

DESIGN OF SHIFTERS
AIM:
To develop the source code for shifters unit by using VHDL/VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.
ALGORITHM:
LOGIC DIAGRAM :
SERIAL-IN SERIAL-OUT SHIFT REGISTER:
SERIAL IN PARALLEL OUT SHIFT REGISTER:
PARALLEL-IN PARELLEL-OUT SHIFT REGISTER:
PAGE NO.
98
PARALLEL-IN SERIAL-OUT SHIFT REGISTER:
VHDL SOURCE CODE

--Design
: SERIAL-IN SERIAL-OUT SHIFT REGISTER
--Description : To implement SERIAL-IN SERIAL-OUT SHIFT REGISTER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
LIBRARY ieee;
entity serinout is
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
end serinout;
architecture Behavioral of serinout is
signal x : std_logic_vector(7 downto 0);
begin
process (d, clk, rst)
begin
if (rst = '1') then
q <= 'X';
elsif (clk = '1' and clk'event) then
x(0) <= d;
x(1) <= x(0);
x(2) <= x(1);
x(3) <= x(2);
x(4) <= x(3);
x(5) <= x(4);
x(6) <= x(5);
x(7) <= x(6);
q <= x(7);
end if;
end process;
end Behavioral;
PAGE NO.
99
module siso(dout, din, clk, rst);

OUTPUT: dout;
input din;
input clk;
input rst;
reg dout;
reg[7:0]x;
always@(posedge(clk) or posedge(rst))
begin
if(rst==1)
dout=1'bz;
else
begin
x={x[6:0],din};
dout=x[7];
end
end
TEST BENCH(VHDL) :
LIBRARY ieee;
ENTITY sisi_test_vhd IS
END sisi_test_vhd;
ARCHITECTURE behavior OF sisi_test_vhd IS
COMPONENT serinout
PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic
);
END COMPONENT;
--Inputs
--OUTPUT:s
BEGIN
uut: serinout PORT MAP(
d => d,
clk => clk,
rst => rst,
q => q
PAGE NO.
100
);
tb : PROCESS
BEGIN
clk<='1';
wait for 1 ns;
clk<='0';
wait for 1 ns;
END PROCESS;
d<='1','0' after 2 ns,'1' after 3 ns,'0' after 4 ns;
END;
SIMULATION OUTPUT:
SYNTHESIS REPORT:
=========================================================================
Macro Statistics
# Registers
:1
1-bit register
:1
# Shift Registers
:1
8-bit shift register
:1
=========================================================================
*
Final Report
PAGE NO.
101

Number of Slices:
Number of GCLKs:
1 out of 3584 0%
2 out of 7168 0%
1 out of 7168 0%
4 out of 97 4%
1 out of 8 12%
=========================================================================
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|3 |
-----------------------------------+------------------------+-------+
TIMING REPORT
Timing Summary:
--------------Speed Grade: -5
SERIAL IN PARALLEL OUT SHIFT REGISTER
VHDL SOURCE CODE:
--Design
: SERIAL IN PARALLEL OUT SHIFT REGISTER
--Description : To implement SERIAL IN PARALLEL OUT SHIFT REGISTER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity sipo is
Port ( si : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic_vector(0 to 7));
end sipo;
architecture Behavioral of sipo is
begin
process (si,rst,clk)
begin
if(rst='1')then
PAGE NO.
102
q<="ZZZZZZZZ";
q(0)<=si;
q(1)<=q(0);
q(2)<=q(1);
q(3)<=q(2);
q(4)<=q(3);
q(5)<=q(4);
q(6)<=q(5);
q(7)<=q(6);
end if;
end process;
end Behavioral;
module sipo(dout, din, clk, rst);
OUTPUT: [7:0] dout;
input din;
input clk;
input rst;
reg [7:0]dout;
reg [7:0]x;
always @(posedge(clk) or posedge(rst))
begin
if(rst)
dout=8'hzz;
else
begin
x={x[6:0],din};
dout=x;
end
end
endmodule
TEST BENCH(VHDL) :
LIBRARY ieee;
ENTITY sipo_test_vhd IS
END sipo_test_vhd;
ARCHITECTURE behavior OF sipo_test_vhd IS
COMPONENT sipo
PORT(
si : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic_vector(0 to 7)
);
END COMPONENT;
PAGE NO.
103
--Inputs
SIGNAL si : std_logic := '0';
--BiDirs
SIGNAL q : std_logic_vector(0 to 7);
BEGIN
uut: sipo PORT MAP(
si => si,
clk => clk,
rst => rst,
q => q
);
tb : PROCESS
BEGIN
clk<='1';
wait for 1 ns;
clk<='0';
wait for 1 ns;
END PROCESS;
si<='1','0' after 2 ns,'1' after 3 ns,'0' after 4 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
104
SYNTHESIS REPORT:
=========================================================================
Macro Statistics
# Registers
:8
1-bit register
:8
# Tristates
:8
1-bit tristate buffer
:8
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of GCLKs:
5 out of 3584 0%
8 out of 7168 0%
11 out of 97 11%
1 out of 8 12%
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|8 |
-----------------------------------+------------------------+-------+
=========================================================================
TIMING REPORT
Timing Summary:
--------------Speed Grade: -5
PARALLEL-IN PARELLEL-OUT SHIFT REGISTER:
PAGE NO.
105
VHDL SOURCE CODE:

--Design
: PARALLEL-IN PARELLEL-OUT SHIFT REGISTER
--Description : To implement PARALLEL-IN PARELLEL-OUT SHIFT REGISTER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity pipo is
Port ( di : in std_logic_vector(0 to 7);
clk : in std_logic;
rst : in std_logic;
do : out std_logic_vector(0 to 7));
end pipo;
architecture Behavioral of pipo is
begin
process(clk,rst,di)
begin
if(rst='1')then
do<="00000000";
do(0)<=di(0);
do(1)<=di(1);
do(2)<=di(2);
do(3)<=di(3);
do(4)<=di(4);
do(5)<=di(5);
do(6)<=di(6);
do(7)<=di(7);
end if;
end process;
end Behavioral;
module pipo(dout, din, clk, rst);
OUTPUT: [7:0] dout;
input [7:0] din;
input clk;
input rst;
reg [7:0]dout;
always @(posedge(clk) or posedge(rst))
begin
if(rst==1)
dout=8'hzz;
else
dout=din;
end
endmodule
TEST BENCH(VHDL) :
PAGE NO.
106
LIBRARY ieee;
ENTITY pipo1_vhd IS
END pipo1_vhd;
ARCHITECTURE behavior OF pipo1_vhd IS
COMPONENT pipo
PORT(
di : IN std_logic_vector(0 to 7);
clk : IN std_logic;
rst : IN std_logic;
do : OUT std_logic_vector(0 to 7)
);
END COMPONENT;
--Inputs
SIGNAL di : std_logic_vector(0 to 7) := (others=>'0');
--OUTPUT:s
SIGNAL do : std_logic_vector(0 to 7);
BEGIN
uut: pipo PORT MAP(
di => di,
clk => clk,
rst => rst,
do => do
);
tb : PROCESS
BEGIN
clk<='1';
wait for 1 ns;
clk<='0';
wait for 1 ns;
END PROCESS;
di<="11111111","10011001" after 2 ns,"11011101" after 3 ns,"10001101" after 4 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
107
SYNTHESIS REPORT:
=========================================================================
Macro Statistics
# Registers
:8
1-bit register
:8
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of GCLKs:
5 out of 3584 0%
8 out of 7168 0%
18 out of 97 18%
1 out of 8 12%
=========================================================================
Clock Information:
------------------
PAGE NO.
108
-----------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|8 |
-----------------------------------+------------------------+-------+
TIMING REPORT
Timing Summary:
--------------Speed Grade: -5
PARALLEL-IN SERIAL-OUT SHIFT REGISTER
VHDL SOURCE CODE:
--Design
: PARALLEL-IN SERIAL-OUT SHIFT REGISTER
--Description : To implement PARALLEL-IN SERIAL-OUT SHIFT REGISTER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity piso is
Port ( clk,rst,load : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic);
end piso;
architecture Behavioral of piso is
begin
process (clk,rst,din,load)
variable x:std_logic_vector(7 downto 0);
begin
if(clk='1' and clk'event)then
if(rst='1')then
dout<='Z';
else
if(load='0')then
x:=din;
else
dout<=x(0);
x(0):=x(1);
x(1):=x(2);
x(2):=x(3);
x(3):=x(4);
PAGE NO.
109
x(4):=x(5);
x(5):=x(6);
x(6):=x(7);
x(7):='Z';
end if;
end if;
end if;
end process;
end Behavioral;
module piso(dout, din, load, clk, rst);
OUTPUT: dout;
input [7:0] din;
input load;
input clk;
input rst;
reg dout;
reg [8:0]x;
always
@(posedge(clk) or posedge(rst))
begin
if(rst)
dout=1'bz;
else
begin
if(load==1'b0)
x=din;
else
x={x[7:0],1'bz};
dout=x[8];
end
end
endmodule
TEST BENCH(VHDL) :
LIBRARY ieee;
ENTITY piso_test_vhd IS
END piso_test_vhd;
ARCHITECTURE behavior OF piso_test_vhd IS
COMPONENT piso
PORT(
clk : IN std_logic;
rst : IN std_logic;
load : IN std_logic;
PAGE NO.
110
din : IN std_logic_vector(7 downto 0);

dout : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL load : std_logic := '0';
SIGNAL din : std_logic_vector(7 downto 0) := (others=>'0');
--OUTPUT:s
SIGNAL dout : std_logic;
BEGIN
uut: piso PORT MAP(
clk => clk,
rst => rst,
load => load,
din => din,
dout => dout
);
tb : PROCESS
BEGIN
END PROCESS;
rst <='1','0' after 1 ps;
load<='0','1' after 10 ns,'0' after 50 ns,'1' after 60 ns;
din<="00010001","00001111" after 20 ns,"11110000" after 30 ns,"11111111" after 40 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
111
SYNTHESIS REPORT:
=========================================================================
Macro Statistics
# Registers
: 11
1-bit register
: 11
# Tristates
:2
1-bit tristate buffer
:2
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of GCLKs:
6 out of 3584 0%
11 out of 7168 0%
8 out of 7168 0%
12 out of 97 12%
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
PAGE NO.
112
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
| 11 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of 8-bit shift register are verified by synthesizing and simulating the VHDL
and VERILOG code.
EXPT NO: 09
DATE:10-3-08
PAGE NO.
113
SYNCHRONOUS AND ASYNCHRONOUS COUNTER

AIM:
To develop the source code for synchronous and asynchronous counter by using
VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA.
ALGORITHM:
LOGIC DIAGRAM:
SYNCHRONOUS COUNTER:
ASYNCHRONOUS COUNTER:
VHDL SOURCE CODE:
PAGE NO.
114
--Design
--Description
--Author
--Roll no
--Version
: SYNCHRONOUS COUNTER
: To implement SYNCHRONOUS COUNTER
: 28SVL132
: Xilinx- 7.1i
library IEEE;
entity syncount is
rst : in std_logic;
dout : inout std_logic_vector(3 downto 0));
end syncount;
architecture structural of syncount is
component tff2
rst : in std_logic;
t : in std_logic;
end component;
component andgate
Port ( p : in std_logic;
q : in std_logic;
r : out std_logic);
end component;
signal x1,x2:std_logic;
signal xdum:std_logic:='1';
signal x3,x4,x5,x6:std_logic:='Z';
begin
t1:tff2 port map(clk,rst,xdum,dout(0),x3);
t2:tff2 port map (clk,rst,dout(0),dout(1),x4);
a1:andgate port map(dout(0),dout(1),x1);
t3:tff2 port map(clk,rst,x1,dout(2),x5);
a2:andgate port map(x1,dout(2),x2);
t4:tff2 port map(clk,rst,x2,dout(3),x6);
end structural;
tff2:
library IEEE;
entity tff2 is
rst : in std_logic;
t : in std_logic;
end tff2;
PAGE NO.
115
architecture Behavioral of tff2 is

begin
process (clk,rst,t)
begin
if(rst='1')then
q<='0';
qbar<='1';
if(t='0')then
q<=q;
qbar<=qbar;
else
q<=not(q);
qbar<=not(qbar);
end if;
end if;
end process;
end Behavioral;
module synch_counter(dout, clk, rst);
OUTPUT: [3:0] dout;
input clk;
input rst;
wire x1,x2,x3,x4;
tff t1(dout[0],x1,1'b1,clk,rst);
tff t2(dout[1],x2,dout[0],clk,rst);
and a1(xin1,dout[0],dout[1]);
tff t3(dout[2],x3,xin1,clk,rst);
and a2(xin2,xin1,dout[2]);
tff t4(dout[3],x4,xin2,clk,rst);
endmodule
TEST BENCH(VHDL) :
LIBRARY ieee;
ENTITY synch_counter_vhd IS
END synch_counter_vhd;
ARCHITECTURE behavior OF synch_counter_vhd IS
COMPONENT syncount
PORT(
clk : IN std_logic;
rst : IN std_logic;
PAGE NO.
116
dout : INOUT std_logic_vector(3 downto 0)

);
END COMPONENT;
--Inputs
--BiDirs
SIGNAL dout : std_logic_vector(3 downto 0);
BEGIN
uut: syncount PORT MAP(
clk => clk,
rst => rst,
dout => dout
);
tb : PROCESS
BEGIN
END PROCESS;
rst<='1','0' after 50 ps;
END;
SIMULATION OUTPUT:
PAGE NO.
117
SYNTHESIS REPORT:
Macro Statistics
# Registers
:8
1-bit register
:8
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of GCLKs:
2 out of 3584 0%
4 out of 7168 0%
2 out of 7168 0%
6 out of 97 6%
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|4 |
-----------------------------------+------------------------+-------+
Timing Summary:
PAGE NO.
118
--------------Speed Grade: -5
Timing Detail:
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 3.388ns (frequency: 295.186MHz)
------------------------------------------------------------------------Delay:
Source:
t1/q (FF)
Destination:
t4/q (FF)
Source Clock:
clk rising
Destination Clock: clk rising
Data Path: t1/q to t4/q
Gate Net
Cell:in->out
---------------------------------------- -----------FDCE:C->Q
5 0.626 1.078 t1/q (t1/q)
LUT2:I0->O
1 0.479 0.681 a1/r1 (x1)
FDCE:CE
0.524
t3/q
---------------------------------------Total
(48.1% logic, 51.9% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
------------------------------------------------------------------------Offset:
Source:
t1/q (FF)
Destination:
dout<0> (PAD)
Source Clock:
clk rising
Data Path: t1/q to dout<0>
Gate Net
Cell:in->out
---------------------------------------- -----------FDCE:C->Q
5 0.626 0.783 t1/q (t1/q)
OBUF:I->O
4.909
dout_0_OBUF (dout<0>)
---------------------------------------Total
(87.6% logic, 12.4% route)
=========================================================================
CPU : 5.59 / 6.08 s | Elapsed : 6.00 / 6.00 s
PAGE NO.
119
PLACE AND ROUTE:

Constraints file: syncount.pcf.
C:/Xilinx.
"syncount" is an NCD, version 3.1, device xc3s400, package tq144, speed -5
Celsius)
Number of BUFGMUXs
Number of Slices
Number of SLICEMs
1 out of 8
6 out of 97
0 out of 6
12%
6%
0%
5 out of 3584 1%
0 out of 1792 0%

Starting Placer
Phase 1.1
Phase 1.1 (Checksum:9896a3) REAL time: 2 secs
Phase 2.31
Phase 3.2

Phase 4.3
Phase 5.5
Phase 6.8
.
Phase 6.8 (Checksum:98ac4b) REAL time: 2 secs
PAGE NO.
120
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs
Phase 8.18
Phase 9.5
Writing design to file syncount.ncd
Starting Router
REAL time: 3 secs
REAL time: 3 secs
REAL time: 3 secs
REAL time: 3 secs

**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
|
Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|
clk_BUFGP |
BUFGMUX7| No | 4 | 0.000 | 0.901
|
+---------------------+--------------+------+------+------------+-------------+
PAGE NO.
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Writing design to file syncount.ncd
PAR done!
ASYNCHRONOUS COUNTER
VHDL SOURCE CODE:
--Design
: ASYNCHRONOUS COUNTER
--Description : To implement ASYNCHRONOUS COUNTER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity asynch is
Port ( clk,rst : in std_logic;
dout : inout std_logic_vector(3 downto 0));
end asynch;
architecture Behavioral of asynch is
component tff2
rst : in std_logic;
t : in std_logic;
end component;
signal x1,x2,x3:std_logic;
signal x:std_logic:='Z';
begin
t1:tff2 port map(clk,rst,'1',dout(0),x1);
t2:tff2 port map(x1,rst,'1',dout(1),x2);
t3:tff2 port map(x2,rst,'1',dout(2),x3);
t4:tff2 port map(x3,rst,'1',dout(3),x);
end Behavioral;
module asynch_counter(dout, clk, rst);
OUTPUT: [3:0] dout;
input clk;
input rst;
wire x1,x2,x3,x4;
tff t1(dout[0],x1,1'b1,clk,rst);
tff t2(dout[1],x2,1'b1,x1,rst);
endmodule
TEST BENCH(VHDL):
PAGE NO.
122
LIBRARY ieee;
ENTITY asy_test_vhd IS
END asy_test_vhd;
ARCHITECTURE behavior OF asy_test_vhd IS
COMPONENT asynch
PORT(
clk : IN std_logic;
rst : IN std_logic;
dout : INOUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
--BiDirs
SIGNAL dout : std_logic_vector(3 downto 0);
BEGIN
uut: asynch PORT MAP(
clk => clk,
rst => rst,
dout => dout
);
tb : PROCESS
BEGIN
END PROCESS;
rst<='1','0' after 500 ps;
END;
SIMULATION OUTPUT:
PAGE NO.
123
SYNTHESIS REPORT:
Macro Statistics
# Counters
:1
8-bit updown counter
:1
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
4 out of 3584 0%
8 out of 7168 0%
8 out of 7168 0%
12 out of 97 12%
Number of GCLKs:
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|8 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
Timing Detail:
=========================================================================
PAGE NO.
124
Timing constraint: Default period analysis for Clock 'clk'

Clock period: 2.733ns (frequency: 365.925MHz)
------------------------------------------------------------------------Delay:
Source:
t1/qbar (FF)
Destination:
t1/qbar (FF)
Source Clock:
clk rising
Destination Clock: clk rising
Data Path: t1/qbar to t1/qbar
Gate Net
Cell:in->out
---------------------------------------- -----------FDPE:C->Q
3 0.626 0.771 t1/qbar (t1/qbar)
INV:I->O
1 0.479 0.681 t1/_n00031_INV_0 (t1/_n0003)
FDPE:D
0.176
t1/qbar
---------------------------------------Total
(46.9% logic, 53.1% route)
PLACE AND ROUTE:
Constraints file: asynch.pcf.
C:/Xilinx.
"asynch" is an NCD, version 3.1, device xc3s400, package tq144, speed -5
Celsius)
Number of BUFGMUXs
Number of Slices
Number of SLICEMs
1 out of 8
6 out of 97
0 out of 6
12%
6%
0%
7 out of 3584 1%
0 out of 1792 0%

Starting Placer
Phase 1.1
Phase 1.1 (Checksum:9896a9) REAL time: 1 secs
Phase 2.31
Phase 3.2
Phase 4.3
PAGE NO.
125

Phase 5.5
Phase 6.8
.Phase 6.8 (Checksum:98ac4b) REAL time: 1 secs
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs
Phase 8.18
Phase 9.5
Writing design to file asynch.ncd
Starting Router
REAL time: 2 secs
REAL time: 2 secs
REAL time: 2 secs
REAL time: 2 secs

**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
|
Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|
clk_BUFGP |
BUFGMUX7| No | 2 | 0.000 | 0.901
|
+---------------------+--------------+------+------+------------+-------------+
|
t1/qbar |
Local|
| 3 | 0.284 | 1.230
|
+---------------------+--------------+------+------+------------+-------------+
|
t2/qbar |
Local|
| 3 | 0.000 | 1.424
|
+---------------------+--------------+------+------+------------+-------------+
|
t3/qbar |
Local|
| 2 | 0.000 | 1.576
|
+---------------------+--------------+------+------+------------+-------------+
PAGE NO.
126

Writing design to file asynch.ncd
PAR done!
RESULT:
Thus the OUTPUT:s of Synchronous and Asynchronous counter are verified by synthesizing and
EXPT NO: 10
DATE:13-3-08
PAGE NO.
127
DESIGN OF MOORE AND MELAY FSM

AIM:
To develop the source code for moore and melay FSM by using VHDL/VERILOG and obtain the
ALGORITHM:
LOGIC DIAGRAM:
MOORE FSM:
``````````
MEALY FSM:
MOORE FSM
VHDL SOUCE CODE:
--Design
: Moore fsm
--Description : To implement Moore fsm
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
PAGE NO.
128
library IEEE;
entity moore is
clk : in std_logic;
z : out std_logic);
end moore;
architecture Behavioral of moore is
type state_type is (st0,st1,st2,st3);
signal moore_state:state_type;
begin
process(clk)
begin
if(clk='0')then
case moore_state is
when st0=>z<='1';
if(a='1')then
moore_state<=st2;
end if;
when st1=>
z<='0';
if(a='1')then
moore_state<=st3;
end if;
when st2=>z<='0';
if(a='0')then
moore_state<=st1;
else
moore_state<=st3;
end if;
when st3=>z<='1';
if(a='1')then
moore_state<=st0;
end if;
end case;
end if;
end process;
end Behavioral;
module moore_fsm(z, a, clk);
OUTPUT: z;
input a;
input clk;
reg z;
parameter st0=0,st1=1,st2=2,st3=3;
reg [0:1]moore_state;
initial
begin
moore_state=st0;
PAGE NO.
129
end
always
@(posedge(clk))
case (moore_state)
st0:
begin
z=1;
if(a)
moore_state=st2;
end
st1:
begin
z=0;
if(a)
moore_state=st3;
end
st2:
begin
z=0;
if(~a)
moore_state=st1;
else
moore_state=st3;
end
st3:
begin
z=1;
if(a)
moore_state=st0;
end
endcase
endmodule
TEST BENCH(VHDL) :
LIBRARY ieee;
ENTITY moore_fsm_vhd IS
END moore_fsm_vhd;
ARCHITECTURE behavior OF moore_fsm_vhd IS
COMPONENT moore
PORT(
a : IN std_logic;
clk : IN std_logic;
z : OUT std_logic
);
END COMPONENT;
--Inputs
--OUTPUT:s
BEGIN
PAGE NO.
130

uut: moore PORT MAP(
a => a,
clk => clk,
z => z
);
tb : PROCESS
begin
clk<='1';
wait for 1 ns;
clk<='0';
wait for 1 ns;
END PROCESS;
--rst<='1','0' after 1 ns;
a<='1','0' after 2 ns,'1' after 3 ns,'0' after 4 ns;
END;
SIMULATION OUTPUT:
SYNTHESIS REPORT:
PAGE NO.
131
=========================================================================
Macro Statistics
# Latches
:2
1-bit latch
:1
4-bit latch
:1
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of GCLKs:
3 out of 3584 0%
5 out of 7168 0%
5 out of 7168 0%
3 out of 97 3%
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|5 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
MEALY FSM
VHDL SOUCE CODE:
--Design
: melay fsm
--Description : To implement melay fsm
--Author
:CH UDAY KUMAR REDDY
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity mealyfsm is
clk : in std_logic;
PAGE NO.
132
z : out std_logic);
end mealyfsm;
architecture Behavioral of mealyfsm is
type mealy_type is(st0,st1,st2,st3);
signal p_state,n_state:mealy_type;
begin
seq_part:process(clk)
begin
if(clk='1')then
p_state<=n_state;
end if;
end process seq_part;
comb_part:process(p_state,a)
begin
case p_state is
when st0=>
if a='1' then
z<='1';n_state<=st3;
else
z<='0';
end if;
when st1=>
if(a='1')then
else
z<='1';
end if;
when st2=>
if(a='0') then
z<='0';
else
end if;
when st3=>
z<='0';
if(a='0')then
n_state<=st2;
else
n_state<=st1;
end if;
end case;
end process comb_part;
end Behavioral;
module mealy_fsm(z, a, clk);
OUTPUT: z;
input a;
input clk;
reg z;
parameter st0=0,st1=1,st2=2,st3=3;
reg [1:2]p_state,n_state;
initial
begin
n_state=st0;
end
PAGE NO.
133
always
@(posedge(clk))
p_state=n_state;
always
@(p_state or a) begin:comb_part
case(p_state)
st0:
if(a)
begin
z=1;
n_state=st3;
end
else
z=0;
st1:
if(a)
begin
z=0;
n_state=st0;
end
else
z=1;
st2:
if(~a)
z=0;
else
begin
z=1;
n_state=st1;
end
st3:
begin
z=0;
if(~a)
n_state=st2;
else
n_state=st1;
end
endcase
end
endmodule
TEST BENCH(VHDL) :
LIBRARY ieee;
ENTITY mealy_test_vhd IS
END mealy_test_vhd;
ARCHITECTURE behavior OF mealy_test_vhd IS
COMPONENT mealyfsm
PORT(
PAGE NO.
134
a : IN std_logic;
clk : IN std_logic;
z : OUT std_logic
);
END COMPONENT;
--Inputs
--OUTPUT:s
BEGIN
uut: mealyfsm PORT MAP(
a => a,
clk => clk,
z => z
);
tb : PROCESS
BEGIN
clk<='1';
wait for 1 ns;
clk<='0';
wait for 1 ns;
END PROCESS;
a<='1','0' after 2 ns,'1' after 3 ns,'0' after 4 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
135
SYNTHESIS REPORT:
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
5 out of 3584 0%
8 out of 7168 0%
6 out of 7168 0%
3 out of 97 3%
Number of GCLKs:
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|4 |
_n0008(_n00081:O)
| NONE(*)(n_state_3) | 4 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of Moore and Mealy fsm are verified by synthesizing and simulating the
EXPT NO: 11
DATE:14-3-08
PAGE NO.
136
STATIC AND ROLLING DISPLAY

AIM:
To develop the source code Static Display by using VHDL/VERILOG and Obtained the
ALGORITHM:
VHDL SOUCE CODE:
--Design
: Static and Rolling Display
--Description : To implement Static Display
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity static_rolling is
rst : in std_logic;
a1,a2,a3 : in std_logic_vector(7 downto 0);
stat_roll : in std_logic;
a_out : out std_logic_vector(23 downto 0));
end static_rolling;
architecture Behavioral of static_rolling is
signal count:integer;
begin
process(clk,rst,a1,a2,a3,count)
begin
if(clk='1' and clk'event) then
if(rst='1')then
a_out<=(others=>'0');
count<=0;
else
if(stat_roll='0')then
a_out<=a1 & a2 & a3;
else
count<=count+1;
if(count=3)then
count<=0;
end if;
PAGE NO.
137
case count is
when 0=>
a_out<=a1&a2&a3;
when 1=>
a_out<=a2&a3&a1;
when 2=>
a_out<=a3&a1&a2;
when others=>null;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
module stat_rolling(a_out, clk, rst, a_in1, a_in2, a_in3, stat_roll);
OUTPUT: [23:0] a_out;
input clk;
input rst;
input [7:0] a_in1;
input [7:0] a_in2;
input [7:0] a_in3;
input stat_roll;
reg [23:0] a_out;
reg x;
integer count=0;
begin
if(rst)
begin
a_out=32'd0;
x=1'b0;
end
else
begin
if(stat_roll)
begin
if(x==1'b0)
a_out={a_in1,a_in2,a_in3};
else
a_out=a_out;
end
else
begin
x=1'b1;
count=count+1;
if(count==3)
count=0;
case(count)
0:a_out={a_in1,a_in2,a_in3};
default:a_out={a_in1,a_in2,a_in3};
PAGE NO.
138
endcase
end
end
end
endmodule
TEST BENCH (VERILOG):
module static_test_v;
// Inputs
reg clk;
reg rst;
reg [7:0] a_in1;
reg [7:0] a_in2;
reg [7:0] a_in3;
reg stat_roll;
// OUTPUT:s
wire [23:0] a_out;
// Instantiate the Unit Under Test (UUT)
stat_rolling uut (
.a_out(a_out),
.clk(clk),
.rst(rst),
.a_in1(a_in1),
.a_in2(a_in2),
.a_in3(a_in3),
.stat_roll(stat_roll)
);
always
#5 clk=~clk;
initial
begin
// Initialize Inputs
clk = 1'b0;rst=1'b1;a_in1=8'haa;a_in2=8'hff;a_in3=8'h00;stat_roll=1'b1;
#15 rst = 1'b0;
#25 stat_roll = 1'b0;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule
SIMULATION OUTPUT:
PAGE NO.
139
SYNTHESIS REPORT:
-------------------------Macro Statistics
# Counters
:1
32-bit up counter
:1
# Registers
:1
24-bit register
:1
# Multiplexers
:2
24-bit 4-to-1 multiplexer
:2
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of GCLKs:
66 out of 3584 1%
58 out of 7168 0%
104 out of 7168 1%
51 out of 97 52%
1 out of 8 12%
PAGE NO.
140
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
| 58 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of Static and Rolling display are verified by synthesizing and simulating the
EXPT NO: 12
DATE:17-3-08
PAGE NO.
141
FREQUENCY DIVIDER
AIM:
To develop the source code Frequency divider by using VHDL/VERILOG and Obtained the
ALGORITHM:
LOGIC DIAGRAM:
VHDL SOURCE CODE:

--Design
: FREQUENCY DIVIDER
--Description : To implement FREQUENCY DIVIDER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity freqdiv1 is
Port (x: in integer range 1 to 31;
clk,rst : in std_logic;
freq_out : inout std_logic);
end freqdiv1;
architecture Behavioral of freqdiv1 is
signal count: integer range 1 to 31:=1;
begin
process(clk,rst,x,count,freq_out)
begin
if(clk='1' and clk'event) then
if(rst='1') then
PAGE NO.
142
freq_out<=clk;
else
if(count>1) then
count<=count-1;
else
count<=x;
freq_out<=not(freq_out);
end if;
end if;
end if;
end process;
end Behavioral;
module freq_div(freq_out, x, clk, rst);
OUTPUT: freq_out;
input [3:0] x;
input clk;
input rst;
reg freq_out;
integer count=1;
begin
if(rst)
freq_out=clk;
else
if(count>1)
count=count-1'b1;
else
begin
count=x;
freq_out=~freq_out;
end
end
endmodule
TEST BENCH(VERILOG):
module freqdiv_test_v;
// Inputs
reg [3:0] x;
reg clk;
reg rst;
// OUTPUT:s
wire freq_out;
freq_div uut (
.freq_out(freq_out),
.x(x),
.clk(clk),
PAGE NO.
143
.rst(rst)
);
always
#5clk=~clk;
initial begin
rst=1'b1;x=4'd5;clk=1'b0;
#10 rst=1'b0;
#200 x=4'd2;
#100 x = 4'd3;
end
endmodule
SIMULATION OUTPUT:
SYNTHESIS REPORT:
PAGE NO.
144
-------------------------Macro Statistics :
# Registers
#
1-bit register
# Counters
#
31-bit up counter
# Adders/Subtractors
#
31-bit adder
:1
:1
:1
:1
:1
:1
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of GCLKs:
44 out of 3584 1%
32 out of 7168 0%
83 out of 7168 1%
3 out of 97 3%
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
| 32 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT: of Frequency Divider are verified by synthesizing and simulating the VHDL
and VERILOG code.
EXPT NO: 13
DATE:18-3-08
PAGE NO.
145
DESIGN OF ARITHMATIC AND LOGIC UNIT

AIM:
To develop the source code for arithmetic and logic unit by using VHDL/VERILOG and obtain
the simulation, synthesis, place and route and implement into FPGA.
ALGORITHM:
LOGIC DIAGRAM:
TRUTH TABLE:
VHDL SOURCE CODE:
PAGE NO.
146
--Design
--Description
--Author
--Roll no
--Version
: ARITHMATIC AND LOGIC UNIT

: To implement ARITHMATIC AND LOGIC UNIT
: 28SVL132
: Xilinx- 7.1i
library IEEE;
entity alu is
cin : in std_logic;
sel : in std_logic_vector(3 downto 0);
y : out std_logic_vector(7 downto 0));
end alu;
architecture Behavioral of alu is
component arith_unit
port(a,b:in std_logic_vector(7 downto 0);
cin:in std_logic;
sel:in std_logic_vector(2 downto 0);
x: out std_logic_vector(7 downto 0));
end component;
component logic_unit
sel:in std_logic_vector(2 downto 0);
x:out std_logic_vector(7 downto 0));
end component;
component mux1
sel:in std_logic;
x:out std_logic_vector(7 downto 0));
end component;
signal x1,x2:std_logic_vector(7 downto 0);
begin
u1:arith_unit port map(a,b,cin,sel(2 downto 0),x1);
u2:logic_unit port map(a,b,sel(2 downto 0),x2);
u3:mux1 port map(x1,x2,sel(3),y);
end Behavioral;
ARITHMATIC UNIT VHDL CODE:
library IEEE;
entity arith_unit is
cin : in std_logic;
x : out std_logic_vector(7 downto 0));
PAGE NO.
147
end arith_unit;
architecture Behavioral of arith_unit is
---signal arith_logic:std_logic_vector(7 downto 0);
begin
with sel select
x<= a when "000",
a+1 when "001",
a-1 when "010",
b when "011",
b+1 when "100",
b-1 when "101",
a+b when "110",
a+b+cin when others;
end Behavioral;
LOGIC UNIT:
library IEEE;
entity logic_unit is
x : out std_logic_vector(7 downto 0));
end logic_unit;
architecture Behavioral of logic_unit is
begin
with sel select
x<= not(a) when "000",
not(b) when "001",
a and b when "010",
a or b when "011",
a nand b when "100",
a nor b when "101",
a xor b when "110",
a nor b when others;
end Behavioral;
module alu(y, a,b,cin, s);
OUTPUT: [7:0] y;
input [7:0] a,b;
input cin;
input [3:0] s;
reg [7:0]y;
always
@(a,b,s)
begin
case(s)
4'b0000: y=a;
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148
4'b0001: y=a+1;
4'b0010: y=a-1;
4'b0011: y=b;
4'b0100: y=b+1;
4'b0101: y=b-1;
4'b0110: y=a+b;
4'b0111: y=a+b+cin;
4'b1000: y=~a;
4'b1001: y=~b;
4'b1010: y=a&b;
4'b1011: y=a|b;
4'b1100: y=~(a&b);
4'b1101: y=~(a|b);
4'b1110: y=a^b;
4'b1111: y=~(a^b);
endcase
end
endmodule
module alu_test_v;
// Inputs
reg [7:0] a;
reg [7:0] b;
reg cin;
reg [3:0] s;
// OUTPUT:s
wire [7:0] y;
alu uut (
.y(y),
.a(a),
.b(b),
.cin(cin),
.s(s)
);
initial
begin
cin=1'b0;a=8'h00;b=8'hff;s=4'b0000;
#5 s=4'b0001;
#5 s=4'b0010;
#5 s=4'b0001;
#5 s=4'b0111;
#5 s=4'b1001;
end
endmodule
SIMULATION OUTPUT:
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149
SYNTHESIS REPORT:
# Multiplexers
:2
#
8-bit 8-to-1 multiplexer : 2
:6
#
8-bit adder
:3
#
8-bit adder carry in
:1
#
8-bit subtractor
:2
=========================================================================
*
Final Report
*
=========================================================================
=========================================================================
Number of Slices:
57 out of 3584
1%
PAGE NO.
150

88 out of 7168 1%
29 out of 97 29%
=========================================================================
TIMING REPORT
Clock Information:
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of Arithmetic Logic Unit are verified by synthesizing and simulating the
EXPT NO: 14
DATE:19-3-08
PAGE NO.
151

BARREL SHIFTER
AIM:
To develop the source code for barrel shifter by using VHDL/VERILOG and obtain the
ALGORITHM:
LOGICAL DIAGRAM:
VHDL SOURCE CODE:

--Design
: BARREL SHIFTER
--Description : To implement BARREL SHIFTER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
entity barrel is
generic (n : positive := 4);
port( data : in std_logic_vector(n-1 downto 0);
selekt : in integer range 0 to n-1;
barr : out std_logic_vector (n-1 downto 0));
PAGE NO.
152
end barrel;
architecture Behavioral of barrel is
begin
process(selekt,data)
variable var_buf:std_logic_vector(n-1 downto 0);
begin
var_buf:=data;
for k in 1 to selekt loop
var_buf:= var_buf(n-2 downto 0)& var_buf(n-1);
end loop;
barr <= var_buf;
end process;
end Behavioral;
module barrel(aout, clk, rst, a, sft, lr);
input clk, rst, lr;
input [7:0]a;
input [2 :0]sft;
OUTPUT: [7:0]aout;
reg [7:0]aout;
always @ (posedge clk) begin
if (rst )
aout = 8'd0;
else
begin
if (lr)
aout = a << sft;
else
aout = a >> sft;
end
end
endmodule
module barr_test_v;
// Inputs
reg clk;
reg rst;
reg [7:0] a;
reg [2:0] sft;
reg lr;
// OUTPUT:s
wire [7:0] a_out;
barr_shift uut (
.a_out(a_out),
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153
.clk(clk),
.rst(rst),
.a(a),
.sft(sft),
.lr(lr)
);
always
#5clk=~clk;
initial
begin
a=8'h10;
clk =1'b0;rst = 1'b1;sft = 3'd3;lr=1'b0;
#5 rst=1'b0;
#20 sft=3'd5;
#10 lr=1'b1;
#20 sft=3'd1;
end
endmodule
SIMULATION OUTPUT:
PAGE NO.
154
SYNTHESIS REPORT:
# Registers
:1
#
8-bit register
:1
# Logic shifters
:2
#
8-bit shifter logical left : 1
#
8-bit shifter logical right : 1
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of GCLKs:
24 out of 3584 0%
8 out of 7168 0%
44 out of 7168 0%
22 out of 97 22%
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
-----------------------------------+------------------------+-------+
PAGE NO.
155
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|8 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of Barrel Shifter are verified by synthesizing and simulating the VHDL and
VERILOG code.
EXPT NO: 15
DATE:20-3-08
PAGE NO.
156
TRAFFIC LIGHT CONTROLLER

AIM:
To develop the source code for traffic light controller by using VHDL/VEILOG and obtain the
simulation, place and route and implementation into FPGA.
ALGORITHM:
Step4: Check the syntax and debug the errors if found, obtain the SYNTHESIS REPORT.
Step6: Write all the possible combinations of input using test bench.
LOGIC DIAGRAM:
VHDL SOURCE CODE:

--Design
: TRAFFIC LIGHT CONTROLLER
--Description : To implement TRAFFIC LIGHT CONTROLLER
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
PAGE NO.
157
entity tlc is
port(clk,rst : in std_logic;
gr1, gr2, gr3 : out std_logic_vector(1 downto 0);
rd1, rd2, rd3, yl1, yl2, yl3 : out std_logic);
end tlc;
architecture Behavioral of tlc is
type state is (s1, s2, s3);
signal prstate : state;
signal count : integer := 0;
begin
process (clk, rst)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
prstate <= s1;
else
case prstate is
when s1 =>
if (count =4) then
yl1 <= '1'; yl2 <= '0'; yl3 <= '0';
count <= 0;
prstate <= s2;
else
gr1 <= "11"; gr2 <= "00"; gr3 <= "10";
rd1 <= '0'; rd2 <= '1'; rd3 <= '1';
yl1 <= '0'; yl2 <= '0'; yl3 <= '0';
prstate <= s1;
count <= count +1;
end if;
when s2 =>
if (count =4) then
yl1 <= '0'; yl2 <= '1'; yl3 <= '0';
count <= 0;
prstate <= s3;
else
gr1 <= "10"; gr2 <= "11"; gr3 <= "00";
rd1 <= '1'; rd2 <= '0'; rd3 <= '1';
yl1 <= '0'; yl2 <= '0'; yl3 <= '0';
prstate <= s2;
count <= count +1;
end if;
when s3 =>
if (count =4) then
yl1 <= '0'; yl2 <= '0'; yl3 <= '1';
count <= 0;
prstate <= s1;
else
gr1 <= "00"; gr2 <= "01"; gr3 <= "11";
rd1 <= '1'; rd2 <= '1'; rd3 <= '0';
yl1 <= '0'; yl2 <= '0'; yl3 <= '0';
prstate <= s3;
count <= count +1;
end if;
end case;
PAGE NO.
158
end if;
end if;
end process;
end Behavioral;
module traffic(clk, rst, gr1, gr2, gr3, rd1, rd2, rd3, yl1, yl2, yl3);
input clk, rst;
OUTPUT:[1:0] gr1, gr2, gr3;
OUTPUT: rd1, rd2, rd3, yl1, yl2, yl3;
reg [1:0] gr1, gr2, gr3;
reg rd1, rd2, rd3, yl1, yl2, yl3;
parameter s1=0, s2=1, s3=2;
reg[0:1] ps;
reg [2:0]count ;
initial
begin ps=s1;
end
always @ ( clk or rst) begin
if ( rst == 1'b1)
ps = s1;
else
case (ps)
s1 :
if ( count ==3'b100 )
begin
yl1 = 1'b1; yl2 = 1'b0; yl3 = 1'b0;
count = 3'b000;
ps = s2;
end
else
begin
gr1 = 2'b11; gr2 = 2'b00; gr3 = 2'b10;
rd1 = 1'b0; rd2 = 1'b1; rd3 = 1'b1;
yl1 = 1'b0; yl2 = 1'b0; yl3 = 1'b0;
ps = s1;
count = count + 3'b001;
end
s2 :
if ( count ==3'b100 )
begin
yl1 = 1'b0; yl2 = 1'b1; yl3 = 1'b0;
count = 3'b000;
ps = s3;
end
else
begin
gr1 = 2'b10; gr2 = 2'b11; gr3 = 2'b00;
rd1 = 1'b1; rd2 = 1'b0; rd3 = 1'b1;
yl1 = 1'b0; yl2 = 1'b0; yl3 = 1'b0;
ps = s2;
end
PAGE NO.
159
s3 :
if ( count ==3'b100 )
begin
yl1 = 1'b0; yl2 = 1'b0; yl3 = 1'b1;
count = 3'b000;
ps = s1;
end
else
begin
gr1 = 2'b00; gr2 = 2'b01; gr3 = 2'b11;
rd1 = 1'b1; rd2 = 1'b1; rd3 = 1'b0;
yl1 = 1'b0; yl2 = 1'b0; yl3 = 1'b0;
ps = s3;
end
endcase
end
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
ENTITY traffic_test_vhd IS
END traffic_test_vhd;
ARCHITECTURE behavior OF traffic_test_vhd IS
COMPONENT traffic_lightcontr
PORT(
clk : IN std_logic;
rst : IN std_logic;
gr1 : OUT std_logic_vector(1 downto 0);
rd1 : OUT std_logic;
yl1 : OUT std_logic;
yl2 : OUT std_logic;
yl3 : OUT std_logic
);
END COMPONENT;
--Inputs
--OUTPUT:s
SIGNAL gr1 : std_logic_vector(1 downto 0);
SIGNAL gr2 : std_logic_vector(1 downto 0);
PAGE NO.
160
SIGNAL gr3 :
SIGNAL rd1 :
SIGNAL rd2 :
SIGNAL rd3 :
SIGNAL yl1 :
SIGNAL yl2 :
SIGNAL yl3 :
std_logic_vector(1 downto 0);

std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
BEGIN
uut: traffic_lightcontr PORT MAP(
clk => clk,
rst => rst,
gr1 => gr1,
gr2 => gr2,
gr3 => gr3,
rd1 => rd1,
rd2 => rd2,
rd3 => rd3,
yl1 => yl1,
yl2 => yl2,
yl3 => yl3
);
tb : PROCESS
BEGIN
clk<='1'; wait for 5 ns;
clk<='0'; wait for 5 ns;
END PROCESS;
END;
SIMULATION OUTPUT:
PAGE NO.
161
SYNTHESIS REPORT:
-------------------------Macro Statistics
# FSMs
:1
:1
33-bit adder
:1
# Registers
: 12
1-bit register
:8
2-bit register
:3
32-bit register
:1
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of GCLKs:
43 out of 3584 1%
46 out of 7168 0%
61 out of 7168 0%
14 out of 97 14%
1 out of 8 12%
=========================================================================
TIMING REPORT
PAGE NO.
162
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
| 46 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of Traffic Light Controller are verified by synthesizing and simulating the
EXPT NO: 16
DATE:7-4-08
PAGE NO.
163
DESIGN OF MEMORIES
AIM:
To develop the source code for memories by using VHDL/VEILOG and obtain the simulation,
place and route and implementation into FPGA.
ALGORITHM:
BLOCK DIAGRAM:
ROM
VHDL SOURCE CODE:

--Design
: ROM
--Description : To implement ROM
--Author
--Roll no
: 28SVL132
--Version
: Xilinx- 7.1i
library IEEE;
PAGE NO.
164
entity rom is
generic(bits:integer:=8;
words:integer:=8);
Port ( addr:in integer range 0 to words-1;
data : out std_logic_vector(bits-1 downto 0));
end rom;
architecture Behavioral of rom is
type vector_array is array(0 to words-1) of std_logic_vector(bits-1 downto 0);
constant memory:vector_array:=("00000000",
"00000010",
"00000100",
"00001000",
"00010000",
"00100000",
"01000000",
"10000000");
begin
data<=memory(addr);
end Behavioral;
module rom(data_out, address);
input [7:0] address;
OUTPUT: [7:0] data_out;
reg [7:0]data_out;
reg [0:7]mem[0:7];
initial
begin
mem[0]=8'b00000000;
mem[1]=8'b00000010;
mem[2]=8'b00000100;
mem[3]=8'b00001000;
mem[4]=8'b00010000;
mem[5]=8'b00100000;
mem[6]=8'b01000000;
mem[7]=8'b10000000;
end
always@(address)
begin
data_out=mem[address];
end
endmodule
PAGE NO.
165
SIMULATION OUTPUT:
SYNTHESIS REPORT:
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
4 out of 3584 0%
7 out of 7168 0%
11 out of 97 11%
=========================================================================
TIMING REPORT
Clock Information:
PAGE NO.
166
Timing Summary:
--------------Speed Grade: -5
RAM
VHDL SOURCE CODE:
--Design
--Description
--Author
--Roll no
--Version
: RAM
: To implement RAM
:CH UDAY KUMAR REDDY
: 28SVL132
: Xilinx- 7.1i
library IEEE;
entity ram is
generic ( bits : integer := 8; words : integer := 16);
port (addr : in integer range 0 to (words-1); wr_ena, clk : in std_logic;
datain : in std_logic_vector(bits-1 downto 0);
dataout : out std_logic_vector(bits-1 downto 0));
end ram;
architecture Behavioral of ram is
type vectorarray is array(0 to words-1) of std_logic_vector(bits-1 downto 0);
signal memory : vectorarray;
begin
process(clk, wr_ena)
begin
if (clk = '1' and clk'event) then
if(wr_ena = '1') then
memory(addr) <= datain;
else
dataout <= memory(addr);
end if;
end if;
end process;
end Behavioral;
PAGE NO.
167
module ram(clk, wr_en, datain, dataout, addr);

input clk;
input wr_en;
input [0:7]datain;
input [0:4]addr;
OUTPUT: [0:7]dataout;
reg [0:7]dataout;
reg [0:7]mem[0:31];
always @ (posedge clk, wr_en, datain, addr)
if(clk)
begin
if (wr_en)
mem[addr] = datain;
else
dataout = mem[addr];
end
endmodule
module ram_testb_v;
// Inputs
reg clk;
reg [7:0] data_in;
reg [4:0] address;
reg wr_rd;
// OUTPUT:s
wire [7:0] data_out;
ram uut (
.data_out(data_out),
.clk(clk),
.data_in(data_in),
.address(address),
.wr_rd(wr_rd));
always
#5 clk=~clk;
initial
begin
clk = 1'b1;
data_in = 8'ha0;
address = 5'd0;
wr_rd = 1'b1;
#10 wr_rd=1'b0;
end
endmodule
PAGE NO.
168
SIMULATION OUTPUT:
SYNTHESIS REPORT:
=========================================================================
*
Final Report
*
=========================================================================
Number of BRAMs:
Number of GCLKs:
22 out of 97 22%
1 out of 16 6%
1 out of 8 12%
PAGE NO.
169
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
|1 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of ROM and RAM are verified by synthesizing and simulating the VHDL
and VERILOG code.
EXPT NO: 17
DATE:9-4-08
PAGE NO.
170
DESIGN OF MAC UNIT

AIM
To develop the source code for MAC unit by using VHDL/VEILOG and obtain the simulation,
place and route and implementation into FPGA.
ALGORITHM:
BLOCK DIAGRAM:
VHDL SOURCE CODE:

--Design
--Description
--Author
--Roll no
--Version
: MAC UNIT
: To implement MAC UNIT
: 28SVL132
: Xilinx- 7.1i
library IEEE;
entity mac is
port (a, b : in std_logic_vector(7 downto 0);
clk, rst : in std_logic;
acc : out std_logic_vector(15 downto 0));
end mac;
PAGE NO.
171
architecture Behavioral of mac is

signal prod, reg : std_logic_vector(15 downto 0);
begin
process (a, b, rst, clk)
variable sum : std_logic_vector(15 downto 0);
begin
prod <= a * b;
sum := prod + reg;
if (rst = '1') then
reg <= (others => '0');
elsif (clk ='1' and clk'event) then
reg <= sum;
end if;
acc <= reg;
end process;
end Behavioral;
module mac(acc, clk, rst, a,b);
OUTPUT: [25:0]acc;
input clk;
input rst;
input [3:0]a,b;
reg [25:0]pd;
reg [25:0]adder;
reg [25:0]acc;
always@(posedge(clk))
begin
if(rst==1)
adder=4'b0000;
else
begin
pd=a*b;
adder=adder+pd;
end
acc=adder;
end
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
ENTITY mac_test_vhd IS
END mac_test_vhd;
ARCHITECTURE behavior OF mac_test_vhd IS
COMPONENT mac
PAGE NO.
172
PORT(
clk : IN std_logic;
rst : IN std_logic;
acc : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
--OUTPUT:s
SIGNAL acc : std_logic_vector(15 downto 0);
BEGIN
uut: mac PORT MAP(
a => a,
b => b,
clk => clk,
rst => rst,
acc => acc
);
tb : PROCESS
BEGIN
clk<='1';wait for 5 ns;
clk<='0';wait for 5 ns;
END PROCESS;
a<="11001010","10101010" after 20 ns;
b<="11001011","11111111" after 40 ns;
END;
SIMULATION OUTPUT:
PAGE NO.
173
SYNTHESIS REPORT:
=========================================================================
Macro Statistics
# Multipliers
:1
8x8-bit multiplier
:1
# Accumulators
:1
16-bit up accumulator
:1
=========================================================================
*
Final Report
*
=========================================================================
Number of Slices:
Number of MULT18X18s:
Number of GCLKs:
8 out of 3584 0%
16 out of 7168 0%
16 out of 7168 0%
34 out of 97 35%
1 out of 16 6%
1 out of 8 12%
=========================================================================
TIMING REPORT
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
-----------------------------------+------------------------+-------+
clk
| BUFGP
| 16 |
-----------------------------------+------------------------+-------+
PAGE NO.
174
Timing Summary:
--------------Speed Grade: -5
RESULT:
Thus the OUTPUT:s of Multiplication and Accumulator are verified by synthesizing and
PAGE NO.
175

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SATHYABAMA UNIVERSITY

DEPARTMENT OF VLSI DESIGN

VLSI DESIGN LABORATORY

DEPARTMENT OF VLSI DESIGN

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DEPARTMENT OF VLSI DESIGN

SYNTHESIS RTL SCHEMATIC:

VLSI DESIGN LABORATORY

DEPARTMENT OF VLSI DESIGN

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Timing constraint: Default path analysis

Overall effort level (-ol): Standard (set by user)

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REAL time: 3 secs

Total REAL time to Router completion: 3 secs

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ADDERS AND SUBTRACTORS

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FULL ADDER USING TWO HALF ADDERS:

FULL SUBTRACTOR USING TWO HALF SUBTRACTORS:

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wait for 100 ps;

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SYNTHESIS RTL SCHEMATIC:

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Minimum period: No path found

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a<='0'; b<='0'; c<='0';

SYNTHESIS RTL SCHEMATIC:

VLSI DESIGN LABORATORY

DEPARTMENT OF VLSI DESIGN

--------------------------Selected Device : 3s400tq144-5

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

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wait for 100 ps;

SYNTHESIS RTL SCHEMATIC:

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SYNTHESIS RTL SCHEMATIC:

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Number of bonded IOBs:

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