Beruflich Dokumente
Kultur Dokumente
in VLSI
Presented By:
Subhradeep Mitra
Ankita Dutta
Paramita Sau
Debanjana Biswas
Outlines
VLSI DESIGN CYCLE
PHYSICAL DESIGN CYCLE
ROUTING
PHASES OF ROUTING
CROSSTALK OVERVIEW
EFFECT OF CROSSTALK
HOW TO MINIMIZE CROSSTALK
HOW TO PREVENT CROSSTALK
CONCLUSION
REFERENCES
1) Partitioning
Routing
Problem :
The Routing is to locate a set of wires in the routing space that connect all the nets in
the net list.The capacity of channels width of wires, and wire crossing often need to
be taken into consideration.
Input :
Netlist
Timing budget for typically critical nets
Placement information including location of blocks, location of pins in
the block boundary, location of the I/O pins on the chip boundary etc.
Output :
Geometric layouts of all nets
Objectives of Routing:
Minimize the total wire length
Minimize the no of layers ( fewer layer is less expensive)
Minimize the no of vias,bends i.e. completing all connection without
increasing the chip area
Minimize the crosstalk
PHASES OF ROUTING:Routing
Global Routing
Line Routing
Detailed Routing
Maze Routing
Channel
Routing
Switch Box
Routing
Global Routing:- .
Its the first phase of routing and generates a loose route for each net.
Minimize the total wire length
Minimize running time
The global routing considers the entire layout.
This routing consists of three distinct phases-
i. Region Definition
ii. Region Assignment
iii. Pin Assignment
Global Routing
Detailed Routing: Its the second phase, of routing to finds the actual geometric layout of
each net within the assigned routing regions.
Three types of detailed routing methods:i) Channel Routing
ii) 2-D Switchbox Routing
iii) 3-D Switchbox Routing
Channel Routing
2-D Switchbox
3-D switchbox
Detailed Routing
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Crosstalk
Definition :
The electromagnetic coupling of a signal from one conductor to
another is called as crosstalk
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1. Mutual Inductance :
Mutual inductance Lm induces current from a driver line onto a
quiet line by means of the magnetic field.
The mutual inductance Lm will inject a voltage noise onto the
victim proportional to the rate of change of the current on the
driver line. The magnitude of this noise is calculated as
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2. Mutual Capacitance: Due to the recent trends of higher aspect ratios and lower spacing
between signal lines, the coupling capacitance is becoming
significant. Also the vertical height has not been scaled down .
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If one line is switching and the other line is steady the energy transfer
through the coupling capacitance results in a glitch on the quiet line
The inductively induced voltages were generally negligible compared to the
effects of the parasitic capacitances of the interconnect lines.
The interconnect capacitance is modeled as Mutual Capacitance.
d(Vvictim Vdriver)
dt
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The current
generated on the
victim line due to
mutual capacitance
will split and flow
toward both ends of
the adjacent line.
The current
generated on the
victim line due to
mutual inductance
will flow from the far
end toward the near
end of the victim line
As a result, the crosstalk currents flowing toward the near and far ends can
be broken down into several components:
Near end crosstalk is always positive
Far end crosstalk is always negative
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Effects of Crosstalk:
Signal Integrity Illustration
Noise on Delay effect
Destroying Local Information
Timing Noise
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4. Timing noise
This includes the noise by,
Skew that is the DC components of the noise
Jitter that is the AC components of the noise
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Noi sy
Regi on
Ext r a
space
Segr egat i on
Qui et
Regi on
Spaci ng
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Shielding type 1
Shieling type 2
Net Ordering
Left : Unordered
track
permutation
S
S
Right : Ordered
track
permutation for
minimizing
crosstalk
L
L
L
L
S
S
L
L
L
L
S
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Layer Assignment
When using more than 3 layer in channel routing, adjacent
Unoder ed net
Layer 1
Layer 2
Or der ed net
Layer 3
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Conclusion :
NP-hard problem
Optimal solution are taken because some other
constraints are there like wire length and congestion
Future scope :
Recently FinFET is used instead of CMOS in VLSI because, FinFET can
be significantly more power efficient than CMOS at the same gate
length.
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References :
Algorithms for VLSI Physical design Automation by Naveed
Sherwani
VLSI Design Automation Kia Bazragar
J.J.Xiong & L.He.IEEE Transon CAD, 2008
US PATIENT, PATINENT NO : US 6, 218, 631B1
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Thank You
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