5

Topstar Digital technologies Co.,LTD

D

Board name: Mother Board Schematic

1. System Block Diagram & Schematic page description;

Project name:

2. Power Block Diagram & Discription;

X03

Version: Ver A

3. Annotations & information;

Initial Date:

4. Schematic modify Item and history;

New update:

5. Power on & off Sequence;

6. ACPI Mode Switch Timings;
7. Power On Sequence Map;
8. CLOCK Distribution;

9. Power Distribution;

Topstar Confidential

Hardware drawing by:

Hardware check by:

EMI Check by:

Power check by:

Power drawing by:

B

Manager Sign by:

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name

Title

Size
A3

X03

Project Name

Rev
A

Thursday, April 29, 2010

1
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

CONTENT

Topstar Confidential
ShenZhen Topstar Industry Co.,LTD

1 Title
2 System Block & Sch Page
3 PWR Block & description
4 NOTE and Annotations
5 Sch Modify and history
6 CK-505M
7 Pineview Host/k/LVDS/DMI
8 Pineview DDR3
9 Pineview VGA/RVDS
10 Pineview Power
11 CTR CONN
12 LVDS Inverter CONN
13 DDRII SODIMM0
14 Tigerpoint (1of3)
15 Tigerpoint (2of3)
16 Tigerpoint (3of3)
17 SATA HDD
18 Card Reader
19 PCIE MINI SLOT 1
20 PCIE MINI SLOT 2
21 USB Port & FAN
22 Audio (ALC662)
23 LED
24 OTP
25 KBC(KB3310B)
26 LAN(RTL8105)
27 ADAPTER IN
28 BATTERY JACK
29 V3.3AL/+V5AL POWER
30 DDR V1.8/+V0.9S POWER
31 V1.5S/+V1.05S POWER
32 Power Good Logic_OVP
33 V5S/V3.3S/V1.8S/V1.2 Power
34 VCORE POWER
35 Power Discharge Circuit
36 CHARGER
37 Power On Secquence & Reset M
38 Power ON/OFF
39 Touchpad Board

P01 SYSTEM BLOCK Ver:A

CK505M
Clocking

Backlight
Connector

CY28548

+VDC

PG 15

+V3.3S

Pineview

LVDS

10.1' LED
+V3.3S

FCBGA 437PIN

PG 12

+VCC_CORE,+VCCP
+1.05V,+V0.89V,+V1.8V
VGA

R/G/B

DDR3
667

PG 6

DDR2 SODIMM0
667
+V0.75S,+V1.5,
PG 13

PG 7,8,9,10

+V5S

PG 11

SIM CARD

PG 20

DMI x2
Gen1

PCIE mini Card

PCIE mini Card

PG 20

10/100M

PG 19

PCIE X1

LAN
RTL8105E

RJ45

+V3.3AL,+V3.3S

PG 26
PCIE 1X

Tigerpoint
82801GBM 652 BGA

USB1.1/2.0

8Mbit

S-ATA

+V1.05S,+V3.3S
+V3.3AL,+V5AL
+V1.5S,+V5S
+V3.3A_RTC

BIOS
+V3.3AL

2.5" HHD

SATAO(R1.0)

PG 17

PG 14,15,16

PG 25

HDA

USB PORT1

Speaker

+V5S

PG 21

KB Controller/EC
+V5AL

AMP
TPS6017A2

+V5AL

USB PORT2

+V5S,+V3.3S

KB Matrix

PG 22

KB3310B
+V3.3AL

PG 25

LED & TouchPAD

AZALIA
ALC662
+V5S,+V3.3S

CAM

MiC

PG 22

Audio Jack

+V5S

PG 22

BIOS

8Mbit

+V3.3AL

TOPSTAR TECHNOLOGY
Swain Xu()

PG 25

Page Name

SD/MMC/MS/XD CARD

Size
A3

PG 18

System Block & Index

Rev
P01
A
Thursday, April 29, 2010
2
39
Date:
Sheet
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
4

Project Name

P02H

Charger power
ISL6251

Adapter
12V 2.5A

+V3.3AL5A
/+V5AL4A

POWER BLOCK Ver:A

Battery
6V-8.4V
4A

Power
Switch

Always power
ISL62382

VCC_CORE
ISL6545

+VDC

Chipset Power
ISL6545

+VCC_CORE

1.1V6A

DDR Power
ISL6545

GFX Power
ISL6545

+V1.8 6A

+0.89S 3A

+V1.05S4A
B

MOSFET
Switch

+V3.3S4A
/+V5S4A

MOSFET
Switch

+V1.8S 0.5A

LDO

LDO

+V1.5S 2A

+V0.9S 2A

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

Project Name

PWR Block & description

Rev
A

P01

Thursday, April 29, 2010

3
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

Voltage Rails

+VDC

Primary DC system power supply (6V-9.5V)

+VBATTERY

Battery Power supply (6-8.4V)

+VCC_CORE

Core Voltage for CPU

+V1.05S

1.05V for Calistoga & ICH7M core / FSB VTT

+V1.8

1.8V power rail for DDR2

+V0.9S

0.9V DDR2 Termination voltage

+V3.3AL

3.3V always on power rail

+V5AL

5V for ICH7-M's VCC5 Refsus

+V3.3S

3.3V main power rail

I2C SMB Address

Device

Address

Hex

Master

Clock Generator

D2

CPU Thermal Sensor

1101 001x
1010 000x
1001 100x

Smart Battery

0001 011x

A0
98
16

ICH7-M
ICH7-M
KBC
KBC

PCIE Slot

TBD

TBD

ICH7-M

SO-DIMM0

Power States

+V5S

5V main power rail

+V0.89S

0.89V power rail for Pineview Graphics core

Board stack up description

Signal

SLP_S3#

SLP_S4#

SLP_S5#

+V*ALW

+V*

+V*S

Clock

S0(Full On)

HIGH

HIGH

HIGH

ON

ON

ON

ON

S3(STM)

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4(STD)

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5(SoftOff)

LOW

LOW

LOW

ON

OFF

OFF

OFF

PCB Layers
Top(Signal1)
VCC 2
Signal 3

Trace Impedence:55ohm +/-15%

Wake up Events
LID switch from EC

Signal4

Power switch from EC

Ground 5
Bottom(Signal6)

USB Table

SOT23
USB Port#

PCB Footprints

Function Description

Standard USB2.0 Port

Standard USB2.0 Port

Standard USB2.0 Port

MINICARD_USB

CAM_USB

MINICARD_USB

CR_USB

NC

SOT23_5
1 2 3

ns: Component marked "ns" is not stuff

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

Project Name

NOTE
P01

Rev
A

Thursday, April 29, 2010

4
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

Schematic modify Item and history:

2009-7-6

P02 VerA Release

P02 VerB
D

2009-8-21
PG13: Add SM_VREF circuit
PG20: change SIMCARD connector to 621200700002

2009-8-24
PG25: Stuff TPCLK TPDAT pull up resistors
2009-8-27
PG31: Delete 0.89S reserved circuit
PG33: Delete 1.2S reserved circuit
2009-9-7
PG18: change IT1337E power rail to +V3.3AL follow demo

2009-9-8
PG6: Delete Clock Generator SMBUS 0ohm resistors
PG10: Delete 1.8S 1.2S colay circuit,change net name
PG11: Delete reserved 0ohm resistors that connect GND and GND_VGA
PG13: change 2.2uF capacitors from 0805 to 0603 for layout issue

2009-9-9
PG25: Delete keyboard scanin pull up RN
PG25: Delete A20gate RCIN# reserved 2N7002
PG31: Delete colay +V5S
PG35: Delete IMVP_PWRGD reserved circuit
2009-9-14
PG6: change PCI clcok,ICH 14.318MHz clock source resistors from 22ohm
to 33ohm for SI issue

2009-9-15
PG6: change Clock Generator Crystal Y3 to TFL small package for layout issue
PG16: change boardid from vera to verb
PG25: change PCB version to VerB
PG27: Connect JACK_GND with GND

2009-9-17
PG6: BUS Frequence controlled by CPU
2009-9-18

P02 VerB Release

P02 VerC
2009-10-23
PG23: ADD MSI wifi/bt 2in1 module connector and peripheral circuit
PG25: ADD MSI wifi/bt 2in1 module 3 control signals to EC gpio

2009-10-26
PG29: delet open points of +V3.3AL and +V5AL

TOPSTAR TECHNOLOGY
Swain Xu()

2009-10-27
PG19: change part reference of pcie nut to PCIE_NUT2

Page Name
Size
A3

2009-10-28
PG25: Colay small package EC

Project Name

Sch Modify and history

Rev
A

P01

Thursday, April 29, 2010

5
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
4

+V3.3S
+V1.05S

U14
SLG8SP510T
TSSOP64_0D5_6D1

+V3.3S FB7
100ohm@100MHz,3A
FB0805
1
2

+V3.3S_CK_VDD
C117
0.1uF/10V,X5R
C0402

C116
0.1uF/10V,X5R
C0402

C118
0.1uF/10V,X5R
C0402

+V3.3S_CK_VDD
C98
10UF/6.3V,X5R
C0805

C103
4.7UF/10V,Y5V
C0805

+VDDIO_CLK
+VDDIO_CLK
+VDDIO_CLK

C93
0.047uF/16V,X7R
C0402

2
9
16
61

VDD_PCI
VDD_48
VDD_PLL3
VDD_REF

39
55

VDD_SRC
VDD_CPU

48

SMB_DATA
SMB_CLK

63
64
38
37

SRC5/PCI_STOP#
VDD_IO
SRC5#/CPU_STOP#
VDD_PLL3_IO
VDD_SRC_IO_1
CPU0
VDD_SRC_IO_2
CPU0#
VDD_SRC_IO_3
VDD_CPU_IO
CPU1
CPU1#
PCI0/OE#_0/2_A
SRC8/CPU2_ITP
PCI1/OE#_1/4_ASRC8#/CPU2#_ITP

PCI2/TME

PCI3/FSD

PCI4/SRC5_SEL

PCIF5/ITP_EN

1
+V3.3S

change from 22ohm to 33ohm for SI issue

090914
TME

25
FB8
100ohm@100MHz,3A
FB0805

PCI_CLK_EC

19 PCI_CLK_DEBUG
14

PCI_CLK_ICH

R313

33

R0402

R312

33

R0402

R311

33

R0402

27M_SEL
PCIF_ITP_EN
CLK_XTAL_IN

+VDDIO_CLK
C100
10UF/6.3V,X5R
C0805

R299
10K R0402
Set to SRC8

C119
0.1uF/10V,X5R
C0402
+VDDIO_CLK

C99
10UF/6.3V,X5R
C0805
ns

R316
R310

18
CR_USB48
14 CLK_USB48

22
22

15

R395 33

CLK_ICH14

C105
10UF/6.3V,X5R
C0805

C94
0.1uF/10V,X5R
C0402

+VDDIO_CLK
C115
0.1uF/10V,X5R
C0402

090914

8
11
15
19
52
23
29
58
42

C96
0.1uF/10V,X5R
C0402

+VDDIO_CLK
C303
27pF/50V,NPO
C0402

CLK_PCIE_EXPCARD 19
CLK_PCIE_EXPCARD# 19
MPCIE_CLKREQ
MCH_CLKREQ

R375 475,1%

R0402 ns

PCIE_CLKREQ# 19

SRC9
SRC9#

30
31

SRC7/OE#_8
SRC7#/OE#_6

44
43

SRC6
SRC6#

41
40

DREFSSCLK
DREFSSCLK#

SRC4
SRC4#

27
28

CLK_PCIE_ICH 14
CLK_PCIE_ICH# 14

24
25

CLK_PCIE_LAN 26
CLK_PCIE_LAN# 26

21
22

CLK_ICH_SATA 15
CLK_ICH_SATA# 15

CLK_MCH_EXP 7
CLK_MCH_EXP# 7

9
9
C

17
18
13
14

DREFCLK
DREFCLK#
VR_CLK_EN R385 0

56

R0402

9
9

CK505_CLK_EN# 15,35

Remove 4P2R resistor.

100315

Y3
14.318180MHz
XS2_3D3
C301
27pF/50V,NPO
C0402

PM_STP_PCI# 15
PM_STP_CPU# 15

CLK_MCH_BCLK 9
CLK_MCH_BCLK# 9

33
32

VSS_PCI
SRC2/SATA
VSS_48
SRC2#/SATA#
VSS_IO
VSS_PLL3
SRC1/SE1
VSS_CPU
SRC1#/SE2
VSS_SRC_1
VSS_SRC_2
SRC0/DOT96
VSS_REF
SRC0#/DOT96#
VSS_SRC3
CK_PWRGD/PWRDWN#

CLK_XTAL_IN

R0402
R0402

47
46

C95
0.1uF/10V,X5R
C0402

R372 0
R373 0

CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7

SRC11/OE#_10
SRC11#/OE#_9

FSB/TEST_MODE
REF0/FSC/TEST_SEL
SRC3/OE#_0/2_B
SRC3#/OE#_1/4_B

R0402

change from 22ohm to 33ohm for SI issue

13,16,19
13,16,19

51
50

34
35

USB_48/FSA

57
62

SMB_DATA_S
SMB_CLK_S

54
53

SRC10
SRC10#

XTAL_IN

10

DEL 0 ohm resistors 090908

CLK_XTAL_OUT 59
No more than 500 milXTAL_OUT

R0402
R0402

CLK_BSEL0 R304 2.2K R0402

CLK_BSEL1
CLK_BSEL2 R384 10K R0402

C120
0.1uF/10V,X5R
C0402

60

7,9,10,11,12,13,14,15,16,17,19,21,22,23,24,25,26,31,32,33,34,35
7,10,15,16,24,31,32,34

SMBUS ADD:1101 001X

IO_VOUT

12
20
26
36
45
49

+VDDIO_CLK

Add R385 at CK_PWRGD for Power solution update

100315

CLK_XTAL_OUT
+V3.3S

CLK_ICH14

C313

CLK_USB48

C295

PCI_CLK_DEBUG C291
B

R131
10K
R0402
ns

PCI_CLK_EC

C292

PCI_CLK_ICH

C294

10PF/50V,NPO
C0402
10PF/50V,NPO
C0402
10PF/50V,NPO
C0402
10PF/50V,NPO
C0402
10PF/50V,NPO
C0402

ns
ns
ns
B

ns
ns

CPU_BSEL0

CPU_BSEL1

CPU_BSEL2

CLK_BSEL0

R271 1K

R0402

CLK_BSEL1

R272 1K

R0402

CLK_BSEL2

R273 1K

R0402

R139
1K
R0402
15,35 CK505_CLK_EN#
MCH_BSEL0

MCH_BSEL1

MCH_BSEL2

ns

Q2
2N7002
SOT23
ns

VR_CLK_EN

BUS FREQUENCE SELECT

+V3.3S
C129
0.1uF/10V,X5R
C0402
ns

R130
10K
R0402
ns

MCH_CLKREQ

R315 10K

R0402

MPCIE_CLKREQ R389 10K

R0402

TME

R0402

FSC
FSB
BSEL2 BSEL1

1
0

0
0
1

FSA HOST Clock

BSEL0 frequency

1
1
1

R301
10K
R0402
ns

133MHz

27M_SEL

100MHz

+V1.05S

+V1.05S

C219

R300
10K
R0402

0.1UF/10V,X5R
C0402

C133

TOPSTAR TECHNOLOGY

0.1UF/10V,X5R
C0402

166MHz
EMI CAP

R314 10K

0:Normal mode
1:No Overclocking

+V3.3S

Swain Xu()
Page Name

CK505M

Size
A3

P01

Project Name

Rev
A

of
Thursday, April 29, 2010
6
39
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
1

PINEVIEW_M

R55

R56

H_BPM_N0
H_BPM_N1
H_BPM_N2
H_BPM_N3

G11
E15
G13
F13

BPM_1B_0
BPM_1B_1
BPM_1B_2
BPM_1B_3

H_BPM2_N0
H_BPM2_N1
H_BPM2_N2
H_BPM2_N3

B18
B20
C20
B21

BPM_2_0#/RSVD
BPM_2_1#/RSVD
BPM_2_2#/RSVD
BPM_2_3#/RSVD

CPU_RSVD
H_TDI
H_TDO
H_TCK
H_TMS
H_TRST#

G5
D14
D13
B14
C14
C16

RSVD_G5
TDI
TDO
TCK
TMS
TRST_B

H_THERMDA
H_THERMDC

D30
E30

THRMDA_1
THRMDC_1

R266
R236
R248
R254

62
51
51
51

H_BPM_N0
H_BPM_N1
H_BPM_N2
H_BPM_N3
H_BPM2_N0
H_BPM2_N1
H_BPM2_N2
H_BPM2_N3
H_BPM4_PRDY#
H_BPM5_PRDQ#

R0603
R0402
R0402
R0402

CPU_RSVD
H_TDI
H_TMS
H_TDO

6 CLK_MCH_EXP#
6 CLK_MCH_EXP

N7
N6

EXP_CLKINN
EXP_CLKINP

PM_THRMTRIP# 15,24
R245 68 R0402
ns
VR_PROCHOT#
R62
0
R0402

+V1.05S

PWROK 0 ohm
,debug

H_PWROK

15

R10
R9
N10
N9

RSVD_R10
RSVD_R9
RSVD_N10
RSVD_N9

K2
J1
M4
L3

RSVD_K2
RSVD_J1
RSVD_M4
RSVD_L3

Remove R232
100315

GTLREF
VSS

A13
H27

RSVD_L6
RSVD_E17

L6
E17

BCLKN
BCLKP

H10
J10

BSEL_0
BSEL_1
BSEL_2

K5
H5
K6

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6

H30
H29
H28
G30
G29
F29
E29

RSVD_L7
RSVD_D20
RSVD_H13
RSVD_D18

L7
D20
H13
D18

RSVD_TP_K9
RSVD_TP_D19
EXTBGREF

K9
D19
K7

GTLREF_EA

R28
R29
R39
R45

G2
G1
H3
J2

EXP_RCOMPO
EXP_ICOMPI
EXP_RBIAS

L10
L9
L8

RSVD_TP_N11
RSVD_TP_P11

N11
P11

RSVD_K3
RSVD_L2
RSVD_M2
RSVD_N2

CLK_CPU_BCLK# 6
CLK_CPU_BCLK 6

0
0
0
0

R0402
R0402
R0402
R0402

DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1

14
14
14
14

R277
49.9,1%
R0402

R278
750
R0402

K3
L2
M2
N2

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
T6
T5
T7
T4
T3
T2
T1

ICTP
ICTP
ICTP
ICTP
ICTP
ICTP
ICTP

1 OF 6
?

+V1.05S
+V1.05S

6
6
6

Note:
CPU GTLREF need to be
2/3 of VCCP1 1.05V
please near GTLREF's pin

Note:
GTLREF MAX TRACE
length of 500 Mil
and 5 Mil spacing

ns
ns
ns
ns
ns
ns
ns

R253
1K,1%
R0402

R268
976,1%
R0402

GTLREF_EA

EXTBGREF
C238
C0402

C220
C0402

R269
3.32K,1%
R0402

C221
C0402 R252
2K,1%
R0402

EXTBGREF
R15
220
R0402

C30
D31

DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1

PNV_22MM_REV1P10

RSVD_C30
RSVD_D31

+V3.3S

C17
0.1uF/10V,X5R
C0402

4 OF 6
?
H_THERMDA
C20
2200pF/25V,X7R
C0402

DXP

SMBCLK

DXN
SMBDATA
G781
ADM1032AR
ALERT#
LM86CIM
MAX6657MSA
THERM#
SOIC-8

GND

H_TCK
H_TRST#

U2
F75393S
SO8_50_150

EC SMBUS ADD:1001 100X

6
4

I2C_CLK

25

I2C_DATA

25

OVT_SHUTDOWN# 24
THERM#
R31
10K
R0402

R0402
R0402

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1

15

15
15
15

H_THERMDC

R251 51
R247 51

F3
F2
H4
G3

DMI

ICH

+V1.05S
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402

0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R

+V1.05S

R0402 LVD_VREFL_OUT_R

PROCHOT_B
CPUPWRGOOD

C18
W1

H_BPM4_PRDY#
H_BPM5_PRDQ#

H_DPRSTP#
H_DPSLP#
H_INIT#

R499 470 R0402

R498 470 R0402
R497 470 R0402

R49

ns 51
ns 51
ns 51
ns 51
ns 51
ns 51
ns 51
ns 51
ns 51
51

E13

15
H_STPCLK#

C22
C21
C28
C26

DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1

PNV_22MM_REV1P10

2.37K,1% LVD_IBG
R0402
0
R0402 LVD_VREFH_OUT_R

R257
R249
R238
R250
R246
R243
R234
R233
R255
R244

THERMTRIP_B

14
14
14
14

1uF/10V,X5R

Resistor close to PNV

G6
G10
G8
E11
F15

R0402

REV = 1.1

15
15
15
15
15

1uF/10V,X5R

NOTE
Place

LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LBKLT_EN
LBKLT_CTL
LCTLA_CLK
LCTLB_CLK
LDDC_CLK
LDDC_DATA
LVDD_EN

DPRSTP_B
DPSLP_B
INIT_B
PRDY_B
PREQ_B

R258 0

H_SMI#
H_A20M#
H_FERR#
H_INTR
H_NMI
H_IGNNE#

12 LDDC_CLK
12 LDDC_DATA
12 LVDD_EN

R22
J28
LVD_VREFH_OUT_R N22
LVD_VREFL_OUT_R N23
L27
L26
LCTLA_CLK
L23
LCTLA_DATA K25
K23
K24
H26

E7
H7
H6
F10
F11
E5
F8

VCC

12,25 LVDS_BKLTEN
12 LBKLT_CTL

LVD_IBG

SMI_B
A20M_B
FERR_B
LINT00
LINT10
IGNNE_B
STPCLK_B

CPU

R37
2.2K
R0402

LVD_A_CLKM
LVD_A_CLKP
LVD_A_DATAM_0
LVD_A_DATAP_0
LVD_A_DATAM_1
LVD_A_DATAP_1
LVD_A_DATAM_2
LVD_A_DATAP_2

LVDS

+V3.3S

U25
U26
R23
R24
N26
N27
R26
R27

6,10,15,16,24,31,32,34
6,9,10,11,12,13,14,15,16,17,19,21,22,23,24,25,26,31,32,33,34,35
12,14,15,16,18,19,23,25,26,27,28,29,30,31,32,33,35

REV = 1.1
12 LVD_A_CLK_DN
12 LVD_A_CLK_DP
12 LVD_A_DATA0_DN
12 LVD_A_DATA0_DP
12 LVD_A_DATA1_DN
12 LVD_A_DATA1_DP
R50 12 LVD_A_DATA2_DN
2.2K 12 LVD_A_DATA2_DP
R0402
LCTLA_CLK
LCTLA_DATA

+V1.05S
+V3.3S
+V3.3AL

PINEVIEW_M

U3A

220pF/50V,X7R

U3D

R27
R26
10K
R0402

C18
27pF/50V,NPO
C0402

R0402
ns

PM_THRM#

15

C19
27pF/50V,NPO
C0402

NOTE

+V3.3AL

1.H_THERMDA/C10 MILS,,
.

R229
10K
R0402

+V3.3S

2.H_THERMDA/C19VVGA
EC_PROCHOT# 25

R230
1K
R0402

Q16
R235
MMBT3904-F 1K
SOT23
R0402
1

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
+V1.05S

Size
A3

+V1.05S

Diamondville(1of2)(Host BUS)
Rev
A

P01

Thursday, April 29, 2010

7
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

VR_PROCHOT#

Project Name

MA_A_A0
MA_A_A1
MA_A_A2
MA_A_A3
MA_A_A4
MA_A_A5
MA_A_A6
MA_A_A7
MA_A_A8
MA_A_A9
MA_A_A10
MA_A_A11
MA_A_A12
MA_A_A13
MA_A_A14

13

R72

MA_A_A[14:0]

M_CLK_DDR#1
M_CLK_DDR1
M_CLK_DDR#0
M_CLK_DDR0
M_ODT1
M_ODT0

M_CKE1
M_CKE0
13
13

M_CS#1
M_CS#0
13
13

MA_A_BS#2
MA_A_BS#1
MA_A_BS#0
13
13
13

MA_A_RAS#
MA_A_CAS#
MA_A_WE#
13
13
13

AK29

DDR_VREF AL28
DDE_RPD AK28
DDR_RPU AJ26

RSVD_AK29

DDR_VREF
DDR_RPD
DDR_RPU

DDR_A

RSVD_TP_AB11
RSVD_TP_AB13

VSS
RSVD_AK8

RSVD_AD17
RSVD_AC17
RSVD_AB15
RSVD_AB17

DDR_A_CK_3
DDR_A_CKB_3
DDR_A_CK_4
DDR_A_CKB_4

DDR_A_CK_0
DDR_A_CKB_0
DDR_A_CK_1
DDR_A_CKB_1

DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3

DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3

DDR_A_CSB_0
DDR_A_CSB_1
DDR_A_CSB_2
DDR_A_CSB_3

DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2

DDR_A_WEB
DDR_A_CASB
DDR_A_RASB

0 R0402
R80
R0402
5.6K,1%

DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

DDR_A_DQS_7
DDR_A_DQSB_7
DDR_A_DM_7

DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55

DDR_A_DQS_6
DDR_A_DQSB_6
DDR_A_DM_6

DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47

DDR_A_DQS_5
DDR_A_DQSB_5
DDR_A_DM_5

DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39

DDR_A_DQS_4
DDR_A_DQSB_4
DDR_A_DM_4

DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31

DDR_A_DQS_3
DDR_A_DQSB_3
DDR_A_DM_3

DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23

DDR_A_DQS_2
DDR_A_DQSB_2
DDR_A_DM_2

DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15

DDR_A_DQS_1
DDR_A_DQSB_1
DDR_A_DM_1

DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7

DDR_A_DQS_0
DDR_A_DQSB_0
DDR_A_DM_0

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

AA24 MA_DATA56
AB25 MA_DATA57
W24 MA_DATA58
W22 MA_DATA59
AB24 MA_DATA60
AB23 MA_DATA61
AA23 MA_DATA62
W27 MA_DATA63

AB27 MA_DQS7
AA27 MA_DQS#7
AB26 MA_DM7

AG31 MA_DATA48
AG30 MA_DATA49
AD30 MA_DATA50
AD29 MA_DATA51
AJ30 MA_DATA52
AJ29 MA_DATA53
AE29 MA_DATA54
AD28 MA_DATA55

AE30 MA_DQS6
AF29 MA_DQS#6
AF30 MA_DM6

AE24 MA_DATA40
AG25 MA_DATA41
AD25 MA_DATA42
AD24 MA_DATA43
AC22 MA_DATA44
AG24 MA_DATA45
AD27 MA_DATA46
AE27 MA_DATA47

AE26 MA_DQS5
AG27 MA_DQS#5
AJ27 MA_DM5

AE19 MA_DATA32
AG19 MA_DATA33
AF22 MA_DATA34
AD22 MA_DATA35
AG17 MA_DATA36
AF19 MA_DATA37
AE21 MA_DATA38
AD21 MA_DATA39

AG22 MA_DQS4
AG21 MA_DQS#4
AD19 MA_DM4

AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6

AK5 MA_DQS3
AK3 MA_DQS#3
AJ3 MA_DM3

AG8 MA_DATA16
AG7 MA_DATA17
AF10 MA_DATA18
AG11 MA_DATA19
AF7 MA_DATA20
AF8 MA_DATA21
AD11 MA_DATA22
AE10 MA_DATA23

AD8 MA_DQS2
AD10 MA_DQS#2
AE8 MA_DM2

AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6

AB8 MA_DQS1
AD7 MA_DQS#1
AA9 MA_DM1

AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3

AD3 MA_DQS0
AD2 MA_DQS#0
AD4 MA_DM0

AB11
AB13

AB4
AK8

AD17
AC17
AB15
AB17

AC15
AD15
AF13
AG13

AG15
AF15
AD13
AC13

AK24
AH26
AH24
AK27

AH10
AH9
AK10
AJ8

AH22
AK25
AJ21
AJ25

AJ20
AH20
AK11

DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14

AK22
AJ22
AK21

AH19
AJ18
AK18
AK16
AJ14
AH14
AK14
AJ12
AH13
AK12
AK20
AH12
AJ11
AJ24
AJ10

PINEVIEW_M

5
3
2

13
13

+V1.5

R71
10K
R0402
DDE_RPD
R82

ns

R88
5.6K,1%
R0402
DDR_RPU
R81

13
13
13
13
Note:
COLSE TO MCH PIN ON MCH_VREF

C65
0.1UF/10V,X5R
C0402

Page Name
Size
A3
Project Name

10,13,30,32,33,34

13 MA_DATA[63:0]

13 MA_DQS[7:0]

13 MA_DQS#[7:0]

13 MA_DM[7:0]
D

U3B
PNV_22MM_REV1P10
REV = 1.1
2 OF 6
?
?

+V1.5
80.6,1%
R0402

DDR3_DRAM_RST# 13
DDR3_DRAM_PWROK 25,30,32
+V1.5

80.6,1%
R0402
C270
0.1UF/10V,X5R
C0402

Add RESET & POWEROK FOR DDR3

100315
+V1.5
B

DDR_VREF

R84
1K,1%
R0402

R83
1K,1%
R0402

TOPSTAR TECHNOLOGY
Swain Xu()

Diamondville (PWR&GND)(2of2)

of
Date:
Sheet
Thursday, April 29, 2010
8
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

P01
Rev
A

+V3.3S

Note:
HSYNC/VSYNC: Locate series
esistor strsps within 750 mil of MCH

PINEVIEW_M

U3C
MCH_BSEL0
MCH_BSEL1
MCH_BSEL2

XDP_RSVD_5

XDP_RSVD_9
XDP_RSVD_11

XDP_RSVD_17

D12
A7
D6
C5
C7
C6
D8
B7
A9
D9
C8
B8
C10
D10
B11
B10
B12
C11

L11

XDP_RSVD_00
XDP_RSVD_01
XDP_RSVD_02
XDP_RSVD_03
XDP_RSVD_04
XDP_RSVD_05
XDP_RSVD_06
XDP_RSVD_07
XDP_RSVD_08
XDP_RSVD_09
XDP_RSVD_10
XDP_RSVD_11
XDP_RSVD_12
XDP_RSVD_13
XDP_RSVD_14
XDP_RSVD_15
XDP_RSVD_16
XDP_RSVD_17

?
REV = 1.1
CRT_HSYNC
CRT_VSYNC

M30
M29

CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN

N31
P30
P29
N30

CRT_DDC_DATA
CRT_DDC_CLK

L31
L30

DAC_IREF

P28

R0402
R0402

10
10

R42
R41

CRT_HSYNC
CRT_VSYNC

11
11
D

VGA

6
6
6

6,7,10,11,12,13,14,15,16,17,19,21,22,23,24,25,26,31,32,33,34,35

CRT_RED
CRT_GREEN
CRT_BLUE

11
11
11

+V3.3S

R30

DPL_REFCLKINP
DPL_REFCLKINN
DPL_REFSSCLKINP
DPL_REFSSCLKINN

10K R0402

PM_EXTTS0#

CRT_DDC_DATA 11
CRT_DDC_CLK 11
DACREFSET R70

Y30
Y29
AA30
AA31

665,1%R0402
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#

6
6
6
6

R779 T ,
090513
R0402,

+V3.3S

090910
R35
2.2K
R0402

RSVD_L11

R36
2.2K
R0402

CRT_DDC_DATA
3 OF 6
PM_EXTTS#_1/DPRSLPVR?
PM_EXTTS#_0
PWROK
RSTINB

PNV_22MM_REV1P10
C

AA7
AA6
R5
R6

RSVD_TP_AA7
RSVD_TP_AA6
RSVD_TP_R5
RSVD_TP_R6

AA21
W21
T21
V21

RSVD_TP_AA21
RSVD_TP_W21
RSVD_TP_T21
RSVD_TP_V21

W8
W9

R33

R0402

PM_DPRSLPVR 15
PM_EXTTS0# 13
IMVP_PWRGD 15,25,35
BUF_PLT_RST# 15,19,25,26

CRT_DDC_CLK

R240 1K,1% R0402 ns XDP_RSVD_5

R256 1K,1% R0402

XDP_RSVD_9

R239 1K,1% R0402 ns XDP_RSVD_11

B

CLK_MCH_BCLK# 6
CLK_MCH_BCLK 6

MISC

HPL_CLKINN
HPL_CLKINP

K29
J30
L5
AA3

R237 1K,1% R0402 ns XDP_RSVD_17

R54

150,1%

R0402

CRT_BLUE

R60

150,1%

R0402

CRT_GREEN

R48

150,1%

R0402

CRT_RED

150ohmGMCH
37.5ohm
150ohmVGA
50ohm
PLACE 150 OHM
RESISTORS CLOSE TO
GMCH

TOPSTAR TECHNOLOGY
Swain Xu()

Page Name

Calistoga(HOST)

Size
B

P01

Project Name

Rev
A

Date:
Sheet
of
Thursday, April 29, 2010
9
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

U3F
+V3.3S
6,7,9,11,12,13,14,15,16,17,19,21,22,23,24,25,26,31,32,33,34,35
+V1.5
8,13,30,32,33,34
+V1.05S
6,7,15,16,24,31,32,34
+V1.5S
14,16,19,23,33,34
+VCC_CORE 32,35
+V0.89S
31,34
+V1.8S
31,32

+VCC_CORE
U3E

?
PINEVIEW_M

+V1.5
PNV_22MM_REV1P10

AK13
AK19
AK9
AL11
AL16
AL21
AL25

2A

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

0.3A

+V1.05S

C253
C0402

ns

1uF/10V,X5R

10uF/6.3V,X5R

C153
C0805
10uF/6.3V,X5R

C242
C0805

4.7uF/10V,X5R

C229
C0805

C274
C0402

10uF/6.3V,X5R

C272
C0805

+V1.05S

2A

AK7
AL7

VCCCK_DDR
VCCCK_DDR

U10
U5
U6
U7
U8
U9
V2
V3
V4
W10
W11

VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR

AA10
AA11

C231
C0402

C230
C0402

C240
C0402

C359
C0805

C359 C360 Gerber FootprintC12060805

2010.03.23

Totol:
+VCC_CORE:
+V0.89S :
+V1.05S:
+V1.5S:
+V1.5:
+V1.8S:
+V3.3S:

Layout Note: VCCSENSE

and VSSSENSE lines
should be of equal
length

+VCC_CORE

VCCSENSE
VSSSENSE
VCCA

VCCACK_DDR
VCCACK_DDR

R16
R18

C29
B29
Y2

100,1%R0402
100,1% R0402

AA19

0.16A

R0805

AC31

+V1.8S

1uF/10V,X5R
C0402

L1

C56

1uF/10V,X5R
C0402

VCCACRTDAC

T31
J31
C3
B2
C2
A21

VCC_GIO
VCCRING_EAST
VCCRING_WEST
VCCRING_WEST
VCCRING_WEST
VCC_LGI_VID

V30
W31

1
+V1.8S

VCCA_DMI
VCCA_DMI
VCCA_DMI

VCCP

C249
C0402

C47
C0805

T1 VCCA_DMI
T2
T3

600ohm@100MHz,1.5A C51
C0402
FB0805
ns

E2

0.54A
T8

P2
AA1

C37
C0402
ns

0.15A

10uF/6.3V,X5R

RSVD
VCCSFR_DMIHMPLL

ICTP

ns

0
R0603

C38
C0402

+V1.8S

+V1.05S C48
C0402
ns
1uF/10V,X5R

0.18A

PINEVIEW_M

VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PNV_22MM_REV1P10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
VSS
RSVD_NCTF
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS

REV = 1.1
VSS F24
VSS F28
VSS F4
VSS G15
VSS G17
VSS G22
VSS G27
VSS G31
VSS H11
VSS H15
VSS H2
VSS H21
VSS H25
VSS H8
VSS J11
VSS J13
VSS J15
VSS J4
VSS K11
VSS K13
VSS K19
VSS K26
VSS K27
VSS K28
VSS K30
VSS K4
VSS K8
VSS L1
VSS L13
VSS L18
VSS L22
VSS L24
VSS L25
VSS L29
VSS M28
VSS M3
VSS N1
VSS N13
VSS N18
VSS N24
VSS N25
VSS N28
VSS N4
VSS N5
VSS N8
VSS P13
VSS P14
VSS P16
VSS P18
VSS P19
VSS P21
VSS P3
VSS P4
VSS R25
VSS R7
VSS R8
VSS T11
VSS U22
VSS U23
VSS U24
VSS U27
VSS V14
VSS V16
VSS V18
VSS V28
VSS V29
VSS W13
VSS W2
VSS W23
VSS W25
VSS W26
VSS W28
VSS W30
VSS W4
VSS W5
VSS W6
VSS W7
VSS Y28
VSS Y3
VSS Y4

VSS

6 OF 6
?

T29

Demo 1.0P2pin NC
090605

0.42A

1uF/10V,X5R

1uF/10V,X5R

C263
C0402
1uF/10V,X5R

C233
C0402

1uF/10V,X5R

0.35A

C243
C0402

FB6

VCCSFR_AB_DPL

+V3.3S

+V1.05S
+V1.05S

+V1.8S

VCCALVD
VCCDLVD
T30

C41

VCCA_DMI R58

VCCD_HMPLL

1uF/10V,X5R
C0402

600ohm@100MHz,1.5A
FB0805

0.01uF/16V,X7R
C0402

LVDS

C54

VCCP
VCCP

0 R0402

VCCD_AB_DPL

DMI

D4
B4
B3

R501

C43

+V1.05S

V11

+V1.8S
R75

VCC

+V1.5S

1uF/10V,X5R

ns

EXP\CRT\PLL

ns

0.1uF/10V,X5R

C244
C0402

0.1uF/10V,X5R

C228
C0402

5.77A
6.04A

Route VCCSENSE and VSSSENSE

traces at 27.4 Ohms with 50
mil spacing

+V1.05S

R280
0
R0402

N450/N45x
N470/N47x
2.64A
3.2A
0.16A
2.3A
0.33A
0.01A

1uF/10V,X5R

R0805

POWER

0.1uF/10V,X5R

R283

DDR

+V1.5

C234
C0402
ns

1uF/10V,X5R

1uF/10V,X5R

ns

1uF/10V,X5R

1uF/10V,X5R

C276 C269 C277

C0402 C0402 C0402
ns

1uF/10V,X5R

C271
C0402

5 OF 6

+VCC_CORE

10uF/6.3V,X5R

+V1.5

6.04A

1uF/10V,X5R

ns

A23
A25
A27
B23
B24
B25
B26
B27
C24
C26
D23
D24
D26
D28
E22
E24
E27
F21
F22
F25
G19
G21
G24
H17
H19
H22
H24
J17
J19
J21
J22
K15
K17
K21
L14
L16
L19
L21
N14
N16
N19
N21

1uF/10V,X5R

+V0.89S

VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
? VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

1uF/10V,X5R

C255

2.64A

CPU

C254

T13
T14
T16
T18
T19
V13
V19
W14
W16
W18
W19

GFX/MCH

C0402
1uF/10V,X5R

C0402
1uF/10V,X5R

C250

1uF/10V,X5R
C0402

C0402
1uF/10V,X5R

C0402
1uF/10V,X5R

C248

1uF/10V,X5R
C0402

C246

2.2UF/10V,X5R
C0603

C257

1uF/10V,X5R

REV = 1.1

+V0.89S
C247

A11
A16
A19
A29
A3
A30
A4
AA13
AA14
AA16
AA18
AA2
AA22
AA25
AA26
AA29
AA8
AB19
AB21
AB28
AB29
AB30
AC10
AC11
AC19
AC2
AC21
AC28
AC30
AD26
AD5
AE1
AE11
AE13
AE15
AE17
AE22
AE31
AF11
AF17
AF21
AF24
AF28
AG10
AG3
AH18
AH23
AH28
AH4
AH6
AH8
AJ1
AJ16
AJ31
AK1
AK2
AK23
AK30
AK31
AL13
AL19
AL2
AL23
AL29
AL3
AL30
AL9
B13
B16
B19
B22
B30
B31
B5
B9
C1
C12
C21
C22
C25
C31
D22
E1
E10
E19
E21
E25
E8
F17
F19

GND

+V0.89S

ns

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name

Calistoga(Graphic)

Size
A3

P01

Project Name

Rev

Thursday, April 29, 2010

10
39
Date:
Sheet
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V5S
+V3.3S

Cross moat
place

Cross moat place

+V5S

CRT_RED

FB2

D3
1

FB5
47ohm@100MHz,500mA
FB0603
1
2

ROUT

2 1

1N5819HW-F
SOD123

GND_VGA

100ohm@100MHz,3A
FB0805

R264
100K
R0402

+V5_VGA

C45

5.6pF/50V NPO
C0402

15pF/50V,NPO

ROUT

FB4
47ohm@100MHz,500mA
GND_VGA
FB0603
1
2

CRT_GREEN

D8
BAT54S
SOT23

6
1
7
2
8
3
9
4
10
5

GND_VGA

GOUT

GND_VGA +V3.3S

BOUT
GOUT

C44

R63
150,1%
R0402

5.6pF/50V NPO
C0402

15pF/50V,NPO

FB3
GND_VGA
47ohm@100MHz,500mA
FB0603
1
2

CRT_BLUE

5VDDCDA
CRT_HSYNC

14

CRT_VSYNC

CRT_HSYNC

CRT_VSYNC

5VDDCCK

15

shell

C10518-11505-L
VGADMF

C252
15PF/50V,NPO
C0402
ns

C239
100pF/50V,NPO
C0402

C235
100pF/50V,NPO
C0402

C227
15PF/50V,NPO
C0402
ns

BOUT
GND_VGA
GND_VGA

C25
15pF/50V,NPO

D4
BAT54S
SOT23

GND_VGA

No external level shifter for HSync & VSync at PINEVIEW

090605

C24
5.6pF/50V NPO
C0402

150ohm
50ohm

CLK

R265
1K
R0402
ns

13

GND_VGA +V3.3S

R32
150,1%
R0402

12

NC
NC VSYNC

shell

D7
BAT54S
SOT23

11

16

C30

C29

R47
150,1%
R0402

NC

SDA
G
GND
HSYNC
B

GND
GND

+V3.3S

R276
1K
R0402
ns

CONNECTOR TOP VIEW

GND
R
GND

+V3.3S

VGA

17

12,16,17,21,22,23,25,31,33,34,35
6,7,9,10,12,13,14,15,16,17,19,21,22,23,24,25,26,31,32,33,34,35

+V3.3S
GND_VGA
+V3.3S

+V5_VGA

Update C25,C30,C45 to 15PF for EMI issue

100315
R267
2.2K
R0402

5VDDCCK

D26
BAT54S
SOT23

+V5_VGA

R281
2.2K
R0402

+V5_VGA
GND_VGA
5VDDCDA

9 CRT_DDC_DATA

R282
2.2K
R0402

Q18
2N7002

+V3.3S
+V3.3S

9 CRT_DDC_CLK

R263
2.2K
R0402

Q17
2N7002

D29
BAT54S
SOT23

+V3.3S

D28

2
CRT_HSYNC 3

D27
C241
0.1uF/10V,X5R
C0402

3
1

GND_VGA

+V5_VGA
GND_VGA

2
CRT_VSYNC

1
BAT54S
SOT23

+V3.3S

+V3.3S

BAT54S
SOT23

C237
0.1uF/10V,X5R
C0402

GND_VGA

TOPSTAR TECHNOLOGY
Swain Xu()

GND_VGA
Page Name
Connect GND to GND_VGA for EMI requirement
Swain 080724
DEL

R19

R80

0ohm

Size
A3

Project Name

CRT CONN & S TV OUT & LIDR SWITCH

Rev
A

P01

resistors

Friday, April 30, 2010

11
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3AL
+V3.3S
+V5AL
+VDC
+V5S
R1
100K
R0402 D1
BAT54A
SOT23

High : Enable
Low : Disable
D

+V3.3S
LCDVDD

7,25 LVDS_BKLTEN

R5
1K
R0402

3
21,25

LIDR#

LDDC_CLK

CLOSE TO INTCON

LCDCON
88242-4001
CNS40_LCD_R1

LCDVDD
C5
1000pF/50V,X7R
C0402

3
2

15,25 PM_SUS_STAT#

7 LVD_A_CLK_DP
7 LVD_A_CLK_DN
Add LCD Back light on function
0801222

EDID_PWR
+V5AL_CAM

25
Q11
+V3.3S AO6409
TSOP6_0D95_1D6

4
5
6

+V3.3AL

FB21

R0805

R0805

INVT_VDD
C3
0.1UF/25V,Y5V
C0402

ns

500mA

LVDD_EN

PQ46
2N7002
ns SOT23

1
ns

LVD_A_DATA0_DN7
LVD_A_DATA0_DP7
LVD_A_DATA2_DN7
LVD_A_DATA2_DP7
LDDC_CLK 7
LDDC_DATA 7
USB_CAM_PN5 14
USB_CAM_PP5 14
BT_PWR
BT_DISABLE 22
USB_BT_PP7
USB_BT_PN7

Add R698,R701 at SM BUS

081218

23
23
C

Update LCDCON fot 40 pin pannle conn

081111

R226
100K
ns

+V3.3AL +V3.3S
R894
R0603

0
BT
Q23

C216
ns

R225
100K
ns

AO3415
R514
R515

R0603
BT
0
R0603
ns

2
ns

BT_PWR

C260
1000pF/50V,X7R
ns

SPWG Require LCDVDD rising time

is 0.5-10ms,1-10ms is better

100pF/50V,NPO

0.1UF/10V,X5R
C0402

PQ45
2N7002
SOT23

+VDC

R221
100
R0603
ns

Q14
2N7002E-T1
SOT23

C215
R215
10UF/6.3V,X5R 2.2K
C0805
R0402
ns

3
2
1

C214
0.1uF/10V,X5R
C0402

C210

3
2

R220
100K
R0402

+V5S

IVT_I_ADJ

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

LDDC_DATA R34 2.2K R0402

41
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

FB1

BKLT_PWM
BKLT_ON

41
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

R43 2.2K R0402

R209
100K
R0402

7 LVDD_EN

+VDC

LCDVDD

R208
10K
R0402

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

7 LVD_A_DATA1_DN
7 LVD_A_DATA1_DP

D16
BAT54A
SOT23

ns LCD Back light on function

Swain 080820

+V3.3S

500mA

BKLT_ON
25 HW_OFF_BKLT#

14,15,16,18,19,21,23,25,26,27,28,29,30,31,32,33,35
6,7,9,10,11,13,14,15,16,17,19,21,22,23,24,25,26,31,32,33,34,35
16,21,29,30,31,32,33
19,21,27,29,30,31,32,33,34,35
11,16,17,21,22,23,25,31,33,34,35

R517
100K
ns
B

22
+V5AL

R4

R0402

R3

R0402
ns

R516 ns

1K

+V5S

R213
0
R0805
ns

R212
0
R0805

BKLT_PWM

R214

C4
100pF/50V,NPO
C0402

0 R0805
+V5AL_CAM

R2
10K
R0402

R224
10K
R0402
ns

25 EC_BKLT_PWM
7 LBKLT_CTL

BT_ON#

BT_PWRON

Q13
SOT23
AO3415
ns

500mA
C211
0.1uF/10V,X5R
C0402

C213
10UF/6.3V,X5R
C0805

R223 10K
R0402

ns
+V3.3S

R210 0

R0402

EDID_PWR
C212
100pF/50V,NPO
C0402

25 CAM_PWRON

R222
100K
R0402
ns

TOPSTAR TECHNOLOGY

Add +5S to CAM POWER

081111

1
2

Swain Xu()

Q12
2N7002E-T1
SOT23
ns

Page Name
Size
A3

Project Name

LVDS
Rev
A

P01

Thursday, April 29, 2010

12
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V0.75S
+V1.5
+V3.3S

DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7

113
115
110

WE
CAS
RAS

M_CKE0
M_CKE1

73
74

CKE0
CKE1

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1

101
103
102
104

CK0
CK0
CK1
CK1

116
120

ODT0
ODT1

12
29
47
64
137
154
171
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

200
202

SDA
SCL

197
201

SA0
SA1

199

VDDSPD

1
126

VREF_DQ
VREF_CA

198
30

EVENT#
RESET#

77
122
125

NC1
NC2
NCTEST

8 MA_DM[7:0]
8
8
8
8
8

8
8

MA_A_WE#
MA_A_CAS#
MA_A_RAS#

M_ODT0
M_ODT1
MA_DQS0
MA_DQS1
MA_DQS2
MA_DQS3
MA_DQS4
MA_DQS5
MA_DQS6
MA_DQS7

8 MA_DQS[7:0]
B

6,16,19 SMB_DATA_S
6,16,19 SMB_CLK_S

1010 000x

10K R0402
10K R0402

VREF_DQ
VREF_CA

C80
0.1UF/10V,X5R
C0402

R298
R297

C81
2.2UF/10V,X5R
C0603

9 PM_EXTTS0#
8 DDR3_DRAM_RST#

DDR3_SODIMM204_0

145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

DDRIII

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

10
27
45
62
135
152
169
186

MA_DQS#0
MA_DQS#1
MA_DQS#2
MA_DQS#3
MA_DQS#4
MA_DQS#5
MA_DQS#6
MA_DQS#7

+V1.5

11
28
46
63
136
153
170
187

M_CS#0
M_CS#1

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

CS0
CS1

MA_A_BS#0
MA_A_BS#1
MA_A_BS#2

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

C264
10uF/6.3V,X5R
+ C280
220UF/6.3V,OSCON C0805
CAP6_6x7_3
ns
ns

C282
10uF/6.3V,X5R
C0805

C286
0.1uF/10V,X5R
C0402

C267
2.2UF/10V,X5R
C0603

C85
2.2UF/10V,X5R
C0603

C287
0.1uF/10V,X5R
C0402
ns

C86
2.2UF/10V,X5R
C0603
ns

C89
0.1uF/10V,X5R
C0402

C91
0.1uF/10V,X5R
C0402

C281
2.2UF/10V,X5R
C0603

C285
0.1uF/10V,X5R
C0402
ns

C273
2.2UF/10V,X5R
C0603

+V1.5

C90
0.1uF/10V,X5R
C0402

+V1.5

C88
2.2UF/10V,X5R
C0603

Ns C

+V0.75S

C70
0.1uF/10V,X5R
C0402

C69
0.1uF/10V,X5R
C0402
ns

C68
0.1uF/10V,X5R
C0402

C67
0.1uF/10V,X5R
C0402

+V1.5

+V1.5

R505
1K,1%
R0402

R502
1K,1%
R0402

VREF_CA

VREF_DQ

C197

C83
C130
R508
2.2UF/10V,X5R 1K,1%
R0402
C0603

0.1UF/10V,X5R
C0402

0.1UF/10V,X5R
C0402

close to DDR pin

C82
R503
2.2UF/10V,X5R 1K,1%
R0402
C0603

close to DDR pin

MA_DQS#[7:0] 8

GND1
GND2

114
121

8
8

T93

MA_DATA[63:0] 8

205
206

BA0
BA1
BA2

ICTP

VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

109
108
79

8
8
8

+V3.3S

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

ns

8
8
8
8

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

204
203
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78

Layout note:DDR slot VDD PIN

DIM1

MA_A_A0
MA_A_A1
MA_A_A2
MA_A_A3
MA_A_A4
MA_A_A5
MA_A_A6
MA_A_A7
MA_A_A8
MA_A_A9
MA_A_A10
MA_A_A11
MA_A_A12
MA_A_A13
MA_A_A14

VTT2
VTT1

MA_A_A[14:0]

30,34
8,10,30,32,33,34
6,7,9,10,11,12,14,15,16,17,19,21,22,23,24,25,26,31,32,33,34,35

SO-DIMM
0

+V0.75S +V1.5

20.1UF
A

TOPSTAR TECHNOLOGY
leixiaoyu
Page Name
Size
A3

Project Name

DDRII SODIMM0
Rev
A

P02H

Date:
Thursday, April 29, 2010
Sheet
13
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3S
+V3.3AL
+V1.5S

TGP

U18B

26
26
26
26
19
19
19
19

PCIE_RXN0_LAN
PCIE_RXP0_LAN
PCIE_TXN0_LAN
PCIE_TXP0_LAN
PCIE_RXN1_SLOT
PCIE_RXP1_SLOT
PCIE_TXN1_SLOT
PCIE_TXP1_SLOT

C304 0.1UF/10V,X7R
C305 0.1UF/10V,X7R
C307 0.1UF/10V,X7R
C309 0.1UF/10V,X7R

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

K21
K22
J23
J24
M18
M19
K24
K25
L23
L24
L22
M21
P17
P18
N25
N24

PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4

U1LB

PCI-E

R23
R24
P21
P20
T21
T20
T24
T25
T19
T18
U23
U24
V21
V20
V24
V23

USB

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

H7
H6
H3
H2
J2
J3
K6
K5
K1
K2
L2
L3
M6
M5
N1
N2

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31

D4
C5
D3
D2
E5
E6
C2
C3

USBRBIAS
USBRBIAS#

G2
G3

DMI

7
7
7
7
7
7
7
7

USB_PORT_PN1 21
USB_PORT_PP1 21
USB_CAM_PN5 12
USB_CAM_PP5 12
MINICARD_USB_PN4
MINICARD_USB_PP4
USB_CR_PN6 18
USB_CR_PP6 18
USB_BT_PN7 23
USB_BT_PP7
23

+V3.3S

19
19

R364
10K
R0402
+V3.3AL

F4

R353 8.2K

PCI_DEVSEL#

R348 8.2K

PCI_IRDY#

R329
R330
R349
R328
R351
R354
R333
R337
R355
R323

8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K

PCI_CLK_ICH

R345
R325
R324
R115
R327
R347
R116
R326
R117
R114

8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K

PCI_SERR#
PCI_STOP#
PCI_LOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#
PCI_REQ#1
PCI_REQ#2
ns FLASH_SEL0
ns FLASH_SEL1
PCI_PIRQ#0
PCI_PIRQ#1
PCI_PIRQ#2
PCI_PIRQ#3
PCI_PIRQ#4
PCI_PIRQ#5
PCI_PIRQ#6
PCI_PIRQ#7
RSVD_K9
RSVD_M13

R370 22.6,1% R0402

CLK_USB48

T14 ns

USB_PORT_OC0# 21

USB_RBIAS_PN

R331 8.2K
R350 10K

GPIO22
EC_RUNTIME_SCI#
R0402

25 EC_RUNTIME_SCI#
R332
10K
R0402
ns

R346
10K
R0402
ns

R0402 24.9,1%

R135

H24
DMI_IRCOMP_R J22
W23
W24

6 CLK_PCIE_ICH#
6 CLK_PCIE_ICH

A5
PCI_DEVSEL# B15
J12
PCI_RST# A23
PCI_IRDY# B7
C22
PCI_SERR# B11
PCI_STOP# F14
PCI_LOCK# A8
PCI_TRDY# A10
PCI_PERR# D10
PCI_FRAME# A16

PAR
DEVSEL#
PCICLK
PCIRST#
IRDY#
PME#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#

A18
E16

GNT1#
GNT2#

PCI_REQ#1G16
PCI_REQ#2 A20

REQ1#
REQ2#

FLASH_SEL0 G14
FLASH_SEL1
A2
GPIO22
C15
C9

PCI_PIRQ#0 B2
PCI_PIRQ#1 D7
PCI_PIRQ#2 B3
PCI_PIRQ#3H10
PCI_PIRQ#4 E8
PCI_PIRQ#5 D6
PCI_PIRQ#6 H8
PCI_PIRQ#7 F8
R352 1K
R0402 ns

TGP
DMI_ZCOMP
DMI_IRCOMP

TGP

U18A

USB_PORT_PN0 21
USB_PORT_PP0 21

Trace tied togerther close to pins length

no longer than 200 mill to resistor

CLK48

+V1.5S

6,7,9,10,11,12,13,15,16,17,19,21,22,23,24,25,26,31,32,33,34,35
12,15,16,18,19,21,23,25,26,27,28,29,30,31,32,33,35
10,16,19,23,33,34

PCI_STRAP0#
D11
RSVD_K9
K9
RSVD_M13 M13

U1LB

PCI

GPIO48/ STRAP1#
GPIO17/ STRAP2#
GPIO22
GPIO1

PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
STRAP0#
RSVD01
RSVD02

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1

C/BE0#
C/BE1#
C/BE2#
C/BE3#

H16
M15
C13
L16

?
TGP

FLASHSEL1
0
1
1

DMI_CLKN
DMI_CLKP
2

FLASHSEL0
1
0
1

Boot BIOS
SPI
PCI
LPC

SPI_POWER
+V3.3S+V3.3AL
R320
10K
R0402
ns

R321
R322
0
0
R0402
R0402
ns
ns

U16
W25X40
SO8_50_150

VDD

R317 3.3K R0402 SPI_WP# 3

ns
R379 3.3K R0402 SPI_HD# 7
ns
C306
0.1uF/10V,X5R
C0402
ns
A

SPI_POWER
SPI_HD#
SPI_SCK
SPI_SI

WP#

VCC
HOLD#
CLK
D

R318
8.2K
R0402
ns

ns

SI
SO
CE#
SCK

5
2
1
6

VSS

CS#
Q
W#
VSS

1
2
3
4

HOLD#

8
7
6
5

R376
8.2K
R0402
ns

SPI_SI
SPI_SO
SPI_CE#
SPI_SCK

SPI_CE#
SPI_SO
SPI_WP#

R377 22
R319 22

R0402 ns
R0402 ns

R378 22

R0402 ns

SPI_SI_ICH
SPI_SO_ICH
SPI_CE#_ICH
SPI_SCK_ICH

SPI_SI_ICH
SPI_SO_ICH
SPI_CE#_ICH
SPI_SCK_ICH

15
15
15
15

NS SPI ROOM at ICH7

Swain 081113

TOPSTAR TECHNOLOGY
Swain Xu()

U15
W25X80A
SOIC8_50_208

Page Name
Size
A3

ns

SPI ROOM used +3.3S, reserved 3.3AL

Swain 080815

Project Name

ICH7_M(1 of 4)
Rev
A

P01

Date:
Sheet
of
Thursday, April 29, 2010
14
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
4

U1LB

AA14
V14

RSVD27
RSVD28

AD16
AB11
AB10

RSVD29
RSVD30
RSVD31

AD23

GPIO36

SATA

R414 10K R0402

ns
19,25
LPC_AD0
19,25
LPC_AD1
19,25
LPC_AD2
19,25
LPC_AD3
R434 10K R0402
+V3.3S
ns
19,25 LPC_FRAME#

R433
0
R0402
22 HDA_BITCLK
22
HDA_RST#
22 HDA_SDATA_IN0

SATA_CLKN
SATA_CLKP

AD4
AC4

SATARBIAS#
SATARBIAS
SATALED#

AD11
AC11
AD25

22
22
6

CLK_ICH_SATA# 6
CLK_ICH_SATA 6
R0402 24.9,1%

HDD_LED#

T25 ns

R444 0

25
7

R340

H_IGNNE#

H_INIT#
H_INTR

7
7

H_NMI

INT_SERIRQ
R0402

R404
56
R0402

R0402

R445
10K
R0402
H_FERR#

H_RCIN#

25

H_SMI#
H_STPCLK#
7
PM_THRMTRIP# 7,24

16
16

SMB_CLK
SMB_DATA

14
14
14
14

SPI_SO_ICH
SPI_SI_ICH
SPI_CE#_ICH
SPI_SCK_ICH

SPI_SO_ICH
SPI_SI_ICH
SPI_CE#_ICH
SPI_SCK_ICH

R144
10K
R0402

R512 0

R0402
ns

C143
0.1uF/10V,X5R
C0402
ns
+V3.3A_RTC

CK505_CLK_EN# 6,35

Reserved R512 ,NS Q4,R143 for POWER GOOD

100315

PLT_RST# R513

C172
0.1uF/10V,X5R
C0402
ns

R0402

R2
T1
M8
P9
R4

GND

C358
R162
0.1uF/10V,X5R
100K
C0402
R0402
ns
ns

B25
AB23
AA18
F20

BATLOW#
DPRSTP#
DPSLP#
RSVD31

R4322

25
D

PM_DPRSLPVR 9
T23
GPIO25
T15
T18
T19

PM_STP_PCI# 6
PM_STP_CPU# 6

ICTPns
R496
10K
R0402
ns

ICTPns
ICTPns
ICTPns

R500
10K
R0402
ns

+V3.3S

PM_CLKRUN# 25
BOARDID_0
BOARDID_1
BOARDID_2

PM_THRM#
VRM_PWRGD
ICH_SYNC#
PM_RI#
ICH_SUSCLK T16
SYS_RST#
PLT_RST#

PM_THRM#

PM_PWRBTN# 25
PM_SUS_STAT# 12,25
ICTPns
SYS_RST# 25
PCIE_WAKE# 19,25,26

PC_BEEP
PM_SLP_S3#
PM_SLP_S4#
T17
ICTPns

PM_BATLOW#
R409 0
R0402
R438 0
R0402

1 R0402
100

16
16
16

H_PWROK

SM_INTRUDER#
PM_ICH_PWROK
RSMRST#
ICH_INTVRMEN

H20
E25
F21 PM_SLP_S5#

SLP_S3#
SLP_S4#
SLP_S5#

EXT_SMI#

GPIO12
GPIO13
GPIO14
GPIO15

22
25,32 EC
25,34

PM_BATLOW# 25
H_DPRSTP#
7
H_DPSLP#
7
+V1.05S
R440
56nsR0402
R407
56nsR0402

PM_RSMRST# 25,32
R431
10K
R0402

PLT_RST#

2
U7
74AHC1G08GV
SOT23_5
ns

+V3.3S

CR2032_DH

R455
1M
R0402

+V3.3AL

J1
Shunt
Open

3
Assy

Y4
32.768KHz
xd3_2X6

R400
10M
R0402

C316
C338
1uF/10V,X7R
C0603

RTCX1

CMOS Settings
Clear CMOS
Keep CMOS

CLR_CMOS1
JOPEN
RESISTOR_1
ns

R126
R368
R365
R356
R343
R358
R118
R371
R134

10K
10K
10K
10K
10K
1K
10K
10K
10K

R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402

SMB_LINK_ALERT#
SMLINK0
SMLINK1
SMB_ALERT#
PM_BATLOW#
PCIE_WAKE#
SYS_RST#
PM_RI#
EXT_SMI#

R342
R341
R388
R362
R132
R124

090604

1K
1K
1K
1K
1K
1K

R0402
R0402
R0402
R0402
R0402
R0402

25 EC_MAIN_PWROK

C171
0.1uF/10V,X5R
C0402

U6
74AHC1G08GV
SOT23_5

GPIO12
GPIO13
GPIO14
GPIO15
GPIO8
GPIO9

VCC
PM_ICH_PWROK

4
2

9,25,35 IMVP_PWRGD

RTCX2

18pF/50V,NPO
C0402

RTCBAT1

R458
20K
R0402

C317
18pF/50V,NPO
C0402

R10
0
R0402
ns

C13
1uF/10V,X7R
C0603

D2
BAT54C
SOT23

GND

TGP
SPI_MISO
SPI_MOSI
SPI_CS#
SPI_CLK
SPI_ARB

AB17
V16
AC18
E21
H23
G22
D22
G18
G23
C25
T8
U10
AC3
AD3
J16

ICH_INTVRMEN

VCC

SMBALERT#/GPIO11
SMBCLK
SMBDATA
SMLALERT#
SMLINK0
SMLINK1

AB22

THRM#
VRMPWRGD
MCH_SYNC#
PWRBTN#
RI#
SUS_STAT#/LPCPD#
SUSCLK
SYS_RESET#
PLTRSTB
WAKE#
INTRUDER#
PWROK
RSMRST#
INTVRMEN
SPKR

GPIO8
GPIO9

+V3.3A_RTC

RTCX1
RTCX2
RTCRST#

CPUPWRGD/GPIO49

RSMRST#

VCC

R12
332K,1%
R0402

R11
1K
R0402

R9
1K
R0402

LAN_CLK
LANR_STSYNC
LAN_RST#
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2

GPIO0

9,19,25,26 BUF_PLT_RST#

EC_RTC

T4
P7
B23
AA2
AD1
AC2
W3
T7
U4

T15
W16
W14
K18
H19
M17
A24
C23
P5
E24
AB20
Y16
AB19
R3
C24
D19
D20
F22
AC19
U14
AC1
AC23
AC24

Q4
2N7002
SOT23

ns

ns

EE_CS
EE_DIN
EE_DOUT
EE_SHCLK

BM_BUSY#/GPIO0
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
DPRSLPVR
STP_PCI#
STP_CPU#
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
CLKRUN#
GPIO33
GPIO34
GPIO38
GPIO39

+V3.3AL
VRM_PWRGD

6,35 CK505_CLK_EN#

U3
AE2
T6
V3

SMB_ALERT#
E20
SMB_CLK
H18
SMB_DATA
E23
SMB_LINK_ALERT# H21
SMLINK0
F25
SMLINK1
F24

+V1.05S

HDA_BIT_CLK
HDA_RST#
HDA_SDI0
HDA_SDIN1
HDA_SDIN2
HDA_SDOUT
HDA_SYNC
CLK14

U1LB

SPI

+V3.3S

R143
1K
R0402

P6
U2
W2
V2
P8
AA1
Y1
AA3

RTCX1
W4
RTCX2
V5
RTC_RST# T5

25

R0402

+V3.3S

R441
56
R0402

R0402
R0402

23

H_A20GATE
H_A20M#

R442 0

R412 33
R405 33

LDRQ1#/GPIO23
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
LFRAME#

SMB

TGP

CPUSLP# T24 ns

R0402
R0402

AA5
V6
AA6
Y5
W8
Y8
Y4

GND
R158
10K
R0402

R446 10K
R0402

HOST

+V3.3S

U16
Y20
Y21
Y18
AD21
AC25
AB24
Y22
T17
AC21
AA16
AA21
V18
AA20

R394 33
R397 33

R435

+V1.05S

A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT#
INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
THERMTRIP#

HDA_SDOUT
HDA_SYNC
CLK_ICH14

TGP

U18D

+V3.3S

17
17
17
17

RTC

RSVD24
RSVD25
RSVD26

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

C0402 0.01uF/25V,X7R C327

C0402 0.01uF/25V,X7R C326

LAN

AB16
AE24
AE23

AE6
AD6
AC7
AD7
AE8
AD8
AD9
AC9

EPROM

RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

+V3.3S
6,7,9,10,11,12,13,14,16,17,19,21,22,23,24,25,26,31,32,33,34,35
+V1.05S
6,7,10,16,24,31,32,34
+V3.3A_RTC 16
+V3.3AL
12,14,16,18,19,21,23,25,26,27,28,29,30,31,32,33,35

11,12,16,17,21,22,23,25,31,33,34,35
29

AUDIO

RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18

AC17
AB13
AC13
AB15
Y14

+V5S
EC_RTC

LPC

TGP

U18C

R12
AE20
AD17
AC15
AD18
Y12
AA10
AA12
Y10
AD15
W10
V12
AE21
AE18
AD19
U12

MISC

RTC_RST#
SM_INTRUDER#

+V3.3S

R439
R437
R443
R436
ns R410
ns R408
R145

R344 1K

1K R0402 ICH_SYNC#
10K R0402 PM_THRM#
8.2K R0402PM_CLKRUN#
4.7K R0402 INT_SERIRQ
1K R0402 HDA_SDOUT
1K R0402 HDA_SYNC
1K R0402
GPIO0
R0402

TOPSTAR TECHNOLOGY
Swain Xu()

GPIO25

Page Name

ICH7_M(2 of 4)

Size
A3

P01

Project Name

Rev
A

of
Date:
Sheet
Friday, April 30, 2010
15
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
2

+V3.3AL

+V3.3S
+V3.3AL
+V5S
+V3.3A_RTC
+V1.5S
+V1.05S
+V5AL

+V5S
D11
1N4148WS
SOD323

R119
100
R0402

D10
1N4148WS
SOD323

+V5AL

R121
10
R0402

+V3.3S

U1LB

TGP

U18E

U18F
C113
1uF/10V,X7R
C0603

F12

6mA

VCC5REF_SUS

F5

10mA

VCCSATAPLL

Y6

VCC5REF

VCCRTC

AE3

VCCDMIPLL

Y25

VCCUSBPLL

F6

45mA
6uA
24mA

+V1.5S

C328
C0402
0.1UF/10V,X5R

C325
C0402
0.1UF/10V,X5R
ns

C154
C0402
ns

G24
AE13
F2

RSVD32

AE16

0.1UF/10V,X5R

0.01uF/25V,Y5V

10uF/6.3V,X5R

1uF/10V,X5R

4.7uF/10V,Y5V
C0805
ns

C112
C0402

C162
C0402

TGP

F18
N4
K7
F1

+V3.3AL

0.1A

1uF/10V,X5R

0.1UF/10V,X5R

C108
C0402

NEAR PIN F1

C124
C0402

NEAR PIN K7,N4

C107
C0805
10uF/6.3V,X5R

C131
C0402

1uF/10V,X5R

VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4

VSS
VSS
VSS

OPTION FOR FB
C148

0.1UF/10V,X5R

ns

R0805

+V3.3S

0.1UF/10V,X5R

ns

C145
C0402
1uF/10V,X5R

1uF/10V,X5R

C141
C0402
1uF/10V,X5R

C127
C0402

H25
AD13
F10
G10
R10
T9

VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
TGP

0.22A

+V1.5S

R148 0

C149
C0402

C128
C0805

C146
C0402

1uF/10V,X5R

C132
C0402

C158
C0805

VCCDMIPLL

+V1.05S

1A

J10
K17
P15
V10

VCC1_05_1
VCC1_05_2
VCC1_05_3
VCC1_05_4

0.1UF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1.5A

10uF/6.3V,X5R

C138 C110 C156 C134 C155

C0402 C0402 C0805 C0402 C0402
ns
ns
ns

POWER

R0805

OPTION FOR FB
VCCDMIPLL

14mA

AA8
M9
M20
N22

A1
A25
B6
B10
B16
B20
B24
E18
F16
G4
G8
H1
H4
H5
K4
K8
K11
K19
K20
L4
M7
M11
N3
N12
N13
N14
N23
P11
P13
P19
R14
R22
T2
T22
V1
V7
V8
V19
V22
V25
W12
W22
Y2
Y24
AB4 ?
AB6
AB7
AB8
AC8
AD2
AD10
AD20
AD24
AE1
AE10
AE25

+V3.3A_RTC

+V1.05S

VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+V1.5S
R150 0

10mA

W18

V_CPU_IO

TGP

U1LB

C109
0.1uF/10V,X5R
C0402

10uF/6.3V,X5R

U1LB

0.1uF/10V,X5R

6,7,9,10,11,12,13,14,15,17,19,21,22,23,24,25,26,31,32,33,34,35
12,14,15,18,19,21,23,25,26,27,28,29,30,31,32,33,35
11,12,17,21,22,23,25,31,33,34,35
15
10,14,19,23,33,34
6,7,10,15,24,31,32,34
12,21,29,30,31,32,33

ns

NEAR PIN F18

Fuction P.M2 P.M1 P.M0

P02
+V3.3AL

+V3.3S
+V3.3S

R338
2.2K
R0402

15

SMB_DATA

R339
2.2K
R0402

SMB_DATA

SMB_CLK

SMB_CLK

SMB_DATA_S

6,13,19

SMB_CLK_S

6,13,19

R415
10K
R0402

0
0

1
1

0
1

R429
10K
R0402
ns
BOARDID_0
BOARDID_1
BOARDID_2

R411
10K
R0402

R426
10K
R0402
ns

15
15
15

R416
10K
R0402

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

15

R413
10K
R0402
ns

X03
X01i

R294
2.2K
R0402

Q20
2N7002
SOT23

R295
2.2K
R0402

Q21
2N7002
SOT23

X01

ICH7_M(2 of 3)
Rev
A

P01

of
Date:
Sheet
Thursday, April 29, 2010
16
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

+V5S

Project Name

+V5S

11,12,16,21,22,23,25,31,33,34,35

+V3.3S

6,7,9,10,11,12,13,14,15,16,19,21,22,23,24,25,26,31,32,33,34,35

SATA HDD
+V5S

V_HDD
FB20 0

C320
4.7uF/10V,Y5V
C0805

C318
0.1UF/10V,X5R
C0402

+V3.3S

C319
0.1UF/10V,X5R
C0402

15
15
15
15

V3.3_SATA
FB19 0

SATA_HDD
SATA CONN
SATA_D_50B_1

Close to connector as possible

the same distance to connector

R0805

SATA_TXP0
SATA_TXN0
SATA_RXN0
SATA_RXP0

C297 0.01uF/25V,X7R C0402

C298 0.01uF/25V,X7R C0402

2
3
5
6

1
4
7

8
9
10

VCC3_0
VCC3_1
VCC3_2

GND3
GND4
GND5

11
12
13

V_HDD

14
15
16
18

VCC5_0
VCC5_1
VCC5_2
REEVE

GND6

17

GND7

19

20
21
22

VCC12_0
VCC12_1
VCC12_2

GND8
GND9

23
24

C312
0.1UF/16V,Y5V
C0402
ns

GND0
GND1
GND2

V3.3_SATA

R0805 ns
C308
4.7uF/10V,Y5V
C0805
ns

TX
TX#
RX#
RX

C311
0.1UF/16V,Y5V
C0402
ns

SATA_B1

SATA_B2

Screw 2*5mm
Assembly
711000000117

Screw 2*5mm
Assembly
711000000117

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name

Size
A4

Project Name

SATA HDD

Rev
A

P01

17
39
of
Date: Friday, April 30, 2010
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3AL

12,14,15,16,19,21,23,25,26,27,28,29,30,31,32,33,35

All of by-pass capacitors must be closed to IC

D3.3V
D3.3V

DGND

DGND

REG18V

36
35
34
33
32
31
30
29
28
27
26
25
REG33Vin
REG18Vout
SM/SD/MS D7
GPIO6
SM/SD/MS D6
GPIO5
TC
SM/SD/MS D5
GPIO1
GPIO4
VSS
REG33Vout
REG5Vin
GPIO0/LED
SM/SD/MS D4
RST
GPIO3
ClkSel
SM/SD/MS D3
SM_CD
SM_ALE
PWR_SW
VDD33
VSS

24
23
22
21
20
19
18
17
16
15
14
13

+V3.3AL

C177
0.1UF/10V,X5R
C0402

RST
ClkSel
SM_D3

GND_USB

PWR_SW2

PWR_SW2

J3

D3.3V

DGND

C195
0.1UF/10V,X5R
C0402
GND_USB

SM_WP

R188 0

R0402

SD_CLK

SM_RNB
SM_WPSW

10
2

SM_D0
SM_D1
SM_D2
SM_D3

7
8
9
1

SD_CLK
SM_CE

5
11

SM_D2
VDD18

SM_RNB
SM_D0
SM_D1

VDD

VSS1
DAT0
VSS2
DAT1
DAT2
G1
CD/DAT3
G2
G3
CLK
G4
SD_WP

3
6

CD
CMD

2 in 1 Card

1
2
3
4
5
6
7
8
9
10
11
12
XTALO
XTALI

IT1337E-48D/BX
QFPS48_0D5_1D6

GND_USB

OLD 2IN1 CONN.

R504
R0603

IT1337E-48

GND_USB

GND_USB

C182
0.1UF/10V,X5R
C0402

REG3.3V

GPIO7
Clk12M_out
SM_CE/SD_WP
SM_WP/SD_CLK/MS_CLK
VSS
SM_WR
EE_SDA
SD/MS/xD
EE_CLK
AVDD33
DP
DM
AVSS

CR_USB48
SM_WPSW

D3.3V
14 USB_CR_PP6
14 USB_CR_PN6

R0402
ns
C187
2.2UF/10V,X5R
C0603

GND_USB

XTALO
XTALI
xD_CD
Clk48M
SM_WP_SW/SD_CMD/MS_BS
SM_RD/MS_INS
SM_RNB/SD_CD
SM/SD/MS D0
SM/SD/MS D1
SM_CLE
SM/SD/MS D2
VDD18

37
Clk12M-out 38
SM_CE
39
SM_WP
40
DGND
41
42
EE_SDA
43
EE_SCL
44
D3.3V
45
46
47
DGND
48

VDD18

R168 0
R167 R0402

C180
4.7uF/10V,X5R
C175
C0805
4.7uF/10V,X5R
C0805
GND_USB

REG3.3V

U8
GND_USB

REG18V

R165
30K
R0402

RST
C190
0.1UF/10V,X5R
C0402

REG3.3V
D3.3V

REG18V

C362
0.1UF/10V,X5R

12
13
14
15

SD_MMC

GND_USB

C361
1uF/10V,X7R
C0603

GND_USB

GND_USB

VDD18

use 48Mhz crystal

ClkSel R164

0
R0402

GND_USB
CR_USB48

R187

0
Clk12M-out Int-12MHz
R0402

D3.3V
XTALI

1
2
3
4

A0
A1
A2
VSS
ns

GND_USB

VCC
WP
SCL
SDA

8
7
6
5

EE_SCL
EE_SDA

S-24CS02AFJ-TB-G
SO8_50_150

R174 0 EXT-12M
R0402
ns

C193
0.1UF/10V,X5R
C0402
ns
GND_USB

Ext-12MHz

IT1337E-48 PIN MUX

C186
GND_USB
27pF/50V,NPO

R189
0
R0402

S0=P12=EEP_SDA
S1=P13=EEP_SCK

U10

use 12Mhz crystal

R190
0
R0402
ns

EEprom Setting

C0402 ns
Y5
12.000MHz
XS2_3D3
ns
C189

XTALO
GND_USB

R177
ns

0
R0402

GND_USB

27pF/50V,NPO
C0402
ns

PINs
05

SM/xD
SM_WPSW

SD/MMC
SD_CMD

MS
MS_BS

06

SM_RD

07

SM_RNB

MS_INS

08

SM_D0

SD_D0

MS_D0

09

SM_D1

SD_D1

MS_D1

11

SM_D2

SD_D2

MS_D2

18

SM_D3

SD_D3

MS_D3

22

SM_D4

SD_D4

MS_D4

SD_CD

TOPSTAR TECHNOLOGY
Swain Xu()

29

SM_D5

SD_D5

MS_D5

Page Name

Card Reader(UB6232 USB)

32

SM_D6

SD_D6

MS_D6

Size
A3

P01

34

SM_D7

SD_D7

MS_D7

39

SM_CE

SD_WP

40

SM_WP

SD_CLK
2

MS_CLK

Project Name

Rev
A

Thursday, April 29, 2010

18
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
1

+V3.3S
+V3.3AL
+V1.5S
+VDC

6,7,9,10,11,12,13,14,15,16,17,21,22,23,24,25,26,31,32,33,34,35
12,14,15,16,18,21,23,25,26,27,28,29,30,31,32,33,35
10,14,16,23,33,34
12,21,27,29,30,31,32,33,34,35

+DATA4

change pcie nut part reference

-DATA4

+V3.3S

+V3.3AL

R459
0
R0603

CHK5
90ohm@100M0.33A
l4_0805
ns
3
4
2
1

-DATA4
+DATA4

36
38

USB_DUSB_D+

6 CLK_PCIE_EXPCARD#
6 CLK_PCIE_EXPCARD

11
13

REFCLKREFCLK+

14 PCIE_TXN1_SLOT
14 PCIE_TXP1_SLOT

31
33

PETN0
PETP0

6 PCI_CLK_DEBUG

R477 0
R478 0

R0402
R0402

ns
Debug

17
19

RESERVED0
RESERVED1

R489 0
R493 0

R0402
R0402 Debug
PICE_39
R0402
R0402
Debug
R0402
Debug
R0402
Debug
R0402
Debug
R0402
Debug

37
39
41
43
45
47
49
51

RESERVED_PCIE0
RESERVED_PCIE1
RESERVED_PCIE2
RESERVED_PCIE3
RESERVED_PCIE4
RESERVED_PCIE5
RESERVED_PCIE6
RESERVED_PCIE7

R484
R485
R480
R481
R482
R483

15,25 LPC_FRAME#
15,25
LPC_AD0
15,25
LPC_AD1
15,25
LPC_AD2
15,25
LPC_AD3

PERN0
PERP0

0
0
0
0
0
0

th_230_118_6

24

48
28
6

+V3.3S

LED_WPAN#
LED_WLAN#
LED_WWAN#

46
44
42

PERST#
WAKE#
CLKREQ#

22
1
7

SMB_DATA
SMB_CLK

32
30

ns
ns
ns

ns

R492 0
R491 0

R0603
R0603

PICE_39

R487
10K
R0402
ns

minicard_CLKREQ#
C

minicard_Wake#
minicard_CLKREQ#

R486 0
R490 0

R0402
R0402

ns
ns

R456 0
R457 0

R0402
R0402

ns
ns

minicard_Wake#

BUF_PLT_RST# 9,15,25,26
PCIE_WAKE# 15,25,26
PCIE_CLKREQ# 6
SMB_DATA_S 6,13,16
SMB_CLK_S 6,13,16

+V3.3AL

CHANNEL_CLK
CHANNEL_DATA

5
3

RESERVED_DISABLE

20

RESERVED_SIM0
RESERVED_SIM1
RESERVED_SIM2
RESERVED_SIM3
RESERVED_SIM4

16
14
12
10
8

9
15
21
27
29
35
4
18
26
34
40
50
53
54

+V3.3AL
+V3.3S

+V3.3AL

R488
10K
R0402
ns

ICTP
T28
ICTP
T32
ICTP
T27

R0402
10K
R460
R461 0
ns

ns

T29
R464 ICTP
0
R0402
R463 0
R0402
R462 0
R0402
T26

R0402

ns
ns
ns

HW_RATIO_OFF1#

25

PWR_SW_VCC2 21,29
EC_DEBG_UTXD 25
EC_DEBG_URXD 25

ICTP

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13

WIFI OptionDebug Option

23
25

MINI_HOLE

1
2
3
4
5
6
7

14 PCIE_RXN1_SLOT
14 PCIE_RXP1_SLOT

R452
0 +V1.5S
R0603
ns

+1.5V0
+1.5V1
+1.5V2

R0402
R0402

PCIE mini Card

+3.3V0
+3.3V1

Keep USB2.0 Signal stub short

R453 0
R454 0

R451
0
R0603
+V3.3AL_PCIE

2
52

MPCIE2
MINIPCIE_TEMP1

+VDC
9,15,25,26 BUF_PLT_RST#

1
2
3
4
5
6
7

R155
0
R0603
ns

+3.3VAUX

D39
ESDPAD_R0603
EGA1-0603-V05
ns

+V3.3S_PCIE

14 MINICARD_USB_PN4
14 MINICARD_USB_PP4

091027

+V3.3S
PCIE_NUT2

D40
ESDPAD_R0603
EGA1-0603-V05
ns

+V3.3S_PCIE
C170
10UF/6.3V,X5R
C0805
ns

PCIE MINI CARD

+V3.3AL_PCIE
C335
0.1UF/10V,X5R
C0402

C330
10UF/6.3V,X5R
C0805

C337
0.1UF/10V,X5R
C0402

+V1.5S

C331
10UF/6.3V,X5R
C0805
ns

C333
0.1UF/10V,X5R
C0402
ns

C336
0.1UF/10V,X5R
C0402
ns

C332
0.1UF/10V,X5R
C0402

C334
0.1UF/10V,X5R
C0402

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

Project Name

PCIE MINI SLOT 1

Rev
A

P01

Friday, April 30, 2010

19
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

Project Name

Blank
Rev
A

X03

of
Date:
Sheet
Thursday, April 29, 2010
20
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

Change C289 to F source

Swain 080814

GND

1
D33
ESDPAD_R0603
EGA1-0603-V05

SINGLE USB PORT

USB1G_1

GND_USB

CHK4 ns

1
4

2
3

+V3.3AL

USB_PORT_PN0 14
USB_PORT_PP0 14

l4_0805
90ohm@100M0.33A
D34
ESDPAD_R0603
EGA1-0603-V05

R336 0

R0603

R335 0

R0603

PWR_SW
Button_4P
BUTTON4_S
DEL 2

PWRSW#

hole 090908

GND_USB
GND_USB

GND_USB

SWVCC1

PR1

10K

R0402

SWVCC2_SW

PR2

100K

R0402

Isense_SYSP

1
PR137
1M
R0402

PC2
1000pF/50V,X7R
PC1
C0402
1000pF/50V,X7R
C0402

GND

-DATA1
+DATA1

SINGLE USB PORT

USB1G_1

GND_USB

GND_USB

D30
ESDPAD_R0603
EGA1-0603-V05

D31
ESDPAD_R0603
EGA1-0603-V05

PD16
BAT54S
SOT23
ns

PZ1
BZT52C5V6S
SOD323

PC95
1000pF/50V,X7R
C0402

PWR_SW_VCC2

CHK3 L4_0805 ns
3
4
2
1

GND_USB

4
3
2

R291 0

R0603

R290 0

R0603

19,29

USB_PORT_PN1 14
USB_PORT_PP1 14
C

+V3.3AL

VCC1
-DATA1
+DATA1

HOLE0
HOLE1
HOLE2
HOLE3

D32
ESDPAD_R0603
EGA1-0603-V05
ns

USB1

Keep USB2.0 Signal stub short

GND_USB

U1
APX9132A
SOT23_A
VS+ 1

GND_USB
GND_USB

+V3.3AL

+V5S

R73
10K

+V3.3S

R67
10K
ns

R68
10K

Output

GND

GND_USB
C1
1000pF/50V,X7R
C0402

ns

R66
ns

1K

FAN_TACH_ON
1

EN/FON#
VIN
VOUT
VSET

1
2
3
4

D9

U21
P2793A
SO8_50_150

+V3.3S

R293
200K
C283
4.7UF/10V,Y5V
C0805

25

Q1
2N2222
SOT23
ns

GND_USB
R74
0
B

CPUFAN1
Vfan

GND
GND
GND
GND

1000pF/50V,X7R
ns

2.2uF/10V,X5R

C64
1N4148WS
2.2uF/10V,X5R
SOD323

8
7
6
5

C468

C57
R69
10K
ns

12,25

ESD1
EGA1-0603-V05
ESDPAD_R0603
ns

FAN_BACK
+V3.3S +V5S

LIDR#

Update USB footprint to USB1F

081215

C2
0.1UF/10V,X5R

5
6
7
8

C84
100uF/10V
ct7343_28

25

+V3.3AL

PQ37
2N7002E-T1
SOT23

27,36

+V5AL_USB1

C290
330PF/50V,X7R
+
C0402
ns
ns

PR138
20K
R0402

3
2

Install C429 for OC# issue

Swain 080815

6,7,9,10,11,12,13,14,15,16,17,19,22,23,24,25,26,31,32,33,34,35
12,14,15,16,18,19,23,25,26,27,28,29,30,31,32,33,35
11,12,16,17,22,23,25,31,33,34,35
12,16,29,30,31,32,33
12,19,27,29,30,31,32,33,34,35

USB_PORT_OC0#14

Keep USB2.0 Signal

stub short

-DATA1
+DATA1

R0402

C300
1000pF/50V,X7R
C0402

GND_USB

-DATA0
+DATA0

+V3.3S
+V3.3AL
+V5S
+V5AL
+VDC

GND_USB
4

R366
300K
R0402

+V5AL

R361 560K
C101
100uF/10V
ct7343_28

VCC1
HOLE0
HOLE1
HOLE2
HOLE3

USB2

5
6
7
8

C302
330PF/50V,X7R +
C0402

D36
ESDPAD_R0603
EGA1-0603-V05
ns

+V5AL_USB1

S2
1.6A
FUSE1812
1
2

1
2
3

1
2
3

Econn
CNS3_R

GND_USB
FAN_FB

R86
4.7K
R0402
FAN1_V

R0402

25

C284
0.1UF/10V,X5R
C0402

TOPSTAR TECHNOLOGY

FAN1_V=3.30V,Vfan=5V
FAN1_V=2.65V,Vfan=4V
FAN1_V=1.98V,Vfan=3V

Swain Xu()
Page Name

Output Board

Size
A3

P01

Project Name

Rev
A

Friday, April 30, 2010

21
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3S
+V5S

6,7,9,10,11,12,13,14,15,16,17,19,21,23,24,25,26,31,32,33,34,35
11,12,16,17,21,23,25,31,33,34,35

Headphone Jack
VCC5CDC

+V5S
FB16
1

T30 ICTP

C0805

HP_OUT_L

FRONT-OUT-R

36

C356

4.7uF/10V,X5R

C0805

HP_OUT_R

LINE1-VREFO-R

37

VREF
11

REST#

15 HDA_BITCLK

BITCLK

15 HDA_SYNC

10
5

R0402

C348

1uF/10V,Y5V C0603

C352

33

R0402

10pF/50V,NPO

BTL_BEEP

C0402
ns
12

JACK_DET_A
R469
15

75K R0402

C347

1uF/10V,Y5V C0603

C350

PC_BEEP

100pF/50V,NPO
C0402
R470
4.7K
R0402

R468
4.7K
R0402

JD2

34

LINE2-L

CEN-OUT

43

15

LINE2-R

LFE-OUT

44

C0805 16

MIC2-L

4.7uF/10V,X5R

C0805 17

MIC2-R

ALC662

SIDESURR-OUT-L

45

SIDESURR-OUT-R

46

18

CD-L

SPDIFI/EAPD

47

20

CD-R

SPDIFO

48

SURR-OUT-L

39

JDREF

40

SURR-OUT-R

41

C344

1uF/10V,X7R

C0603 21

MIC1-L

C343

1uF/10V,X7R

C0603 22

MIC1-R

23

LINE1-L

Layout Note:
All of JD resistors should be
placed as close as possible to
the sense pin of codec.

33

14

4.7uF/10V,X5R

INT_MIC_L

32

DCVOL

JD1

C341

update internal MIC circuit

LINE2-VREFO
MIC1-VREFO-R

13

C342

LINE1-R

19

4
7

24

VREFOUT

R473

4.7K

R0402
ns

FB11 1

ESDPAD_R0603
D38

0.1UF/10V,X5R
C315
C168
C0402
100pF/50V,NPO
C0402

EGA1-0603-V05

GND_AUD

D14
ESDPAD_R0603
C161
EGA1-0603-V05
100pF/50V,NPO
C0402

D13
ESDPAD_R0603
EGA1-0603-V05

AZALIAJACK
AUDIO8B

INT_MIC_L_R

GND_AUD

31

PC-BEEP

MIC2_R

REMOVE SHUTDOWN#

30

SDIN

MIC2_L

MIC2-VREFO
SDOUT

AGND1
AGND2

25

51K

LINE1-VREFO-L

10UF/6.3V,X5R C0805

R0402

R475

R474

2.2K

R0402

R476

4.7K

R0402

MIC2_REF

Stereo Microphone Jack

INT_MIC_L_R
1N4148WS
2
SOD323
D42
1N4148WS
1
2
SOD323

VCC5CDC

MIC2_REF 1

JACK_DET_B

R156
4.7K
R0402
EAPD

R495

R0402 SHUTDOWN#
ns

INPUT:STEREO MIC-IN
OUTPUT:CENT/LFE

D41

10K R0402
ns

R153
4.7K
R0402

MIC_IN1

MIC2_L

R466

75

R0402

FB14 1

MIC2_R

R465

75

R0402

FB13 1

2 300ohm@100MHz,2A
FB0805
2 300ohm@100MHz,2A
FB0805

MIC2_JD
SURR_OUT_L
R494

20K,1%

R0402

D43
ESDPAD_R0603
EGA1-0603-V05

GND_AUD
SURR_OUT_R

C339

C173

C169

D19
ESDPAD_R0603
EGA1-0603-V05

100pF/50V,NPO 100pF/50V,NPO
C0402
C0402
C0402
0.1UF/10V,X5R

1
4
2
5
6
3
7
8

D18
ESDPAD_R0603
EGA1-0603-V05

AZALIAJACK
AUDIO8B

26
42

R472

15 HDA_SDATA_IN0
R471

28
29

SYNC

CD-GND

15 HDA_SDOUT

MIC1-VREFO-L

0.1UF/10V,X5R C0402

C346

75

HP_JD

1
4
2
5
6
3
7
8

??

GND1
GND2

15 HDA_RST#

27

C349

R149

2 300ohm@100MHz,2A
FB0805
2 300ohm@100MHz,2A
FB0805

GPIO1

4.7uF/10V,X5R

FB12 1

C353

R0402

A_GPIO1

35

75

ns

HP_OUT_R
FRONT-OUT-L

R152

GPIO0

LINE_OUT1
HP_OUT_L

AVDD1
AVDD2

A_GPIO0

C199
0.1UF/10V,X5R
C0402

Cross moat place

GND_AUD

U19
ALC662
QFPS48_0D5_1D6

25
38

1
9
ns

VDD1
VDD2

T31 ICTP

C340
C0805
10UF/6.3V,X5R

C345
C0402
0.1UF/10V,X5R

C357
C0402
0.1UF/10V,X5R

C355
C0805
10UF/6.3V,X5R

C354
C0402
0.1UF/10V,X5R

C351
C0402
0.1UF/10V,X5R

INPUT:HEADPHONE/LINE-OUT
OUTPUT:FRONT L/R

2 300ohm@100MHz,2A
FB0805

+V3.3S

GND_AUD

GND_AUD
JACK_DET_B

R479

20K,1%

JACK_DET_A

R467

5.11K,1% R0402

R0402

MIC2_JD

VCC5CDC VCC5CDC

R181
10K
R0402
ns

AMP_SHDW

15.6dB
21.6dB

AMP_SHDW

HP_JD

Q6
2N7002DW
SC70_6

Q9
2N7002DW
SC70_6

Av(inv)
6dB
10dB

D20

5
1

Adjust Gain to 10dB

BY K' 080118

GAIN0 GAIN1
0
0
0
1
1
0

GND_AUD

GAIN0
GAIN1

R185
10K
R0402
ns

R180
10K
R0402

HP_OUT_R

GND_AUD

2 JOPEN_3
ns

HP_OUT_L

R183
10K
R0402

R157

R0402
ns

R182

R0402

VCC5CDC
C166

GND_AUD GND_AUD

R176
10K
R0402

C191
SHUTDOWN#

De-pop Solution
3
AMP_SHDW

R0402

1
R195
10K
R0402

FB15 1
C136

R179
100K
R0402

25

1K

ns

0.1UF/10V,X5R

Layout Note:
Tied at three points under the
codec and near the codec

Q10
2N7002
R194

C0402

0.1UF/10V,X5R
C0402
ns

2 300ohm@100MHz,2A
FB0805
ns
C0402

ns

0.1UF/10V,X5R

GND_AUD

Onboard Amp

GND_AUD
SURR_OUT_L

C179
C178

20K R0402

0.22uF/10V,X7R R166 10K R0402

C0603
0.22uF/10V,X7R
C0603
R175 20K R0402

C192
0.22uF/10V,X7R
C0603

SHUTDOWN#

ROUT+

18

INTSPR+

RIN+

ROUT-

14

INTSPR-

LIN+

LOUT+

INTSPL+

10

BYPASS LOUT-

5
12

LINNC

16
6
15
1
11
13
20
21

17

RIN-

7
9

19

GAIN0

GAIN1

VDD
PVDD1
PVDD2
SHDWN# GND1
GND2
GAIN0
GND3
GND4
GAIN1
GND5

INTSPLINTSPL+
INTSPR+
INTSPR-

INTSPLVCC5CDC
C188
C0402

INTSPK1
INT_spkR 4Pin
CNS4_R
4 4 6 6
3 3
2 2
1 1 5 5

INT_MIC_L

R146
1K
R0402

FB10
2 300ohm@100MHz,2A 1
FB0805
2

C135
100pF/50V,NPO
C0402

C181
C0805

C183
C0402

onboard stereo
microphone

INT_MIC_L_R

GND_AUD

U9
APA2031
sop20_0d65_4d4g
R184

C194
0.22uF/10V,X7R
C0603
SURR_OUT_R

GND_AUD

4.7uF/10V,Y5V

MIC1
Microphone
BZ_D6027
ASSY

D12
ESDPAD_R0603
EGA1-0603-V05
ns

TOPSTAR TECHNOLOGY

0.1UF/10V,X7R
0.1UF/10V,X7R

Swain Xu()
Page Name
GND_AUD

Change R336,R326,R324 to 0 ohm

Swain 081120

Size
C

GND_AUD

Project Name

Audio
P01

Rev
A

Date:
Sheet
Friday, April 30, 2010
22
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V5S
+V3.3S
+V3.3AL
+V1.05S
+V1.5S

+V3.3S

R447
10K
R0402

LED
D

+V3.3S

ns

R196 220 R0402 IDE+

ns

2 ns

TP_HDD_LED#

HDD_LED#

15

1
2
3
4
5
6

1
2
3
4
5
6

11,12,16,17,21,22,25,31,33,34,35
6,7,9,10,11,12,13,14,15,16,17,19,21,22,24,25,26,31,32,33,34,35
12,14,15,16,18,19,21,25,26,27,28,29,30,31,32,33,35
6,7,10,15,16,24,31,32,34
10,14,16,19,33,34

+V5S
D

TPCLK
TPDAT

25
25

CNS6_0D5_RA1
INT_spkR 6Pin
TP

HDD
BL-HB335A-TRB

TCHARGE
LED4_1210B
HA1B333B AMP&BLUE

+V3.3AL

Blue Color
2

TP_CHG_LED#

C198
0.1UF/10V,X5R
C0402

R202 220 R0402 BAT_STATE_LED 3

R203 220 R0402 CHARGE_LED

TP_BTL_LED#

Orange color
R204 220 R0402 PWR+

25

BTL_LED#

25

H6

H3

H9

H2

HOLE
TH_256_100

HOLE
TH_256_100

H11
TP_POWERLED#

CHG_LED#

POWERLED# 25

ns
TP_HDD_LED#

TESD6
ns

2 EGA1-0603-V05
ESDPAD_R0603

TP_CHG_LED#

TESD4
ns

2 EGA1-0603-V05
ESDPAD_R0603

TP_BTL_LED#

TESD3
ns

2 EGA1-0603-V05
ESDPAD_R0603

TP_POWERLED#

TESD5
ns

2 EGA1-0603-V05
ESDPAD_R0603

IDE+

ns

C201

1000pF/50V,X7R C0402

CHARGE_LED

C203

1000pF/50V,X7R C0402

BAT_STATE_LED

C204

1000pF/50V,X7R C0402

ns

ns

HOLE

HOLE
TH_S276_256_100

POWER
BL-HB335A-TRB
C

HOLE

ns

ns
GND_BAT

TH_256_100A

H8

H4

TH_256_100A

H10

H1

H5

ns

ns

ns

GND_AUD

TH_256_100A
PWR+

C200

1000pF/50V,X7R C0402

TP_POWERLED# R201 10K R0402

ns

ns

HOLE

HOLE
TH_S276_256_100

HOLE
TH_256_100

R199 10K R0402

ns

HOLE

TP_BTL_LED#

HOLE
TH_256_100

R200 10K R0402

ns

+V3.3AL
TP_CHG_LED#

ns

TH_276X236_100

H4,H4 footprintTH_315_100
080820

FD5

FD8

FD1

FMARKS
ns

FMARKS
ns

FD6

FD3

FMARKS FMARKS
ns
ns

FD7

FMARKS
ns

FD4

FMARKS
ns

FD2

FMARKS
ns

FMARKS
ns

+V3.3AL

C222
0.1UF/10V,X5R
C0402

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

Project Name

LED/WIFI/BT
Rev
A

P01

Thursday, April 29, 2010

23
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V1.05S
+V3.3S

6,7,10,15,16,31,32,34
6,7,9,10,11,12,13,14,15,16,17,19,21,22,23,25,26,31,32,33,34,35

+V3.3S
+V1.05S
R186
10K
R0402

R192
4.7K
R0402
ns
SHDN_LOCK#

ALT_ON

3
R169
100K
R0402
ns

C184
0.1uF/10V,X5R
C0402
ns

ns

7,15 PM_THRMTRIP#
Q5
2N7002E-T1
SOT23

1
R178
100K
R0402

SHDN_LOCK# 32

R171
470
R0402

25

R170
4.7K
R0402
ns

2
Q8
MMDT3904
SC70_6

R172
100K
R0402

C185
1000pF/50V,X7R
C0402

7 OVT_SHUTDOWN#

R193
100
R0402
ns

R173
10K
R0402

R191
1K
R0402
ns

Q7
MMDT3904
SC70_6
ns

C196
2.2uF/10V,X7R
C0805
ns

OVP CIRCUIT

VIN

CPU
THRMTRIP#
AND

SHDN#

THERM_ALERT#
Thermal
sensor

VDC

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name

Size
A4

Project Name

MDC&BT/FAN/OTP

Rev
A

P01

24
39
of
Date: Thursday, April 29, 2010
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3S
+V3.3AL
+V5S

EC_V3.3AL
+V3.3S

6,7,9,10,11,12,13,14,15,16,17,19,21,22,23,24,26,31,32,33,34,35
12,14,15,16,18,19,21,23,26,27,28,29,30,31,32,33,35
11,12,16,17,21,22,23,31,33,34,35
EC_V3.3AL

KSI7/GPIO37
KSI6/GPIO36
KSI5/GPIO35
KSI4/GPIO34
KSI3/GPIO33
KSI2/GPIO32
KSI1/GPIO31
KSI0/GPIO30/E51_TXD(ISP)

SCANOUT15
SCANOUT14
SCANOUT13
SCANOUT12
SCANOUT11
SCANOUT10
SCANOUT9
SCANOUT8
SCANOUT7
SCANOUT6
SCANOUT5
SCANOUT4
SCANOUT3
SCANOUT2
SCANOUT1
SCANOUT0

82
81
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

KSO17/GPIO49
KSO16/GPIO48
KSO15/GPIO2F/E51_RXD(ISP)
KSO14/GPIO2E
KSO13/GPIO2D
KSO12/GPIO2C
KSO11/GPIO2B
KSO10/GPIO2A
KSO9/GPIO29
KSO8/GPIO28
KSO7/GPIO27
KSO6/GPIO26
KSO5/GPIO25
KSO4/GPIO24
KSO3/GPIO23/TP_ISP
KSO2/GPIO22/TP_ANA_TEST
KSO1/GPIO21/TP_PLL
KSO0/GPIO20/TP_TEST

Fuction P.M2 P.M1 P.M0

0
0

Verc

R450
10K
R0402
ns

R422
10K
R0402

R448
10K
R0402
ns
PCB_Mark0
PCB_Mark1
PCB_Mark2
R421
10K
R0402

V0_75S_ON
ALWAYS_ON
MAIN_ON
V1_5_ON

32 MAIN_PWROK
9,15,35 IMVP_PWRGD

R0402 0

R403

76
75

GPI43
GPI42

90
30
31
92
93
91
95

E51CS#/GPIO52
E51TXD/GPIO16
E51RXD/GPIO17/E51CLK
E51TMR0/GPIO54/WDT_LED#
E51INT0/GPIO55/SCROLED#
E51TMR1/GPIO53/CAPSLED#
E51INT1/GPIO56

7 EC_PROCHOT#

111
96
33
22
9
125
VCC
VCC
VCC
VCC
VCC
VCC

R357 10K R0402

R363 10K R0402
R369 10K R0402

CHG_ON
SYS_I_Sense

R122 10K R0402

C299 3300pF/50V,X7R
C0402

C137
100pF/50V,NPO
C0402

FAN_BACK
BT_DISABLE
FAN1_V
IVT_I_ADJ

PSCLK1/GPIO4A/P80CLK
PSDAT1/GPIO4B/P80DAT
PSCLK2/GPIO4C
PSDAT2/GPIO4D
PSCLK3/GPIO4E
PSDAT3/GPIO4F

83
84
85
86
87
88

TPCLK
TPDAT
EC_ICH_PWROK
EC_SMI#
ns R0402

21
23
21
12

23
23

EC_ICH_PWROK R390
MAIN_PWROK
R154

HW_RATIO_OFF1# 19
0 R398

EXT_SMI#

SPI pull up

EC_SPI_CS#
EC_SPI_MOSI
EC_SPI_MISO
EC_SPI_SCK
I2C_CLK
I2C_DATA
SM_BAT_SDA2
SM_BAT_SCL2
LIDR#
EC_IMVP_PD_IN#

R334
R306
R430
R305
R133
R138
R129
R125
R401
R127

PCIE_WAKE#_EC
ALT_ON
PWRSW#
EC_IMVP_PD_OUT
TPCLK
TPDAT

R393 10K
R147 10K
R163 10K
R123 10K
R140ns 10K
R142 10K

0 R0402 ns
0 R0402

+V3.3AL

10K R0402
10K R0402
10K R0402
10K R0402
4.7K R0402
4.7K R0402
5.6K R0402
5.6K R0402
10K R0402
10K R0402

ns
ns
ns
ns

ns

R0402
R0402
ns
R0402
R0402
ns
R0402
R0402
ADD R140 R142
leixy 090824

EC_MAIN_PWROK 15

ICH_PWROK from EC
Swain 080819

15

SDA1/GPIO47
SCL1//GPIO46
SDA0/GPIO45
SCL0/GPIO44

GPXIOA00/SDICS#
GPXIOA01/SDICLK
GPXIOA02/SDIMOSI
GPXIOA03
GPXIOA04
GPXIOA05
GPXIOA06
GPXIOA07
GPXIOA08
GPXIOA09
GPXIOA10
GPXIOA11

80
79
78
77

97
98
99
100
101
102
103
104
105
106
107
108

GPXIOD0/SDIMISO
GPXIOD1
GPXIOD2
GPXIOD3
GPXIOD4
GPXIOD5
GPXIOD6
GPXIOD7

109
110
112
114
115
116
117
118

MISO
MOSI
SPICLK/GPIO58
SPICS#

119
120
126
128

XCLK32K/GPIO57
XCLKI
XCLKO

121
122
123

I2C_DATA
I2C_CLK
SM_BAT_SDA2
SM_BAT_SCL2

7
7
28
28

R308
4.7K
R0402

GPXIOA00
CHG_LED#
R0402 0

R418

+V3.3AL

8
EC_SPI_HOLD# 7
EC_SPI_SCK
6
EC_SPI_MOSI
5

23

PM_PWRBTN# 15
AMP_SHDW 22
EC_IMVP_PD_OUT 35
CHG_ON
36

VCC
HOLD#
CLK
D

EC_PM_SUS_STAT#
R0402 0
PCB_Mark0
PCB_Mark1
PCB_Mark2
EC_BUF_PLT_RST#
R0402
R0402
R0402
R0402

0
0
0
0

R425
R296
R427
R428

R420
1K
R0402

R419

VDD

EC_SPI_WP#

WP#

EC_SPI_HOLD#

HOLD#

PM_SUS_STAT# 12,15
+V3.3AL

EC_SPI_MISO
EC_SPI_MOSI
EC_SPI_SCK
EC_SPI_CS#

32XCLKI
32XCLKO

23

ns
SI
SO
CE#
SCK

5
2
1
6

VSS

EC_SPI_MOSI
EC_SPI_MISO
EC_SPI_CS#
EC_SPI_SCK

colay small package EC

C164
18pF/50V,NPO
C0402

ns

C296
1uF/10V,X7R
C0603

U20
W25X40
SO8_50_150

+V3.3AL

LVDS_BKLTEN 7,12
EC_IMVP_PD_IN# 35

BT_PWRON

EC_SPI_CS# R309 4.7K R0402

EC_SPI_MISO
EC_SPI_WP# R307 4.7K R0402

U13
W25Q80BV
SOIC8_50_208

PROCHOT#
HW_OFF_BKLT# 12
CAM_PWRON 12
BTL_LED#
23

1
2
3
4

CS#
Q
W#
VSS

091028

32XCLKI

R151
10M
Y1
R0402
32.768KHz
xd3_2X6

C167
18pF/50V,NPO
C0402

32XCLKO

090604

GND
GND
GND
GND
GND
113
94
35
24
11

AGND
69

1
A

R417 10K R0402

HDD_ZOUT
HDD_YOUT
HDD_XOUT

Assy

+V5S
Q24
2N7002E-T1
SOT23
EC output Signal!
ns
PROCHOT#
3

28
29
26
27

CLK

33
V1_5S_ON
19 EC_DEBG_UTXD
19 EC_DEBG_URXD
29 ALW_PWROK
31 V1.8S_ON
15 PM_BATLOW#
31 V0_89S_ON

GPO3C
GPO3D
GPO3E
GPO3F

GPXIOA00

PM_SLP_S3#

ns

FANFB0/GPIO14
FANFB1/GPIO15
FANPWM0/GPIO12
FANPWM1/GPIO13

SPI

LABEL1
Topstar Soft
BIOS Ver: X.XX
EC Ver: X.XX
BIU configuration
should match flash XXXXXXXX
speed used
EC/BIOS Label
740601900104

30
29
33
30

GPIO04
GPIO07/i_clk_8051
GPIO08/i_clk_peri
GPIO0A
GPIO0B/ESB_CLK
GPIO0C/ESB_DAT_O/ESB_DAT_I
GPIO0D
GPIO18
GPIO1A/NUMLED#
GPIO40
GPIO41
GPIO50
GPIO59/TEST_CLKSPICLKI

68
70
71
72

HDD_ZOUT
HDD_YOUT
HDD_XOUT

C111
100pF/50V,NPO
C0402

36

BTL_BEEP
22
POWERLED# 23
SET_I
36
EC_BKLT_PWM 12

GPXIOD

R423
10K
R0402

R449
10K
R0402
ns

R402 1K R0402
6
12,21
LIDR#
R391
0 R0402 PCIE_WAKE#_EC14
15,19,26 PCIE_WAKE#
ns
15
27
AC_IN
16
28
BATT_IN#
17
15,32 PM_RSMRST#
R387 1K R0402 18
21
PWRSW#
19
15,32 PM_SLP_S3#
32
15,34 PM_SLP_S4#
R0402 0
R360
36
15 SYS_RST#
73
8,30,32 DDR3_DRAM_PWROK
R374 1K R0402 74
35
IMVP_ON
89
24
ALT_ON
127
31
V1_05S_ON

C144
0.1UF/10V,X5R
C0402

+V3.3AL

GPXIOA

+V3.3AL

VerA
VerB

C157
0.1UF/10V,X5R
C0402

PM_SLP_S4#

R0402 EC_BUF_PLT_RST#

C126
0.1UF/10V,X5R
C0402

R424 0

9,15,19,26 BUF_PLT_RST#

KB3926

R0402

Connect PLTRST to EC_PCI_RST#

Swain 080819

GPIO

EC_PCI_RST#

KB

R396 4.7K R0402

ns
EC_BUF_PLT_RST# R399 0

MSIC

62
61
60
59
58
57
56
55

8051

+V3.3AL

SYS_I_Sense

21
23
25
34

SMBUS

CNS26_1_R_UP
Econn
KBCON1

SCANIN7
SCANIN6
SCANIN5
SCANIN4
SCANIN3
SCANIN2
SCANIN1
SCANIN0

EC_PCI_RST#

15 PM_CLKRUN#

63
64
65
66

C159
0.1UF/10V,X5R
C0402

C151
1uF/10V,X7R
C0603

PWM0/GPIO0F
PWM1/GPIO10
PWM2/GPIO11
PWM3/GPIO19

PS2

SCANOUT15
SCANOUT14
SCANOUT13
SCANOUT12
SCANOUT11
SCANOUT10
SCANOUT9
SCANOUT8
SCANOUT7
SCANOUT6
SCANOUT5
SCANOUT4
SCANIN0
SCANOUT3
SCANIN1
SCANIN2
SCANOUT2
SCANOUT1
SCANIN3
SCANIN4
SCANIN5
SCANOUT0
SCANIN6
SCANIN7

PCICLK
SERIRQ
LFRAME#
LAD0
LAD1
LAD2
LAD3
PCIRST#/GPIO05
CLKRUN#/GPIO1D

AD0/GPI38
AD1/GPI39
AD2/GPI3A
AD3/GPI3B

FAN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

12
3
4
10
8
7
5
13
38

C160
0.1UF/10V,X5R
C0402
ns

Should have a 0.1uF capacitor close to every

GND-VCC pair + one larger cap on the supply.

U17

PWM

27
28

1
2
3
4
27 5
28 6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

6 PCI_CLK_EC
15 INT_SERIRQ
15,19 LPC_FRAME#
15,19
LPC_AD0
15,19
LPC_AD1
15,19
LPC_AD2
15,19
LPC_AD3

GA20/GPIO00
KBRST#/GPIO01
SCI#/GPIO0E
ECRST#

C102
0.1UF/10V,X5R
C0402
ns

LPC

H_RCIN#

1
2
20
37

EC_RESET#

C150
10UF/6.3V,X5R
C0805

C152
0.1UF/10V,X5R
C0402

ADC

15

A20GATE
RCIN#
14 EC_RUNTIME_SCI#

D35
1N4148WS RCIN#
EC Output Signal!
SOD323

+V3.3AL

V18R

C125
0.01uF/25V,X7R
C0402

+V3.3S

R359
10K
R0402
ns
1

R136
0
R0805

V18R

C122
0.1UF/10V,X5R
C0402

67

R137
10K
R0402

090909

C114
0.1UF/10V,X5R
C0402

Q3
MMBT3904-F
SOT23

124

del 2n7002

100,1%
1
R0402

V18R

R141

AVCC

D37
1N4148WS A20GATE
SOD323
EC Output Signal!

H_A20GATE

FB9
120ohm@100MHz,500mA
FB0603
EC_V3.3AL
1
2

EC_RESET#

15

C142
4.7UF/10V,Y5V
C0805

R367
8.2K
R0402

R128
10K
R0402

KB3310B

TOPSTAR TECHNOLOGY
Swain Xu()

R406 0

The 0ohm RES will across the isolate

island of anolog GND and digital GND

R0402

R120 0

R0603

Page Name

KBC(KB3310B)

Size Project Name

Custom

P01

Rev
A

of
Friday, April 30, 2010
25
39
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3AL
+V3.3S

VDD3D3_LAN

VCC
NC1
NC2
GND

8
7
6
5

FB18
1

+V3.3AL

C63
0.1uF/10V,X5R
C0402

FB0805
2

300ohm@100MHz,2A
FB17
ns 1

+V3.3S

Place close to VDD33_LAN PINS.

300ohm@100MHz,2A

C36
0.1uF/10V,X5R
C0402

C34
0.1uF/10V,X5R
C0402

C55
0.1uF/10V,X5R
C0402

C61
0.1uF/10V,X5R
C0402
ns

MDIP0
MDIN0
AVDD10_1
MDIP1
MDIN1
AVDD10_2(NC)
MDIP2(NC)
MDIN2(NC)
AVDD10_3(NC)
MDIP3(NC)
MDIN3(NC)
AVDD33_4(NC)

DVDD10_1
SMBCLK(NC)
SMBDATA(NC)
CLKREQB
HSIP
HSIN
REFCLK_P
REFCLK_N
EVDD10
HSOP
HSON
GND

REGOUT
VDDREG_2
VDDREG_1
ENSWREG
EEDI/SDA
LED3/EEDO
EECS/SCL
DVDD10_2
LANWAKEB
DVDD33_1
ISOLATEB
PERSTB

C59
C60

C245
4.7uF/10V,X5R
C0805

C259
0.1uF/10V,X5R
C0402

R79 0 R0402 ns
EEDI/AUX R692 10K R0402
EEDO
EECS
R693 10K R0402
VDD10
VDD3D3_LAN

PCIE_WAKE# 15,19,25

Place close to VDD10 PINS.

R76 1K R0402 +V3.3S

R77 15K R0402

BUF_PLT_RST# 9,15,19,25

R92 0

R0603

C466
C467
C0805
C0402
4.7uF/10V,X5R0.1uF/10V,X5R

C262
0.1uF/10V,X5R
C0402

C266
0.1uF/10V,X5R
C0402

G3
G4
G5
G6
G7

4.7uH/1.22A
LS2_3513

0.1UF/10V,X7RC0402
0.1UF/10V,X7RC0402

C261
0.1uF/10V,X5R
C0402
ns

R91 0

C40
1uF/10V,X5R
C0402

C62
0.1uF/10V,X5R
C0402

C46
27pF/50V,NPO
C0402

LAN_TX0+

VDD3D3_LAN

N4
N3

N2
N1

5
4

TD-

TX-

TX0+
MCT1
TX0-

11

TDC

CMT

LAN_TX0-

10

TD+

TX+

LAN_TX1+

15

RD-

RX-

TX1+

14

RDC

RXC

MCT2

16

RD+

RX+

TX1-

1CT:1CT
1CT:1CT

LAN_TX1C223
0.01uF/25V,X7R
C0402

PCIE_WAKE# R689 10K

R0402

CLKREQ#

R0402

R691 10K

1
3
5
7

R0402 2.49K,1% R59

TX0+
TX0TX1+
TX1-

VDD3D3_LAN

4
3
2
1

L2+
L2L1+
L1-

L3+
L3L4+
L4-

RJ45_TX0+
RJ45_TX0RJ45_TX1+
RJ45_TX1-

5
6
7
8

RJ45_TX1MCT4

1
2
3
4
5
6
7
8

TX0+
TX0TX1+
TX2+

TX3+
TX3-

330pF/50V,X7R C0402

C11

4.7uF/10V,Y5V

C6

330pF/50V,X7R C0402

10
MCT4

MCT3

MCT2
R8
75
R0402

R7
75
R0402

R217
75
R0402

C10
1000pF/2000V
C1206

330pF/50V,X7R C0402
LAN_TX0+

LAN_TX0-

CASE_GND
CASE_GND

R216
75
R0402

TOPSTAR TECHNOLOGY
<OrgAddr1>

C0805

C7

MCT1

R0603

C8

CASE_GND

0 ns

LAN_TX1-

R6
A

TX0+
TX0TX1+
TX2+
TX2TX1TX3+
TX3-

TX2TX1-

C39
0.1uF/10V,X5R
C0402

LD1
AZC099-04S
ns

J4
RJ45
RJ45_SB

RJ45
RJ45_TX0+
RJ45_TX0RJ45_TX1+
MCT3

100MHz0.5A
CMC8

LAN_TX1+

PINS

CASE_GND

CHK2
ns

10K ohm close to Host side

RSET

RN1
0x4
RA0603_8
2
4
6
8

U11
TRAN16_50_272

13
12

R0603

Place close to EVDD10

C265
0.1uF/10V,X5R
C0402

EVDD10

Y2
25MHz
XS2_3D3
1
2
C50
27pF/50V,NPO
C0402

VDD10

L2
REGOUT

G9
G8

VDD10
CLKREQ#
PCIE_TXP0_LAN
PCIE_TXN0_LAN
CLK_PCIE_LAN
CLK_PCIE_LAN#
PCIE_RXP0_LAN
PCIE_RXN0_LAN

C279
0.1uF/10V,X5R
C0402

R0603

R78
0
R0402

REGOUT
VDDREG

G3
G4
G5
G6
G7

QFNS48_0D4_1G

G9
G8

36
35
34
33
32
31
30
29
28
27
26
25

VDDREG
R90 0

XTAL2

1
2
3
4
5
6
7
8
9
10
11
12

VDD3D3_LAN

FB0805
2

VDD3D3_LAN

XTAL1

G1
G2

AVDD33_3
AVDD33_2
RSET
AVDD10_5
CKXTAL2
CKXTAL1
AVDD33_1
DVDD10_3(NC)
LED0
DVDD3_2
GPO/SMBALERT
LED1/EESK

G1
G2

14
14
6
6
14
14

ns

CS
SK
DI
DO

93C46
so8_50_150

13
14
15
16
17
18
19
20
EVDD10 21
22
23
24

LAN_TX0+
LAN_TX0VDD10
LAN_TX1+
LAN_TX1-

U5

12,14,15,16,18,19,21,23,25,27,28,29,30,31,32,33,35
6,7,9,10,11,12,13,14,15,16,17,19,21,22,23,24,25,31,32,33,34,35

48
47
46
45
44
43
42
41
40
39
38
37

U4

1
2
3
4

EESK

EECS
EESK
EEDI/AUX
EEDO

R89
1K
R0402

VDD3D3_LAN

VDD3D3_LAN
VDD3D3_LAN
RSET
VDD10
XTAL2
XTAL1
VDD3D3_LAN

VDD3D3_LAN

Page Name

RTL8101E/8111C(GLAN)

Size
A3

P01

Project Name

Rev
A

Date:
Friday, April 30, 2010
Sheet
26
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained with the
expressed written consent of TOPSTAR
1

BATT+
+V3.3AL
+VDC
AD+

PR177
30K

R0402
S_Bot

R0402
200KS_Bot

PD19
1

PFB4

AD-2

5A

3
2
1

SBM54PT
SMB

100ohm@100MHz,3A
FB0805

SHLD1
AD-1

PR16
0.025,1%
R2512

AD+

3A

ns

1
SBM54PT
SMB
21,36 Isense_SYSP

100ohm@100MHz,3A
FB0805
PC113
1uF/25V,Y5V
C0805

PC114
1uF/25V,Y5V
C0805

BATT+

PD2
SSM34PT
SMA

PC13
0.1uF/25V,Y5V
C0402

5A
GND

1
2
3

090915 240mil

PQ7
S
AO4419
SO8_50_150 G

0 R0402
0 R0402
0 R0402

5A

8
7
6
5

PR54

PC37
0.01uF/25V,X7R
C0402

510K
R0402

Jack_GND

+VDC

PR3 ns
PR5 ns
PR4 ns

5A

5
6
7
8

28,32,36 Isense_SYSN

connect Jack_GND to

PC40
0.1uF/25V,X7R
C0603
+V3.3AL

PR174
510K
R0402

PQ44
2N7002
SOT23

28,32

PR175
510K
R0402

AC_IN

PC116
C0402

PQ11
2N7002
SOT23

SHDN#

0815VB:Change PR9 to 51K

Update PR175 TO 30k

bobo100315

PR55
100K,1%
R0402

ns

PR62
51K
R0402

AD+

1000pF/50V,X7R

update PJ1 as N02

100315

SHLD2

PD20
1

3A

PQ4
AO4419
SO8_50_150

PFB3

29

3A

ALW_EN

PC115
0.1uF/25V,X7R
C0603

AD+
PF2
7A
FUSE1206
1
2

PR17
10
R0402

PR176

ALW_EN
PJ1
DC JACK 5P
PWR5P_DC3

28,33,36
12,14,15,16,18,19,21,23,25,26,28,29,30,31,32,33,35
12,19,21,29,30,31,32,33,34,35
33

PR178
47K
R0402

PR179
1K
R0402

25
PR60
100K
R0402

PC46
1000pF/50V,X7R
C0402

TOPSTAR TECHNOLOGY
Liu JX
Page Name

ADAPTER IN

Size
A3

P01

Project Name

Rev
A

Date:
Friday, April 30, 2010
Sheet
27
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

BATT+
+V3.3AL

PFB2

5A

PFB1

PC20
1000pF/50V,X7R

25 SM_BAT_SDA2
25 SM_BAT_SCL2

Battery connector

100ohm@100MHz,3A
1
2 FB0805

5A

100ohm@100MHz,3A
1
2 FB0805

PF1
7A
FUSE1206
1
2

GND_BAT

1
C9
0.1uF/25V,Y5V
C0402
ns
2

GND_BAT

SM_BAT_SDA2

PR7

100 R0402

SM_BAT_SDA

SM_BAT_SCL2

PR10 100 R0402

SM_BAT_SCL

BATT+

BATCON1

GND

GND

25

SM_BAT_SDA

GND_BAT

BATT_IN#

PC5
0.1UF/10V,X5R
C0402

GND_BAT
1K

PZD2
SOT23
BAT54S

+V3.3AL
BAT_CON_1X5

PR213
47K
R0402
PR215
R0402

KEY
SDAT
SCLK

+V3.3AL

PR202
510K
R0402

BATT+

1
PQ56
2N7002
SOT23

PC145
1000pF/50V,X7R
C0402

BATT+

27,33,36
12,14,15,16,18,19,21,23,25,26,27,29,30,31,32,33,35

PZD1
+V3.3AL SOT23
BAT54S

PR216
510K
R0402

2
PC3
0.1UF/10V,X5R
C0402

SM_BAT_SDA2

SM_BAT_SCL

SM_BAT_SCL2
GND_BAT
PR15 0 R0402 ns
PC4
5.6pF/50V,NPO
C0402

PC6
5.6pF/50V,NPO
C0402

PR11 0 R0402 ns
PR6

GND_BAT

GND_BAT

0 R0402

,240mils.

ns
GND_BAT

GND_BAT

TOPSTAR TECHNOLOGY
Liu JX
Page Name

BATTERY IN

Size
A3

P01

Project Name

Rev
A

Date:
Friday, April 30, 2010
Sheet
28
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

+V3.3AL
+VDC
AD+
+V5AL
EC_RTC

12,14,15,16,18,19,21,23,25,26,27,28,30,31,32,33,35
12,19,21,27,30,31,32,33,34,35
27,33
12,16,21,30,31,32,33
15

1.MOSFET

+V3.3AL

PR253
51K
R0402
S_Top

2A
GND_TPS51125

T
5.11K,1%

PR56

ENTRIP1

LL2

12

DRVL2

G2

GND2

21

LL1

20

DRVL1

19

C0603

PQ85
AO4468
SO8_50_150
4

5
6
7
8

VFB1

ENTRIP1

DRVH1

PC252
0.1uF/25V,X7R

+V5AL

PR240

PL17
5.2uH/5.5A
LS2_1051
S_Bot

3
2
1
4.7

PR243
10K
R0402

LL2

5
6
7
8
0
R0402

PQ86
AO4468
SO8_50_150

GND_TPS51125

3
2
1

VREG5

VCLK
18

17

VIN

GND

PR249

PR254

3A

Isense_SYSN {43}

PC194
4.7uF/10V,X5R
C0805

VREF

PR58
510K
R0402

PR99
100K
R0402

BAT54C
SOT23

GND_TPS51125

C0402
ns

PC190
220UF/6.3V,OSCON
CAP6_6x7_3

PC139
1000pF/50V,X7R
C0402
B

PR232
1K
R0402

ns
VREG5

PR209
1K
R0402

PZ17
BZT52C5V6S-F/5.6
SOD323
ns

PC190
4.2
090723

ENTRIP1
PR207
47K
R0402
S_Top

PC57
0.022uF/16V,X7R
C0402
ns

PR204
1K
R0402

GND_TPS51125

PC146
0.1uF/25V,Y5V
C0402
ns
1

PC154
0.1uF/25V,Y5V
C0402
ns

0 R0402
ns

PQ84
2N7002
SOT23

1
2

PR255

1000pF/50V,X7R

PC195
10uF/6.3V,X5R
C0805

V5AL
TestP
TPC60
ns

5A

PQ81
MMBT3904-F
2

PC144

PD33
1N5819
SOD123
S_Top

5A

VREG5

PC239
4.7uF/25V,X7R
C1206

PR261
2.2
R0805
ns
1

16

G1

15

GND1

GND_TPS51125

PD12

VBST1

22

R0402

19,21 PWR_SW_VCC2

PR251

SKIPSEL

R0402

EN0

PR247

14

G2

PD10
1N4148WS
SOD323

ALW_EN

23

11

Update PC245 to 533115722001 for Buyer request

090917

27

PGOOD

PU9
RT8205B
S_Top

13

3
S2

PC153
1000pF/50V,X7R
C0402
ns

ALWAYS_ON

24

DRVH2

VO1

VBST2

10

VREF

VREG3

TONSEL

4.7

VO2

PR246

D2

4.7uF/25V,X7R

PD32
1N5819
SOD123
ns

25

ENTRIP1

+ PC245
220UF/6.3V,OSCON
CAP6_6x7_3

PR260
2.2
R0805
ns

VREF

1
2

PL13
3.3uH/4.8A
LS2_8836

6
2

1
7

C0603
PR250
10K
R0402

R0402

8
1G

15K,1%
R0402

D1

PC143
4.7uF/25V,X7R
C1206

PC253
0.1uF/25V,X7R

S1

PC147
1000pF/50V,X7R
C0402

D1

PC242
10uF/ 25V,X7R
C1210

EC_RTC

PQ75
AO4932
SO8_50_150

R0402

PC188
0.1uF/25V,X7R
C0603

ENTRIP2

10uF/6.3V,X5R
C0805

PR203
10K,1%
PC78
0.22uF/16V,X7R
C0603

R0402

PC193

V3.3AL
TestP
TPC60
ns

7.68K,1%
PR248

GND_TPS51125

+V3.3AL

PC243
1000pF/50V,X7R
C0402

PR51
PR252

PC189
1000pF/50V,X7R
C0402

VFB2

PC244
0.1uF/25V,X7R
C0603

PR272
100K

PZ16
BZT52C3V6S-F/3.6
SOD323
ns

+VDC

2A
PC211
10uF/ 25V
C1210

PC241
C1206

3.Thermal
GND5,
4.

25 ALW_PWROK

+VDC
VDC2
TestP
TPC60
ns

5A

2.MOSIC

0
R0402

PR231
30K
R0402

GND_TPS51125
TOPSTAR TECHNOLOGY
Liu JX
Page Name
Size Project Name
Custom

+V3.3AL/+V5AL
Rev
A

P01

Date:
Thursday, April 29, 2010
Sheet
29
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V0.75S
+V5AL
+V3.3AL
+VDC
+V1.5
+V3.3S

13,34
12,16,21,29,31,32,33
12,14,15,16,18,19,21,23,25,26,27,28,29,31,32,33,35
12,19,21,27,29,31,32,33,34,35
8,10,13,32,33,34
6,7,9,10,11,12,13,14,15,16,17,19,21,22,23,24,25,26,31,32,33,34,35

+V5AL
+V3.3AL
D

+VDC

TRIP

DRVH

EN

SW

PR50
10K

AO4468
PQ53
SO8_50_150

TPC60

5A

5
6
7
8
4

11

PC72
4.7uF/10V,X5R
C0805

PC63
C0402
0.1uF/10V,X7R

PQ54
AO4468
SO8_50_150

PR262
2.2
R0805
ns

290K

PD25
SSM34PT
SMA

PC135
1000pF/50V,X7R
C0402
ns

5A

+
PC136
220UF/6.3V,OSCON
CAP6_6x7_3

3
2
1

DRVL

PR86
470K
Set Fsw

GND

RF

V5IN

PR200
0
R0402

VFB

PR80
10K,1%

ns

PC59
0.022uF/16V,X7R
C0402
ns

2A

V1_5
TestP

PL7
2.2UH/14A
LS2_6530
1

PR940
100K
R0402

PC61
1000pF/50V,X7R
C0402

+V1.5

PR201
0
R0402

PC56
4.7uF/25V,X7R
C1206

10

3
2
1

1K

VBST

PR195
R0402

PGOOD

V1_5_ON

130K
R0402

25

PC248
0.1uF/25V,X7R
C0603

TPS51218

8,25,32 DDR3_DRAM_PWROK

PC62
0.1uF/25V,X7R
C0603

5
6
7
8

tps51218
PU10

PR194
1K
R0402
S_Top

R940

PR193
0
R0402

PZ2
BZT52C2V0S-F/2.0V
SOD323
ns

Update PD13 to 1N5819 for EMI request

090917
PR263
11.5K,1%

PC60
0.022uF/16V,X7R
ns
C0402

PR68
20K
R0402

ns

PU7
AP1250
SOP8_1D27_4G

VIN

NC3

GND

NC2

VCNTL

NC1

REFEN

VOUT

PR100
10K,1%

+V3.3AL

PC65
4.7uF/10V,X5R
C0805

PC64
0.1UF/10V,X7R
C0402

PR98
10K,1%

4.7uF/10V,X5R

PC66
C0805

PGND

2A

+V1.5

PC67
0.1UF/10V,X7R
C0402

+V3.3AL

PR112
1K
R0402
V0_75S_ON

3
PQ24
MMBT3904-F

25

PR110
30K
R0402

PQ22
2N7002
SOT23

V0_75S
ns
TestP
TPC60

PR106
47K
R0402

+V0.75S

2A
PC70
10uF/6.3V,X5R
C0805
ns

PC69
10uF/6.3V,X5R
C0805

PC76
C0402
0.1UF/10V,X5R
ns

TOPSTAR TECHNOLOGY

Mayc

Liu JX
Page Name

+V1.5/+V0.75S DDR

Size
A3

P02

Project Name

Rev
A

Date:
Friday, April 30, 2010
Sheet
30
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3AL
+V3.3S
+VDC
+V1.5S
+V1.05S
+V5AL
+V0.89S
+V1.8S
+V5S

12,14,15,16,18,19,21,23,25,26,27,28,29,30,32,33,35
6,7,9,10,11,12,13,14,15,16,17,19,21,22,23,24,25,26,32,33,34,35
12,19,21,27,29,30,32,33,34,35
10,14,16,19,23,33,34
6,7,10,15,16,24,32,34
12,16,21,29,30,32,33
10,34
10,32
11,12,16,17,21,22,23,25,33,34,35

+V5S

+VDC

1.5A

+V3.3S

PC68
C1206
4.7uF/25V,X7R

DRVL

8
G1

PL6

PL15
2.2UH/14A
LS2_6530

S1

PR183
0
R0402

080716VA:Co_lay.

D2

+V0.89S
V0_89S
TestP
TPC60
PD23
ns
SOD323
BZT52C2V0S-F/2.0V
ns

3
G2

PC49
4.7uF/10V,X5R
C0805

PD30 PR265
1N5819 2.2
SOD123 R0805
ns
ns

S2

PC127
C0402
0.01uF/25V,X7R
ns

2A

ns

PU11
AP1250
SOP8_1D27_4G

2A

+V3.3S

PC126
0.1uF/10V,X5R
C0402

PR226
10K,1%
R0402
PC45
4.7uF/10V,X5R
C0805

PC138
220UF/6.3V,OSCON
CAP6_6x7_3
PC55
0.1UF/10V,X7R
C0402

PR57
2.74K,1%

PC42
0.022uF/16V,X7R
ns
C0402

PR53
20K
R0402

VIN

NC3

GND

NC2

REFEN

VCNTL

VOUT

NC1

PR228
12.1K,1%

PC71
0.1UF/10V,X7R
C0402

Update PC138 to 533115722001 for Buyer request

090917

PGND

RF

V5IN

PR257
10K
R0402

VFB

SW

DRVH

3.3uH/4.8A
LS2_8836

EN

tps51218
PR266
470K
R0402

PR79
10K,1%
R0402

+V3.3AL

PC53
0.1uF/25V,X7R
C0603

PC73
0.022uF/16V,X7R
C0402
ns

TRIP

PQ6
AO4932
SO8_50_150

PR942
100K
R0402

D1

100K,1%
R0402

GND

PR264

V0_89S_ON

J7
JOPEN
RESISTOR_1
ns

VBST

D1

PR234
1K
R0402

0 R0402
25

PGOOD

10

ns

32 +V1.05SPWROK

PC51
1000pF/50V,X7R
C0402

TPS51218

11

PR236

PU14

32 +V0.89SPWROK

PC249
0.1uF/25V,X7R
PR190 C0603
PR189
0
0
R0402
R0402

+V3.3AL

PC75
4.7uF/10V,X5R
C0805

PR89
47K
R0402
ns

ns
TPC60
TestP
V1_8S
ns
PR224
47K
R0402
S_Bot
0
R0402
ns

PR227

PQ80
MMBT3904-F

R0402 1K

32 +V1.05SPWROK

2A

PQ83
L2N7002LT1G
SOT23

1
PC152
0.1UF/10V,X5R
C0402
ns
1

V1.8S_ON

PR256
25

+V3.3AL

PC50
10uF/6.3V,X5R
C0805

+V1.8S

PC52
10uF/6.3V,X5R
C0805

ns

PR225
30K
R0402

+V5S
+VDC

1.5A

+V3.3S
PC250
0.1uF/25V,X7R
C0603

R0402

TPS51218
2

TRIP

DRVH

EN

SW

V5IN

DRVL

5
6
7
8
D

PR87
10K,1%
R0402

RF

PR268
tps51218
470K
R0402

GND

11

VFB

PC79
4.7uF/10V,X5R
C0805

+V3.3AL

080716VA:Co_lay.

R938
2.2
R0805

PQ70
AO4468
SO8_50_150

+V1.05S

PL5

PD31
1N5819
SOD123
1

PC123
0.022uF/16V,X7R
C0402
ns

PR237
0
R0402

J8
JOPEN
RESISTOR_1
ns

PR943
100K
R0402

PR197
1K
R0402

V1_05S_ON

PR258
10K
R0402

R0402
25

PL11
2.2UH/14A
LS2_6530 ns

PQ68
AO4468
SO8_50_150

5
63
72
81

130K

3.3uH/4.8A
LS2_8836

ns

PC140
220UF/6.3V,OSCON
CAP6_6x7_3

10

PC131
4.7uF/25V,X7R
C1206

PC74
1000pF/50V,X7R
C0402
ns

VBST

PR267

PGOOD

PC137
0.1uF/25V,X7R
C0603

PC77
1000pF/50V,X7R
C0402

PR198
0
R0402

3
2
1

32 +V1.05SPWROK

PR187
0

PU3

PR90
47K
R0402
S_Top

PC124
0.1uF/10V,X5R
C0402

4A
V1_05S
TestP
TPC60
ns
PD24
ns
SOD323
BZT52C2V0S-F/2.0V

PR69
5.11K,1%
R0402

PC41
0.022uF/16V,X7R
ns
C0402

PR43
20K
R0402

ns

TOPSTAR TECHNOLOGY
Page Name

1.8S 1.05S 0.89S

Size
A2

P02

Project Name

mayc

Rev
A

Friday, April 30, 2010

31
39
Date:
Sheet
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3S
6,7,9,10,11,12,13,14,15,16,17,19,21,22,23,24,25,26,31,33,34,35
+V5AL
12,16,21,29,30,31,33
+V3.3AL
12,14,15,16,18,19,21,23,25,26,27,28,29,30,31,33,35
+V1.05S
6,7,10,15,16,24,31,34
+V1.8S
10,31
+VCC_CORE 10,35
+V1.5
8,10,13,30,33,34
+VDC
12,19,21,27,29,30,31,33,34,35

Power Good Logic CIRCUIT

D

+V3.3S

PR130
47K
R0402
S_Top
PR81
1K
R0402

27,28

3
PD11
BAT54A
SOT23

MAIN_PWROK 25

PR128
1K
R0402

15,25 PM_SLP_S3#

3
2

PD13
BAT54A
SOT23

+V5AL

PC88
0.1uF/10V,X7R
C0402

+V3.3AL

PZ9
BZT52C5V6S-F/5.6
PQ66
SOD323
MMBT3904-F
2
1
SOT23

PZ8
BZT52C3V6S-F/3.6
SOD323
PC203
1uF/10V,X7R
C0603

15,25 PM_RSMRST#

0
R0402

1
PR304
100
R0402

PQ112
MMBT3904-F
SOT23

PQ69
MMBT2907
SOT23

1
2

PR307
24 SHDN_LOCK#

PR320
51K
R0402

PR323
100
R0402

8,25,30 DDR3_DRAM_PWROK

31 +V1.05SPWROK

SHDN#

31 +V0.89SPWROK

PR313
20K
R0402

PC217
0.1uF/16V,X7R
C0402

TOPSTAR TECHNOLOGY
Liu JX
Page Name

Power Good logic/OVP

Size
A3

P02

Project Name

Rev
A

Date:
Thursday, April 29, 2010
Sheet
32
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+VDC
+V5S
+V3.3S
+V5AL
+V3.3AL
+V1.5S
+V1.5
AD+
BATT+

12,19,21,27,29,30,31,32,34,35
11,12,16,17,21,22,23,25,31,34,35
6,7,9,10,11,12,13,14,15,16,17,19,21,22,23,24,25,26,31,32,34,35
12,16,21,29,30,31,32
12,14,15,16,18,19,21,23,25,26,27,28,29,30,31,32,35
10,14,16,19,23,34
8,10,13,30,32,34
27
27,28,36

+VDC
+V3.3AL

PC162
0.01uF/25V,X7R
C0402

PC80
0.1uF/25V,X7R
C0603

SOT23

4A

3
2
1

5
6
7
8
3
2
1

PC81
SO8_50_150
0.1uF/25V,X7R
C0603

+V3.3S

PC166
1uF/10V,X7R
C0603

PC179
1uF/10V,X7R
C0603

PR275
0
R0402

+V1.5

5
6
7
8

PD34
1N4148WS
SOD323

V1_5S_ON

PR277
25

20K ns
R0402

1
PR244
100K
R0402
ns

PQ18
MMBT3904-F
SOT23
ns

2A

SO8_50_150

ns

+V1.5S

PC149
0.1UF/25V,X7R
C0603

PQ65
2N7002
SOT23
ns
1

PR273
100K
R0402
ns

V1_5S
TestP
TPC80

AO4468
PQ34

3
2
1

PR141
100K
R0402

+VDC

PR205
510K
R0402

AO4468
PQ52

SO8_50_150

1
PR278
1K
R0402

PR276
51K
R0402

V5S1
TestP
TPC60
ns
+V5S

AO4468
PQ55

MAIN_PWR_DN

MAIN_ON

PR173
33K
R0402

V3_3S1
TestP
TPC60
ns

PQ51
2N7002
25

34

PR245
51K
R0402

PR208
100K
R0402

PR206
1K
R0402

PD27
1N4148WS
SOD323
1

+V5AL

5
6
7
8

PQ50
DTB114EK
SOT23

PR172
100K
R0402

PR274
1K
R0402

PC148
1uF/10V,X7R
C0603

PR241
100K
R0402
ns

TOPSTAR TECHNOLOGY
Liu JX
Page Name
Size
A3

Project Name

V5S/ V3.3S/ V1.5S Power

P02

Rev
A

Date:
Thursday, April 29, 2010
Sheet
33
of
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

+V3.3S
+V1.05S
+V1.5S
+V1.5
+V0.75S

6,7,9,10,11,12,13,14,15,16,17,19,21,22,23,24,25,26,31,32,33,35
6,7,10,15,16,24,31,32
10,14,16,19,23,33
8,10,13,30,32,33
13,30

+VDC
+V5S
+V0.89S

12,19,21,27,29,30,31,32,33,35
11,12,16,17,21,22,23,25,31,33,35
10,31

+V1.5S
+V5S

PR214
100
R0402

PR222
100
R0402

PQ41
2N7002
SOT23

PQ64
2N7002
SOT23

PQ42
2N7002
SOT23

PR169
100
R0402

PR168
100
R0402

PQ61
2N7002
SOT23

PR171
100
R0402

+V0.89S

+V1.05S

70mA
2

100mA
PR170
100
R0402

PQ60
2N7002
SOT23

33

MAIN_PWR_DN

+V0.75S

+V1.5

+VDC

PR219
510K
R0402

V1_5DISCHG

PQ63
2N7002
SOT23

PR212
100
R0402

PR221
100
R0402

PR210

10K
R0402

PQ59
2N7002
SOT23

1V1_5DISCHG

1
2

15,25 PM_SLP_S4#

PQ62
2N7002
SOT23

PR217
100
R0402

+V3.3S

30mA

PR211
200K
R0402

TOPSTAR TECHNOLOGY
Liu JX
Page Name
Size
A3

Project Name

Discharge Circuit
P02

Rev
A

Date:
Thursday, April 29, 2010
Sheet
34
of
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

+VDC
12,19,21,27,29,30,31,32,33,34
+V5S
11,12,16,17,21,22,23,25,31,33,34
+VCC_CORE 10,32
+V3.3S
6,7,9,10,11,12,13,14,15,16,17,19,21,22,23,24,25,26,31,32,33,34
+V3.3AL
12,14,15,16,18,19,21,23,25,26,27,28,29,30,31,32,33

+VDC
+V3.3S
PR188
2.2

PC129
1000pF/50V,X7R
C0402

TPS51218
10

TRIP

DRVH

EN

SW

VFB

V5IN

RF

DRVL

PQ47
AO4468
SO8_50_150

3
2
1
5
6
7
8
3
2
1

1
2

AO4468
PQ48

tps51218
PR270
470K
R0402

PR97
10K,1%
R0402

4
PC134
4.7uF/10V,X5R
C0805

7A
+VCC_CORE

080716VA:Co_lay.

PL16

PC141
0.1UF/10V,X5R
C0402
ns

J9
JOPEN
RESISTOR_1
ns

PR259
10K
R0402
PR192
0
R0402

11

PR181
1K
R0402

2.2
R0402

+V5S

PR941
100K
R0402

PL12
2.2UH/14A
LS2_6530

IMVP_ON

25

200K
R0402

GND

PR196
PR269

3.3uH/4.8A
R939 LS2_8836
2.2
R0805 ns
PD26
PC142
SSM34PT220UF/6.3V,OSCON
SMA
CAP6_6x7_3

SO8_50_150

VBST

PGOOD

PC120
10uF/25V,X5R
C1210
ns

R0402

PC132
0.1uF/25V,X7R
C0603

R509 0

R0402

5
6
7
8

CK505_CLK_EN#

PU1

PC133
4.7uF/25V,X7R
C1206

PC251
0.1uF/25V,X7R
C0603

PR94
47K
R0402
S_Top

PC128
1000pF/50V,X7R
C0402

PC130
0.1uF/10V,X5R
C0402

VCORE
PD29
TestP
BZT52C2V0S-F/2.0V TPC60
SOD323
ns
ns

+V3.3AL
Update PC142 to POSTCAP
Swain 090708

PR131
5.62K,1%
R0402

Update PR185,PR158 to 2.2ohm,Install PR939,PC87

090917
PC43
0.022uF/16V,X7R
ns
C0402

+V3.3AL

PR44
20K
R0402

ns

+V3.3S

+V3.3S

PR114
20K
R0402
ns

+VCC_CORE

PR191
20K
R0402
ns

mayc

R510 0

PQ49
MMBT3904-F
SOT23
ns

EC_IMVP_PD_OUT 25

3
EC_IMVP_PD_IN# 25

6,15 CK505_CLK_EN#
PGOOD CLK_EN
090723

PR199
75K
R0402 ns

PQ74
2N7002
SOT23
ns

1
2

R0402

R0402

IMVP_PWRGD 9,15,25

R511 0

1
PC125
0.22uF/10V,X7R
C0603
ns

0812 for

CK505_CLK_EN# 6,15

PR182
10K
R0402
ns

PR180
20K
R0402
ns

PR113
20K
R0402
power sequence
ns

CK505_CLK_EN# Pull high to +3.3AL

Swain 080815

PC122
0.22uF/10V,X7R
C0603
ns

TOPSTAR TECHNOLOGY
Liu JX
Page Name

+VCC CORE

Size
A3

P01

Project Name

Rev
A

Date:
Thursday, April 29, 2010
Sheet
35
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

BATT+

PU2

PC35
1uF/10V,X7R
C0603
21,27 Isense_SYSP
PR37

PC25
0.1uF/25V,Y5V
C0402

27,28,32 Isense_SYSN

ACSET

PC36
0.1uF/25V,Y5V
C0402

VDD

19

CSIP

20

CSIN

DCIN

24

UGATE

17

ICOMP

ISL6251HAZ

BOOT

16

SSOP24_25_150
PR35
R0402

PC24
C0402

3.3V

11
3

CHG_ON

PR14
R0402
10K

2.39V_Vref

PR23
10K,1%
R0402

55mV/25m ohm=2.2A.

0.1 Vref

14

PGND

13

CSOP

21

CSON

22

CELLS

ICM

GND

12

D1

8
G1

3
G2

VREF

10

ACLIM

23

ACPRN

PR20
1K,1%
R0402

2Aphase

7
6

EN

CHLIM

PQ1
AO4932
SO8_50_150

S1

D2

PR18

SET_I

LGATE

D1

VDDP

1N4148WS/75V/150mA PR27
10K
SOD323
R0402

VADJ

PC7
1uF/10V,X7R
C0603

PR12
15.4K,1%
R0402
ns

PHASE

VCOMP

PC14
4.7uF/25V,X7R
C1206

070906VACo-lay

S2

PL1
15uH/3.6A
LS2_1040

PR185
50mOHM,1%
R2512

2A

8.4V
PC118
BATT+
0.1uF/25V,X7R
C0603

2A

R941
2.2
R0805
ns
PC150
C0402
1N5819
ns
SOD123
1000pF/50V,X7R
PD3
ns
PR47 2.2
R0402

Change from 10k to 6.98k 25

10K

CHG_GND

SET_I

0.01uF/25V,X7R

PC18
0.1uF/25V,Y5V
C0402
18

PC15
10uF/ 25V
C1210
ns

PD22

PC11
0.1uF/25V,X7R
C0603

27,28,32

PC27
5600pF/50V,Y5V
C0603

C0402

PC12
1000pF/50V,X7R
C0402

PD21
SOD323
1N4148WS/75V/150mA
ns
PR184
R0402

PR24
R0402

R0402
PC31
1000pF/25V,X7R

25

Isense_SYSN

10

1.5A

VDDP

PR186
5V_internal_LDO
4.7
R0402

15

VDDP

PC121
1uF/10V,X7R
C0603

CHG_GND

27,28,33

PC117

PC119
4.7uF/25V,X7R
C1206

10uF/ 25V
C1210
ns

VBATS1
TestP
TPC60
ns

PC34
1uF/25V,Y5V
C0805

PC32
1uF/10V,X7R
C0603

PR26
100
R0402

SYS_I_Sense

25

Layout note:
Far away from critical signal trace

PC19
3300pF/50V,X7R
C0402

0
R0402

CHG_GND

0V
0.2V
1V

0A
0.2A
1A

SYS_CURRENT SYS_I_Sense
>3.6A
>1.8V
<3A
<1.5V

CHG_GND
Change solution from OZ8602 to ISL6251

SYS_I_Trip
High
Low
TOPSTAR TECHNOLOGY
Page Name

CHARGER

Size
A3

P01

Project Name

Rev
A

Date:
Friday, April 30, 2010
Sheet
36
of
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

1B

2A 2B

BATT+

AD+

PD1

1A

3A 5B
+VDC

PWRSWVCC2
ALWAYS_ON

DDR_PWROK

DDR POWER
ISL6545

PWRSW#

6A

PM_SLP_S3#

8
8

PM_RSMRST#

TigerPoint

V1_8_ON

PM_SLP_S4#

13

5B 3A

ALW_PWROK

11
11

V0_9S_ON

+V1.8

13

MAIN_ON

10

APL5331

+V0.9S

DDR_PWG

MAIN_PWROK

16

CHIPPWROK

PU7

SET_I

PM_PWRBTN#
IMVP_ON

V0_89S_ON

PLT_RST#

14

+V1.05S
+V0.89S

V1_5S_ON

V1_05S_ON

+V2.5S

17

11
15

PM_SLP_S3#

6B

SYS_I_Sense
MAIN_PWROK
to IMVP_ON
Delay 100mS

SYS_I_Sense

+V3.3S

V1_5S_ON

13

APL5331

+V1.5S

+V1.5S

14

+VDC

Chipset PWR
ISL6545*2

AC_IN

Charge
ISL6251

BATT+

SET_I

H_PWRGD

CHG_ON

22
V1_05S_ON

CHIPPWROK

+V1.5S

20

15
B

17

PineViwe

12

KIA1117

14

PM_RSMRST# 5A

CHG_ON
ALWAYS_ON

+V5S

+V3.3S
+V5S

MAIN_ON 10

EC_KBC
KB3310B

VR_PWRGD_EN

ICH_POWGD

19

10

11

System Power
+V_S

DDR_PWG

4A 6B

22

ALW_EN

7B

21

+V3.3AL
+V5AL

2A

V1_8_PWROK

PWRSWVCC2

AD+

4B

Always_On
Power
ISL62382

PQ2

3B 5A

+V5_STBY
EC_RTC

ALW_PWROK

PQ1

IMVP_PWRGD

18

IMVP_ON

VR_PWRGD_CLK_EN

VCC_CORE
ISL6545

+VCC_CORE

19

Note:
*A:For adapter in
*B:For battery only
* :For all

Clock
CK410M

VR_PWRGD

19

CLK_EN

19

MAIN_PWROK

H_PWRGD

20

IMVP_PWRGD

ICH_POWGD

21

+VCC_CORE
CPU

TOPSTAR TECHNOLOGY
Page Name
Size
A3

Project Name

PowerOnSequence & Reset Map

Rev
C

N02

of
Date:
Thursday, April 29, 2010
Sheet
37
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

Power On Sequence(Adapter mode)

Power On Sequence(Battery mode)

G3

G3

With Main Battery

Without AC adapter

S3/S4/S5

S5

S0

T04

G3

S0

G3

With AC adapter

S3/S4/S5

S5

S0

T04

T16

T24

T15

T15
PCIRST#
PLTRST#

PCIRST#
T14

T14

SUS_STAT#

SUS_STAT#

T17

T23
(CPU PWRGD)
H_PWRGD

S0
T16

T24

CPURST#

CPURST#

T17

T23

(CPU PWRGD)
H_PWRGD

T10

T10

PM_ICH_PWROK (Input to ICH)

PM_ICH_PWROK (Input to ICH)

Clock Gen Output

Clock Gen Output

IMVP_PWRGD

IMVP_PWRGD

CK410_CLK_EN#

CK505_CLK_EN#

+VCC_CORE

+VCC_CORE

IMVP_ON(EC Output)

IMVP_ON(EC Output)

T08

T08
130ms

130ms
MAIN_PWROK(Input to EC)
+V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8,
+V1.8S,+V0.9S,+V0.89S

MAIN_PWROK(Input to EC)
+V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8,
+V1.8S,+V0.9S,+V0.89S
V0_9S_ON,V1_8S_ON V1_05S_ON,V0_89S_ON(EC Output)

T04

V0_9S_ON,V1_8S_ON V1_05S_ON,V0_89S_ON(EC Output)

V1_8_ON(EC Output)

T49

V1_8_ON(EC Output)

T04

T49

MAIN_ON(EC Output)

MAIN_ON(EC Output)

ALWAYS_ON(EC Output)

SLP_S3#(Input to EC)

SLP_S3#(Input to EC)

SLP_S4#(Input to EC)

SLP_S4#(Input to EC)

PWRBTN#(EC Output)

PWRBTN#(EC Output)

ALWAYS_ON(EC Output)
T03

PWRSW#(Input to EC)

T06

Press Power Button

(PRESS POWER
BUTTON) PWRSWVCC2

Keep up
+V3.3AL

RSMRST#(Input to EC)

T03

T06

+V3.3AL,+V5AL
RSMRST#(Input to ICH&EC)

PWRSW#(Input to EC)

+V3.3AL,+V5AL,
+V5_STBY,EC_RTC

Press Power Button

(PRESS POWER BUTTON)

AC_IN

EC_RTC

+VDC
+VDC
T01

RTCRST#

RTCRST#

T01

T02

VCCRTC

VCCRTC

T02

PLUG
Adapter

PLUG
Main
Battery

Power Off Sequence(Adapter Mode)

Power Off Sequence(Battery Mode)

S0
B

SUS_STAT#

S0

S5

S5

G3

S0

T18
SUS_STAT#

STP_PCI#
PCIRST#
PLTRST#
SLP_S3#(Input to EC)
SLP_S4#(Input to EC)

PCIRST#
PLTRST#
SLP_S3#(Input to EC)

T19

SLP_S4#(Input to EC)

G3

S5

T21
T19

IMVP_ON(EC Output)

IMVP_PWROK(ISL6545 Output)

IMVP_PWROK(ISL6545 Output)

T22

T22
MAIN_PWROK

MAIN_ON(EC Output)
V0_9S_ON,V1_8S_ON V1_05S_ON,V0_89S_ON(EC Output)

S5

STP_PCI#
T21

IMVP_ON(EC Output)

MAIN_PWROK

S0
T18

T22a

MAIN_ON(EC Output)

V1_8_ON(EC Output)
V0_9S_ON(EC Output)

+V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8,
+V1.8S,+V0.9S,+V0.89S

V1_8_ON(EC Output)
+V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8,
+V0.9S
T22a

ALWAYS_ON(EC Output)
ALWAYS_ON(EC Output)

T22c

+V3.3AL,+V5AL
IacN

RSMRST#(Input to EC)
A

IacN

ACIN
Pull out
Main
Battery

TOPSTAR TECHNOLOGY

+V3.3AL
+V5AL

Pull out
AC_ADPTER

Page Name
Size Project Name
Custom

Power ON/OFF Timing

Rev
B

N02

Date:
Sheet
of
Thursday, April 29, 2010
38
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

Touchpad
TR1
1K
R0402

TR2
1K
R0402
LEFT

RIGHT

TP

TP

TFD2

TFD1

4
4

TC2
100pF/50V,NPO
TP
1

FMARKS
ns

TESD2
EGA1-0603-V05
ESDPAD_R0603
ns

R_SW
TD-13XA
BUTTON4_S

TP
TP_+V5S

1
1

TC1
TESD1
100pF/50V,NPO
ESDPAD_R0603
TP
EGA1-0603-V05
ns
1
2
L_SW
TD-13XA
BUTTON4_S

TH2

FMARKS
ns

TH1

TH3

TP

TC4
0.1UF/10V,X5R
C0402
TP

HOLE
TH_R217X268_100
ns

HOLE
TH_R217X268_100
ns

HOLE
TH_315_410_230
ns

TC3
0.1UF/10V,X5R
C0402
TP

TP_CAP1
TP1
INT_spkR 6Pin
CNS6_0D5_RA1

6
5
4
3
2
1

6
5
4
3
2
1

14

TP_+V5S
TP_TPCLK
TP_TPDAT
13

TP

12
11
1410
9
8
7
6
5
4
13 3
2
1

12
11
10
9
8
7
6
5
4
3
2
1

RIGHT
LEFT

TP_TPCLK
TP_TPDAT
TP_+V5S

ns
EMIPOINT

TE3
EMI

TE2
EMI

TE1
EMI

TPCON_USB
CNS12_0D5_RA1
TP

ns
ns
EMIPOINT EMIPOINT
TOPSTAR TECHNOLOGY
Page Name

Size
A4

Project Name

Swain Xu()
Touchpad Board
A

Rev
A

P01

39
39
of
Date: Friday, April 30, 2010
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5