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NNCE
ECE / IV SEM
EC II & S LAB - LM
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
UNIVERSITY EXAMINATION
The exam will be conducted for 100 marks. Then the marks will be calculated to 80
marks
Split up of practical examination marks
Aim and Procedure
Program
Execution
Result
Viva voce
Total
=
25 marks
=
30 marks
=
30 marks
=
05 marks
=
10 marks
---------------------=
100 marks
---------------------
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
LIST OF EXPERIMENTS
Differential amplifier
Active filters : Butterworth 2 nd order LPF, HPF (Magnitude and Phase response)
Astable, Monostable and Bistable multivibrator - Transistor bias
D/A and A/D converters (Successive approximation)
Analog multiplier
CMOS inverter, NAND and NOR
Total: 45
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
01
02
03
COLPITTS OSCILLATOR
12
04
HARTLEY OSCILLATOR
15
05
ASTABLE MULTIVIBRATOR
18
06
MONOSTABLE MULTIVIBRATOR
21
07
BISTABLEMULTIVIBRATOR
24
08
27
09
30
10
33
11
36
12
39
13
42
14
ASTABLE MULTIVIBRATOR
SYMMETRICAL
ASTABLE MULTIVIBRATOR
ASYMMETRICAL
45
16
MONOSTABLE MULTIVIBRATOR
51
17
BISTABLE MULTIVIBRATOR
54
18
CMOS INVERTER
57
19
CMOS NOR
60
20
CMOS NAND
63
21
66
15
48
23
24
25
67
No
LIST OF EXPERIMENTS
ge
S.NO
Pa
CONTENTS
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 1
Title of the Exercise :
Date of the Exercise :
S.NO APPARATUS
1.
OPAMP
2.
Resistors
3.
4.
5
6.
b)
Capacitors
RPS
CRO
Connecting wires
SPECIFICATION
IC74
1.2K,
13K,377,12.5K
0.1F
12V
1MHz
-
QUANTITY
1
3,Each1
3
1
1
Req.
DESIGN PROCEDURE:
Frequency of oscillator F=1//2RC.
Assume C and find R to prevent loading of the amplifier by RC networkR110R.
c)
THEORY:
The amplifier stage is self biased with a capacitor by passed source resistor (Rs) and
drain bias resistor (Rd). the expression for voltage gain of the amplifier is given by A v =gm. rl.
The feedback network consists of three identical RC sections. Each section produces a phase
shift of 60. Therefore the net phase shift of the feedback network is 180 degree. Since the
amplifier stage also introduces a phase shift of 180, therefore total phase shift is 360 or 0.
For the variable frequency oscillators, the three capacitors are ganged and varied
simultaneously. When the circuit is energized by switching on the supply, the circuit starts
oscillating. The oscillations may start due to the minor variation in dc supply or inherent
noise.
d)
PROCEDURE:
Hook up the circuit as shown in the circuit diagram.
Switch on the power supply.
Observe the output waveform in CRO.
Dr.NNCE
e)
CIRCUIT DIAGRAM:
f)
MODEL GRAPH:
ECE / IV SEM
EC II & S LAB - LM
Dr.NNCE
g)
ECE / IV SEM
EC II & S LAB - LM
Time(ms)
Frequency (KHz)
TABULATION:
Amplitude(Volts)
RESULT:
Thus the RC phase shift oscillator was designed and its output waveform was verified.
VIVA QUESTIONS:
1.
What is amplifier?
Amplifier is a device which is used to amplification purpose.
2.
What is amplification?
A low strength signal is converted into strengthen signal ie) boost up process
3.
List the disadvantages of Rc phase shift Oscillator. (or)
What are the merits of Rc phase shift Oscillator.
i. It is ideal for frequency adjustment over a wide range.
ii. It requires a high transistor to overcome losses in the network.
4.
What is the difference between amplifier and oscillator/
Amplifier is working in the negative feedback while oscillator working in the positive
feedback.
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 2
Title of the Exercise :
Date of the Exercise :
S.NO APPARATUS
1.
OPAMP
2.
Resistors
3.
4.
5
6.
b)
Capacitors
RPS
CRO
Connecting wires
SPECIFICATION
IC741
1.5K,
1K,500,1.5K
0.1F
12V
1MHz
-
QUANTITY
1
Each1
1
1
1
Req.
THEORY:
Wein Bridge Oscillator uses a non inverting amplifier and hence does not produce any phase
shift during amplifier stage as total phase shift req. is 0. In wein bridge oscillator type no
phase shift is necessary through Feedback. Thus the total phase shift around a loop is 0.
c)
DESIGN PROCEDURE:
PROCEDURE:
Hook up the circuit as shown in the circuit diagram.
Switch on the power supply.
Observe the output waveform in CRO.
9
Dr.NNCE
e)
CIRCUIT DIAGRAM:
f)
MODEL GRAPH:
ECE / IV SEM
10
EC II & S LAB - LM
Dr.NNCE
g)
EC II & S LAB - LM
TABULATION:
Amplitude(Volts)
h)
ECE / IV SEM
Time(ms)
Frequency (KHz)
RESULT:
Thus the Wein bridge oscillator was designed and its output waveform was verified.
VIVA QUESTIONS:
1.
What is an Oscillator?
An Oscillator is a Circuit, which generates an alternating voltage of any desired
frequency. It can generate an a.c output signal without requiring any externally applied input
signal.
2.
What is a beat frequency oscillator?
Beat frequency Oscillator (BFO) is an Oscillator in which a deserved signal frequency
such as the beat frequency produced by combining the different signal frequencies such as on
different radio frequencies.
3.
What is sustained Oscillation?
The electrical oscillations in which amplitude does not change with time are called as
sustained oscillations. It is also called as Undamped Oscillation.
4.
What is meant by resonant Circuit Oscillators?
LC Oscillators are known as resonant circuit oscillator because the frequency
of operation of LC Oscillator is nothing but a resonant frequency of tank circuit or LC tank
circuit produces sustained Oscillation at the resonant circuit oscillator.
11
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 3
Title of the Exercise :
Date of the Exercise :
COLPITTS OSCILLATOR
S.NO APPARATUS
1.
Transistor
2.
Resistors
3.
4.
5.
6.
7.
b)
Capacitors
Inductor
RPS
CRO
Connecting wires
SPECIFICATION
BC 107
11.64 K,
552.2,10.02K1.67k
53.5nF,80F, 100mF
0.78mH
12V
1MHz
-
QUANTITY
1
Each 1
2,1,1
1
1
1
Req.
DESIGN PROCEDURE:
Select a appropriate transistor and note down its specification such as VCE,IC(MAX), hfe(min) and
Vbe(sat).
VCC= VCEQ
R2=S* RE
VR1+VR2=VCC
XCE RE/10
PROCEDURE:
12
Dr.NNCE
ECE / IV SEM
c)
d)
MODEL GRAPH:
13
EC II & S LAB - LM
Dr.NNCE
e)
EC II & S LAB - LM
TABULATION:
Amplitude(Volts)
f)
ECE / IV SEM
Time(ms)
Frequency (KHz)
RESULT:
Thus the Colpitts oscillator was designed and its output waveform was verified.
VIVA QUESTIONS:
1.
14
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 4
Title of the Exercise :
Date of the Exercise :
HARTLEY OSCILLATOR
S.NO APPARATUS
1.
Transistor
2.
Resistors
3.
4.
5.
6.
7.
b)
Capacitors
Inductor
RPS
CRO
Connecting wires
SPECIFICATION
BC 107
2.74 K,
1.76K,10.58K
0.1F, 0.1F
0.1mH,0.33mH
12V
1MHz
-
QUANTITY
1
1,2,1
Each 2
Each 1
1
1
Req.
DESIGN PROCEDURE:
Select a appropriate transistor and note down its specification such as VCE,IC(MAX), hfe(max) and
Vbe(sat).
R2=S* RE
VR1+VR2=VCC
c)
PROCEDURE:
15
Dr.NNCE
ECE / IV SEM
d)
e)
MODEL GRAPH:
16
EC II & S LAB - LM
Dr.NNCE
f)
EC II & S LAB - LM
TABULATION:
Amplitude(Volts)
g)
ECE / IV SEM
Time(ms)
Frequency (KHz)
RESULT:
Thus the Hartley oscillator was designed and its output waveform was verified.
VIVA QUESTIONS:
1.
What are the types of sinusoidal oscillator? Mention the different types of
sinusoidal oscillator?
RC phase shift Oscillator.
Wein bridge Oscillator.
Hartley Oscillator
Colpitts Oscillator
Crystal Oscillator
2.
What is Barkhausan criterion?
The conditions for oscillator to produce oscillation is given by Barkhausan
criterion. They are :
(i). The total phase shift produced by the circuit should be 360o or 0o
(ii).The Magnitude of loop gain must be greater than or equal to 1
i.e. . A 1.
3.
Name two high frequency Oscillators.
i. Hartley Oscillator
ii. Colpitts Oscillator
iii.Crystal Oscillator
4.
What are the essential parts of an Oscillator?
i.
Tank circuit (or) Oscillatory circuit.
ii.
Amplifier (Transistor amplifier)
iii.
Feedback Circuit.
17
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 5
Title of the Exercise :
Date of the Exercise :
ASTABLE MULTIVIBRATOR
S. NO.
1
2
3
4
5
6
COMPONENTS
Breadboard
Resistors
Capacitors
Transistor
CRO
RPS
RANGE
100k, 2k
0.01F
BC107
0-30MHz
0-30V
QUANTITY
1
2each
2
1
1
1
b)
THEORY:
Astable multivibrator consists of two common emitter amplifying stages.When the d.
c. power supply is switched ON (t=0) one of the transistor will start conducting more than the
other due to some imbalance in circuit. Then because of the other due to some positive
feedback, the transistor Q1 will be driven into saturation and Q2 to cut off. Thus at t>0 Q1 is
ON and Q2 is OFF. During t>0, capacitor C1 is charging and VB2 increases. As it increases
above cut-in-voltage, Q2 starts conducting at t>t1. As the transistor Q2 goes into saturation,
VC falls to VCE(sat). Thus at t>t1, Q1 is OFF and Q2 is ON. During t>t1, VB1 rises
exponentially with time constant. At T=t2, VB1 reaches cutin level and a reverse transition
take place. It is used to generate square waveform.
c)
PROCEDURE:
1.
The components are connected as per the circuit diagram.
2.
The DC supply is switched ON.
3.
The output voltage and the time period is measured across transistors T1 and T2 at
both the base and the collector.
4.
The output wave is plotted in the graph.
18
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
d)
e)
MODEL GRAPH:
19
Dr.NNCE
f)
EC II & S LAB - LM
TABULATION:
Amplitude(Volts)
g)
ECE / IV SEM
Time(ms)
Frequency (KHz)
RESULT:
Thus the Astable multivibrator was designed and its output waveform was verified.
VIVA QUESTIONS:
1.
20
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 6
Title of the Exercise :
Date of the Exercise :
MONOSTABLE MULTIVIBRATOR
S. NO.
1
2
COMPONENTS
Breadboard
Resistors
3
4
5
6
7
Capacitors
Transistor
Diode
CRO
RPS
RANGE
QUANTITY
1
3k, 1k, 280k, 22k, 1 each
1.75k
1nF
2
BC107
1
1N4007
1
0-30MHz
1
0-30V
1
b)
THEORY:
Monostble multivibrator is also called as one shot or univibrator and can be used to
generate a gating pulse, whose width can be controlled. The monostable multivibrator
provides a single pulse of desired duration in response to an external trigger. The external
trigger causes the circuit to go to the quasi stable state. After a certain interval of time, the
circuit returns to its original state. It consists of two NPN transistors. In this case, when a
pulse is applied to the input circuit, the circuit state is changed abruptly to unstable state for a
determined time after which the circuit returned to its original state automatically. The two
outputs are the complement of each other i.e when one of the output is at VCC level, the
other is at VCE(sat) level. The monostable multivibrators are used for the generation of well
defined pulses, the logic design of pulse delay, variable pulse width, etc. The width or
duration of the pulse obtained at the collector or output of either transistor of the monostable
multivibrator is given by the expression t=0.69 RC.
c)
PROCEDURE:
1.
2.
3.
4.
21
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
d)
e)
TRIGGER GENERATION:
22
Dr.NNCE
f)
EC II & S LAB - LM
TABULATION:
Amplitude(Volts)
g)
ECE / IV SEM
Time(ms)
Frequency (KHz)
RESULT:
Thus the Monostable multivibrator was designed and its output waveform was
verified.
VIVA QUESTIONS:
1.
Define integrator.
Integrator is a circuit that passes low frequencies of the input and attenuates high
frequencies. Integrator implies that the output voltage is an integral of the input voltage.
3.
23
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 7
Title of the Exercise :
Date of the Exercise :
BISTABLE MULTIVIBRATOR
S. NO.
COMPONENTS
1
2
Breadboard
Resistors
3
4
5
6
7
Capacitors
Transistor
Diode
CRO
RPS
RANGE
QUANTITY
1
3k, 1k, 280k, 22k, 1 each
1.75k
1nF
2
BC107
1
1N4007
1
0-30MHz
1
0-30V
1
b)
THEORY:
Bistble multivibrator is also called as one shot or univibrator and can be used to
generate a gating pulse, whose width can be controlled. The bistable multivibrator provides a
single pulse of desired duration in response to an external trigger. The external trigger causes
the circuit to go to the quasi stable state. After a certain interval of time, the circuit returns to
its original state. It consists of two NPN transistors. In this case, when a pulse is applied to
the input circuit, the circuit state is changed abruptly to unstable state for a determined time
after which the circuit returned to its original state automatically. The two outputs are the
complement of each other i.e when one of the output is at VCC level, the other is at VCE(sat)
level. The bistable multivibrators are used for the generation of well defined pulses, the logic
design of pulse delay, variable pulse width, etc. The width or duration of the pulse obtained at
the collector or output of either transistor of the bistable multivibrator is given by the
expression t=0.69 RC.
c)
1.
2.
3.
4.
PROCEDURE:
The components are connected as per the circuit diagram.
The output is measured at the collector terminals of the two transistors.
The required output voltages and the total time period is noted.
The output wave is plotted in the graph.
24
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
d)
e)
MODEL GRAPH:
V
Vce(sat)
Output Vc2
Vce(sat)
Output Vc1
Vbe(sat)
Output Vb2
Vbe(sat)
Output Vb1
Time (s)
25
Dr.NNCE
f)
ECE / IV SEM
EC II & S LAB - LM
RESULT:
Thus the Bistable multivibrator was designed and its output waveform was verified.
VIVA QUESTIONS:
1.
26
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 8
Title of the Exercise :
Date of the Exercise :
S. NO.
1
2
3
4
5
6
COMPONENTS
Breadboard
Resistors
Capacitors
Transistor
CRO
RPS
RANGE
1k,4.7k,10k
1nF,0.01mF,0.1 mF
BC107
0-30MHz
0-30V
QUANTITY
1
1 each
2
1
1
1
b)
THEORY:
In class C amplifier, the output current flows only for one half of the cycle of the
input signal. The transistor dissipates no power with zero input signal. The average current
drawn by the circuit in class C is smaller than that in class A. Complementary symmetry
amplifier requireds neither an input nor an output transformer. This arrangement uses
transistors having complementary symmetry in the emitter follower configuration. The term
complementary means that it uses two identical transistors one NPN and the other PNP. The
term symmetry means that biasing resistors are equal. This amplifier circuit has a unity gain
because of the emitter follower configuration. Moreover there is no phase inversion of the
output signal. The split supply used in the circuit gives us an advantage that the dc
component of the output voltage can be made zero. Thus the only ac component of the power
is available across the load resistor.
c)
PROCEDURE:
1.
2.
3.
The load resistance is varied using the decade resistance box and output voltage is
measured and readings are tabulated
27
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
d)
e)
MODEL GRAPH:
28
Dr.NNCE
f)
EC II & S LAB - LM
TABULATION:
Sl.
No.
g)
ECE / IV SEM
Input
frequency
(Hz)
Input
Voltage
(mV)
Output
Voltage
(V)
Voltage gain
V
Vgain 20log o db
Vi
RESULT:
Thus the Class C single tuned amplifier was designed and its frequency response was
observed
VIVA QUESTIONS:
1.
3.
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 9
Title of the Exercise :
Date of the Exercise :
S. NO.
1
2
COMPONENTS
Breadboard
Resistors
Capacitors
4
5
6
7
Transistor
CRO
RPS
Digital multimeter
RANGE
QUANTITY
1
10k, 11k, 200, 1each
283
1F
2
10F
1
BC107
0-30MHz
1
0-10V
1
1
b)
THEORY:
In the current series amplifier, the output current flows only for one half of the cycle
of the input signal. The transistor dissipates no power with zero input signal.. Complementary
symmetry amplifier requires neither an input nor an output transformer. This arrangement
uses transistors having complementary symmetry in the emitter follower configuration. This
amplifier circuit has a unity gain because of the emitter follower configuration. Moreover
there is no phase inversion of the output signal. The split supply used in the circuit gives us
an advantage that the dc component of the output voltage can be made zero. Thus the only ac
component of the power is available across the load resistor.
c)
PROCEDURE:
1.
2.
3.
The load resistance is varied using the decade resistance box and output voltage is
measured and readings are tabulated.
30
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
d)
e)
MODEL GRAPH:
31
Dr.NNCE
f)
ECE / IV SEM
EC II & S LAB - LM
TABULATION:
Sl. No.
Input
frequency
(Hz)
Input
Voltage (mV)
Output
Voltage (V)
Voltage gain
V
Vgain 20log o db
Vi
g)
RESULT:
Thus the Current series feedback amplifier was designed and its frequency response was
observed.
VIVA QUESTIONS:
1.
What is feedback amplifier?
The part of the output is given to the input of the circuit called as feedback amplifier.
2.
Classify the feedback amplifiers.
1) Voltage series feedback amplifier
2) Current series feedback amplifier
3) Voltage shunt feedback amplifier
4) Current shunt feedback amplifier
3.
32
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 10
Title of the Exercise :
Date of the Exercise :
b)
S. NO.
1
2
COMPONENTS
Breadboard
Resistors
Capacitors
4
5
6
7
Transistor
CRO
RPS
Digital multimeter
RANGE
QUANTITY
1
10k, 11k, 200, 1each
283
1F
2
10F
1
BC107
0-30MHz
1
0-10V
1
1
THEORY:
The feedback voltage is connected in series with the input circuit means called as
voltage series amplifier. If the feedback voltage is equal to the output voltage then it is called
as voltage series feedback amplifier.
c)
PROCEDURE:
1.
2.
3.
The load resistance is varied using the decade resistance box and output voltage is
measured and readings are tabulated.
33
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
d)
e)
MODEL GRAPH:
34
Dr.NNCE
f)
ECE / IV SEM
EC II & S LAB - LM
TABULATION:
Sl. No.
Input
frequency
(Hz)
Input
Voltage
(mV)
Output
Voltage (V)
g)
Voltage gain
V
Vgain 20log o db
Vi
RESULT:
Thus the Current series feedback amplifier was designed and its frequency response was
observed.
VIVA QUESTIONS:
1.List out the types of feedback circuits.
Positive feedback
Negative feedback
2.Write the advantages of negative feedback.
Higher input and lower output impedance.
Improved higher sensitivity
Reduced noise
Increased bandwidth
Reduced distortion
3.Write the disadvantages of negative feedback
reduced overall circuit gain
reduced distortion
35
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 11
Title of the Exercise :
ORCAD capture
b)
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
36
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
c)
CIRCUIT DIAGRAM: SECOND ORDER LOW PASS BUTTERWORTH
FILTER
d)
MODEL GRAPH:
37
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
e)
RESULT:
Thus the second order low pass filter circuit was simulated using ORCAD capture and
its frequency response was obtained.
VIVA QUESTIONS:
1.
Write the equation for finding the bandwidth.
Bandwidth= f2-f1
Where f1= lower cut off frequency and f2= higher cut off frequency
2.
4.
38
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 12
Title of the Exercise :
Date of the Exercise :
ORCAD capture
b)
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
39
Dr.NNCE
c)
ECE / IV SEM
EC II & S LAB - LM
C2
0.01u
R2
15.9k
0
R1
C1
12v
4
2
V-
OS1
OUT
V+
OS2
1
6
OUTPUT
Frequency=100
7
12v
AC=1
INPUT
DC=0
1.44k R3
0
Voff=0
Analysis Type : Time Domain ( Transient)
Vamp=1V
Run to Time =40ms
0
Maximum Step Size= 0.2us
0
d)
MODEL GRAPH:
:
Amplitude
in volts
0
Time in ms
0
Time in ms
40
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
e)
RESULT:
Thus the Differentiated Sine wave input circuit was simulated using ORCAD capture
and its frequency response was obtained.
VIVA QUESTIONS:
1.
Define differentiator.
Differentiator is a circuit that passes high frequencies of the input and attenuates low
frequencies. It implies that the output voltage is the differential of the input.
2.
41
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 13
Title of the Exercise :
Date of the Exercise :
ORCAD capture
b)
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
42
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
C2
0.01u
R2
15.9k
0
12v
R1
C1
V-
V1= -1V
V2= 1V
AC=10
DC=0
TR=0ms
TF=0ms
TD=0ms
PW=5ms
1.44k R3
PER=0.01s INPUT
OS1
OUT
V+
OS2
1
6
OUTPUT
12v
0
MODEL GRAPH:
43
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
d)
RESULT:
Thus the Differentiated Square wave input circuit was simulated using ORCAD
capture and its frequency response was obtained.
VIVA QUESTIONS:
1.
44
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 14
Title of the Exercise :
Date of the Exercise :
ORCAD capture
b)
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
45
Dr.NNCE
c)
ECE / IV SEM
EC II & S LAB - LM
V1
8V
Rc1
1k
R2
R1
36K
36K
Rc2
C1
Vc1
1k
C2
0.01U
Vc2
0.01U
Q23
Q22
Vb1
Vb2
SMBT2222A/SIE
SMBT2222A/SIE
d)
MODEL GRAPH:
V
Vce(sat)
Output Vc2
Vce(sat)
Output Vc1
Vbe(sat)
Output Vb2
Vbe(sat)
Output Vb1
Time(s)
46
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
e)
RESULT:
Thus the astable multivibrator(symmetrical) circuit was simulated using ORCAD
capture and its output waveform was obtained.
VIVA QUESTIONS:
1.
47
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 15
Title of the Exercise :
Date of the Exercise :
ORCAD capture
b)
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
48
Dr.NNCE
c)
ECE / IV SEM
EC II & S LAB - LM
8V
Rc1
1k
Vc1
R2
R1
Rc2
43K
28K
1k
C1
C2
0.01U
0.01U
Vc2
Q23
Q22
Vb1
Vb2
SMBT2222A/SIE
SMBT2222A/SIE
d)
MODEL GRAPH:
V
Vce(sat)
Output Vc2
Vce(sat)
Output Vc1
Vbe(sat)
Output Vb2
Output Vb1
Vbe(sat)
Time(s)
49
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
e)
RESULT:
Thus the astable multivibrator(asymmetrical) circuit was simulated using ORCAD
capture and its output waveform was obtained.
VIVA QUESTIONS:
1.
4.
50
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 16
Title of the Exercise :
Date of the Exercise :
MONOSTABLE MULTIVIBRATOR
ORCAD capture
b)
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
51
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
c)
d)
MODEL GRAPH:
Vce(sat)
Output Vc2
Vce(sat)
Output Vc1
Vbe(sat)
Output Vb1
Vbe(sat)
Output Vb2
Time (s)
52
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
e)
RESULT:
Thus the monostable multivibrator circuit was simulated using ORCAD capture and
its output waveform was obtained.
VIVA QUESTIONS:
1.
2.
Define resonance.
The reactance of the capacitor equals that of the inductor reactance.
i.e C. = 1 / L.
What is Quality factor?
The ratio of inductive reactance of the coil at resonance to its resistance is known
as quality factor.
Q = XL / R
3.
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 17
Title of the Exercise :
Date of the Exercise :
BISTABLE MULTIVIBRATOR
ORCAD capture
b)
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
54
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
c)
d)
MODEL GRAPH:
Vce(sat)
Output Vc2
Vce(sat)
Output Vc1
Vbe(sat)
Output Vb2
Vbe(sat)
Output Vb1
Time (s)
55
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
e)
RESULT:
Thus the Bistable multivibrator circuit was simulated using ORCAD capture and its
output waveform was obtained.
VIVA QUESTIONS:
1.
What is unilateralisation?
It is the phenomenon by which a signal can be transmitted from the input to the output
alone and not viceversa. In an unilateralised amplifier both resistive and reactive effects are
cancelled.
2.
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 18
Title of the Exercise :
Date of the Exercise :
CMOS INVERTER
ORCAD capture
b)
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
57
Dr.NNCE
c)
ECE / IV SEM
EC II & S LAB - LM
5v
V1
M1
MbreakP
DSTM1
Off time=0.5us
On time=0.5us
OUTPUT
CLK
INPUT
M2
MbreakN
Run to time=0.01ms
0
d) MODEL
GRAPH
V
Input
Output
Time(s)
e) RESULT:
Thus the CMOS Inverter circuit was simulated using ORCAD capture and its output
waveform was obtained.
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
VIVA QUESTIONS:
Mention the applications of class c tuned amplifier.
One of the most common applications for mixer is in radio receivers. The mixer is
used to convert incoming signal to a lower frequency where it is easier to obtain the high gain
and selectivity required.
Mixer circuits are used to translate signal frequency to some lower frequency or to
some higher frequency. When it is used to translate signal to lower frequency it is called
down converter. When it is used to translate signal to higher frequency, it is called up
converter.
1.
2.
59
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 19
Title of the Exercise :
Date of the Exercise :
CMOS NOR
ORCAD capture
b)
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
60
Dr.NNCE
c)
ECE / IV SEM
EC II & S LAB - LM
V1
M1
5V
MbreakP
Off time=1us
On time=1us
DSTM1
CLK
Input A
M2
MbreakP
Off time=0.5us
On time=0.5us
DSTM2
CLK
Input B
M4
M3
Output
MbreakN
MbreakN
0
Analysis type:Time domain (transient)
Run to time=0.01ms
d)
MODEL GRAPH:
V
Input A
Input B
Output
Time(s)
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
e)
RESULT:
Thus the CMOS NOR circuit was simulated using ORCAD capture and its output
waveform was obtained.
VIVA QUESTIONS:
1.
62
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 20
Title of the Exercise :
Date of the Exercise :
CMOS NAND
ORCAD capture
b)
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
63
Dr.NNCE
c)
ECE / IV SEM
EC II & S LAB - LM
M4
V2
M5
5V
Off time=1us
On time=1us
MbreakP
DSTM3
MbreakP
CLK
Input A
Output
M6
MbreakN
M7
MbreakN
0
Analysis type:Time domain (transient)
Run to time=0.01ms
Maximum step size=0.2us
d)
MODEL GRAPH:
V
Input A
Input B
Output
Time(s)
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
e)
RESULT:
Thus the CMOS NAND circuit was simulated using ORCAD capture and its output
waveform was obtained.
VIVA QUESTIONS:
1.
3.
Define CMRR.
Common Mode Rejection Ratio(CMRR) is the ability of the differential amplifiers to
reject the common mode signals. It is defined as the ratio of difference mode gain Ad to
common mode gain Ac.
4.
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise Number : 21
Title of the Exercise :
Date of the Exercise :
ORCAD capture
b)
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
66
Dr.NNCE
ECE / IV SEM
c)
CIRCUIT DIAGRAM:
d)
MODEL GRAPH:
EC II & S LAB - LM
V
Input
B0
0 0 0 0 0 0 0 0
Input
B1
0 0 0 0
Input
B2
0 0
Input
B3
1 1
1 1 1 1
0 0
1 1
1 1 1 1 1 1 1 1
0 0 0 0
0 0
1 1
1 1 1 1
0 0
1 1
Output
Time(s)
67
0 0
0 0
0 0
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
RESULT:
Thus the digital to analog converter circuit was simulated using ORCAD capture and
its output waveform was obtained.
VIVA QUESTIONS:
1.
What are the basic elements of power supply ?
(i) Transformer
(ii) Rectifier.
(iii) Filter.
2.
What is ripple factor()?
Ripple factor () may be defined as the ratio of the root mean square (rms) value of the ripple
voltage to the absolute value of the dc component of the output voltage, usually expressed as
a percentage. However, ripple voltage is also commonly expressed as the peak-to-peak value.
This is largely because peak-to-peak is both easier to measure on an oscilloscope and is
simpler to calculate theoretically. Filter circuits intended for the reduction of ripple are
usually called smoothing circuits.
3.
What is a rectifier?
A rectifier is an electrical device that converts alternating current (AC), which periodically
reverses direction, to direct current (DC), which flows in only one direction. The process is
known as rectification.
4.
Define SMPS .
A switched-mode power supply (switching-mode power supply, SMPS, or simply switcher)
is an electronic power supply that incorporates a switching regulator in order to be highly
efficient in the conversion of electrical power.
An SMPS is usually employed to efficiently provide a regulated output voltage, typically at a
level different from the input voltage.
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise/Experiment Number: 22
Title of the exercise/experiment : Inverting, Non-inverting and Differential amplifiers
Date of the experiment
:
AIM:
To construct and test the performance of an Inverting, Non-inverting amplifier
and Differential amplifier using IC A 741
APPARATUS REQUIRED:
S. No. Name
Range
Quantity
1
Dual Power Supply
(0-30)V
1
2
Resistors
1K;5 K;100 K
Each 2
3
Regulated Power Supply
(0-30)V
1
4
IC A 741
1
5
Voltmeter
(0-50)V
1
DESIGN
6
Connecting Wires
:
INVERTING AMPLIFIER:
Let A = -5; R1 = 1K
A = Rf / R1
Rf = 5 K
Rcomp = R1 Rf / R1 + Rf
= 833
NON-INVERTING AMPLIFIER:
Let A = 6; R1 = 1K
A = 1 + (Rf / R1)
Rf = 5 K
Rcomp = R1 Rf / R1 + Rf
= 833
NON-INVERTING AMPLIFIER:
Let A = 100; R1 = 1K
A = R2 / R1
R2 = 100 K
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Dr.NNCE
ECE / IV SEM
CIRCUIT DIAGRAM:
NON-INVERTING AMPLIFIER:
EC II & S LAB - LM
MODEL GRAPH:
DIFFERENTIAL AMPLIFIER:
70
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
THEORY:
INVERTING AMPLIFIER:
The fundamental component of any analog computer is the
operational amplifier or op-amp and the frequency configuration in which it is used as an
inverting amplifier. An input voltage Vin is applied to the input voltage. It receives and
inverts its polarity producing an output voltage. this same output voltage is also applied to a
feedback resistor Rf, which is connected to the amplifier input analog with R1. The amplifier
itself has a very high voltage gain.
If Rf = R1 then Vo=Vi
NON- INVERTING AMPLIFIER:
Although the standard op-amp configuration is as an inverting
amplifier, there are some applications where such inversion is not wanted. However, we
cannot just switch the inverting and non inverting inputs to the amplifier itself. We will still
need negative feedback to control the working gain of the circuit .Therefore, we will need to
leave the resistor structure around the op-amp intact and swap the input and ground
connections to the overall circuit.
VO/VI = (Rf / Ri) +1
From the calculations, we can see that the effective voltage
gain of the non-inverting amplifier is set by the resistance ratio. Thus, if the two resistors are
equal value, then the gain will be 2 rather than 1.
DIFFERENTIAL AMPLIFIER:
A circuit that amplifies the difference between two signals is
called as a differential amplifier. This type of amplifiers is very useful in instrumentation
circuits. From the experimental setup of a differential amplifier, the voltage at the output of
the operational amplifier is zero. The inverting and non-inverting terminals are at the same
potential. Such a circuit is very useful in detecting very small differences in signals. Since the
gain can be chosen to be very large. For example, if R2=100R1, then a small difference V1V2 is amplified 100 times.
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
TABULATION:
INVERTING AMPLIFIER:
S.No
9.93
11.2
DIFFERENTIAL AMPLIFIER:
Input Voltage (in volts)
Output Voltage (in volts)
S.No
V1
V2
9.74
9.80
PROCEDURE:
The V1 and V2 voltages are fixed and measured from the other channel of CRO and
the corresponding output voltages are also noted from the CRO.
The above step is repeated for various values of V1 and V2.V1 and V2 may be AC or
DC voltages from function generator or DC power supply.
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Readings are tabulated and gain was calculated and composed with designed values.
RESULT
Thus the Inverting, Non-inverting and Differential amplifier using op-amp was designed and
tested.
VIVA QUESTIONS:
1. Define an operational amplifier.
An operational amplifier is a direct-coupled, high gain amplifier consisting of one or more
differential amplifier. By properly selecting the external components, it can be used to
perform a variety of mathematical operations.
2. Mention the characteristics of an ideal op-amp.
* Open loop voltage gain is infinity.
*Input impedance is infinity.
*Output
impedance is zero.
*Bandwidth is infinity.
*Zero offset.
3. Define input offset voltage.
A small voltage applied to the input terminals to make the output voltage as zero when the
two input terminals are grounded is called input offset voltage.
4. Define input offset current.
The difference between the bias currents at the input terminals of the op-amp is called as
input offset current.
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise/Experiment Number: 23
Title of the exercise/experiment
Date of the experiment
AIM:
To construct a differential amplifier using BJT and to determine the dc collector current of
individual transistors and also to calculate the CMRR.
APPARATUS REQUIRED:
S.No.
1.
2.
3.
4.
5.
6.
Name
Transistor
Resistor
Regulated power supply
Function Generator
CRO
Bread Board
Range
BC107
4.7k, 10k
(0-30)V
(0-3) MHz
30 MHz
Quantity
2
2,1
1
2
1
1
OBSERVATION
VIN = V1 V2
V0 =
Ad = V0/ VIN
For the differential mode operation the input is taken from two different sources and the
common mode operation the applied signals are taken from the same source
Common Mode Rejection Ratio (CMRR) is an important parameter of the differential
amplifier. CMRR is defined as the ratio of the differential mode gain, Ad to the common
mode gain, Ac.
CMRR = Ad / Ac
In ideal cases, the value of CMRR is very high.
OBSERVATION
VIN =VO =AC = VO / VIN
FORMULA:
Common mode Gain (Ac) = VO / VIN
Differential mode Gain (Ad) = V0 / VIN
Where VIN = V1 V2
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Dr.NNCE
ECE / IV SEM
CIRCUIT DIAGRAM
75
EC II & S LAB - LM
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Viva questions
1.What is an amplifier?
An amplifier is a device which produces a large electrical output of similarcharacteristics to
that of the input parameters.
2.. How are amplifiers classified according to the input?
1. Small signal amplifier 2. Large signal amplifier
3.How are amplifiers classified according to the transistor configuration?
Common emitter amplifier 2. Common base amplifier 3. Common collector
amplifier
4. What is the different analysis available to analyze a transistor?
1. AC analysis 2. DC analysis
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise/Experiment Number: 24
Title of the exercise/experiment
POWER AMPLIFIER
Date of the experiment
:
AIM:
To construct a Class B complementary symmetry power amplifier and observe the
waveforms with and without cross-over distortion and to compute maximum output power
and efficiency.
APPARATUS REQUIRED:
S.No.
1.
2.
3.
4.
5.
6.
7.
8.
Name
Transistor
Resistor
Capacitor
Diode
Signal Generator
CRO
Regulated power supply
Bread Board
Range
CL100, BC558
4.7k,15k
100F
IN4007
(0-3)MHz
30MHz
(0-30)V
Quantity
1,1
2,1
2
2
1
1
1
1
FORMULA:
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
into conduction. However there is a period between the crossing of the half cycles of the
input signals, for which none of the transistor is active and output, is zero.
MODEL GRAPH
f1
f2
78
f (Hz)
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
TABULATION:
FREQUENCY RESPONSE OF CASCODE AMPLIFIER
Keep the input voltage constant (Vin) =
Frequency (in Hz)
Output Voltage (in volts)
Gain = 20 log (Vo / Vin) (in dB)
RESULT:
Thus, the Class B amplifier was constructed and the gain was determined.
VIVA QUESTION:
1. What is feed back?
It is the process of injecting some energy from the output and then returns it back
tothe input.
2. What is the disadvantage of negative feed back?
Reduces amplifier gain.
3. Define sensitivity.
It is the ratio of percentage change in voltage gain with feedback to the percentage
change in voltage gain without feed back.
4. Define Desensitivity.
It is the ratio of percentage change in voltage gain without feedback to thepercentage
change in voltage
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
Exercise/Experiment Number: 25
Title of the exercise/experiment
Date of the experiment
AIM:
:CASCADE AMPLIFIER
:
S.No.
Name
1.
Transistor
2.
Resistor
3.
4.
5.
6.
7.
Range
BC107
22k,6 k,700 ,470
16 k,6.2 k,3.3 k
1.1 k
(0-30)V
(0-3)MHz
30 MHz
0.01F
Quantity
2
1,1,1,1,
1,1,1,
1
1
1
1
1
3
THEORY:
A cascode amplifier consists of a common emitter amplifier stage in series with a common
base amplifier stage. It it one approach to solve the low impedance problem of a common
base circuit. Transistor Q1 and its associated components operate as a common emitter
amplifier, while the circuit of Q2 functions as a common base output stage. The cascade
amplifier gives the high input impedance of a common emitter amplifier, as well as the good
voltage gain and frequency performance of a common base circuit.
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. The waveforms at the input and output are observed for cascade operations varying
input frequency.
3. The biasing resistances needed to locate the Q-point are determined.
80
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
4. Set the input voltage as 1V and by varying the frequency, note the output voltage.
5. Calculate gain=20 log (Vo / Vin.)
6. A graph is plotted between frequency and gain.
CIRCUIT DIAGRAM:
81
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
TABULATION:
Keep the input voltage constant, Vin =
Frequency (in Hz)
RESULT:
Thus, the Cascade amplifier was constructed and the gain was determined.
VIVA QUESTIONS:
1.What is biasing?
To use the transistor in any application it is necessary to provide sufficient voltage
and current to operate the transistor. This is called biasing.
2. What is the necessary of the coupling capacitor?
It is used to block the c signal to the transistor amplifier. It allows a c &blocks the d c.
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Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
2.
3.
4.
Dr.NNCE
ECE / IV SEM
EC II & S LAB - LM
84
85