Beruflich Dokumente
Kultur Dokumente
VLSI Designs
Testing VLSI
Circuits
Prepared by
Dr. Lim Soo King
02 Dec 2010.
Exercises........................................................................................................158
Bibliography .................................................................................................160
-i-
- ii -
Chapter 12
Testing of VLSI Circuits
_____________________________________________
12.0 Introduction
In Chapter, student will learn the basic concepts of testing, design constraints,
identifying failure in CMOS integrated circuits, designing the test program, and
test hardware, which consists of mainly the load board the interface circuit
board - connecting between the device under test DUT and the test stimulants
from the automatic test equipment ATE. Student will learn how to test the logic
circuit including learning the modern test technique, which is the design-fortestability DFT aimed to identify the failure site and reduce the number of
tedious and complex test vectors with the ease of controllability and
observability. Lastly, the student learns how to perform failure analysis of the
failed integrated circuit, which can be caused by processes that it has gone
through, to identify the root cause of the failure so that correction action can be
implemented to prevent re-occurrence of the failure and of course improve
profitability.
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Figure 12.2: The refilled deep trench isolation between p-well and n-well isolations used to
reduce the occurrence of latch-up
The structure of n-MOS and p-MOS transistor has two parasitic diodes form
between drain/source and the substrate. An either npn or pnp parasitic bipolar
junction transistor formed between drain substrate and source depending on
whether it is an n-MOS or p-MOS transistor. In the case of wrong application of
stimulant to the device such the input voltage is 0.7V (forward voltage of a
diode) greater than the supply voltage VDD. The voltage difference is sufficient
to switch-on the emitter-base junction of the parasitic npn bipolar junction
transistor. The consequence is the SCR effect result a large current flowing from
power supply VDD via a small resistance of collector-emitters of pnpn thyristor
structure. This high current will destroy the surrounding p-MOS and n-MOS
transistors and can melt the bond wire due high current density.
Beside the isolation technique mentioned earlier to prevent the occurrence
of latch-up, other most common technique is to in-activate parasitic bipolar
transistor by setting the emitter-base junction of the transistor in reverse bias
- 123 -
mode. This is done by setting the n-well to power supply VDD voltage and
setting p-well and p-substrate to VSS rail. These techniques cannot totally
eliminate the latch-up problem but it helps reducing its effect. The illustration of
these techniques used in the layout is shown in Fig. 12.3.
Figure 12.3: The illustration of n-well and p-substrate bias to prevent occurrence of latch-up
- 124 -
- 125 -
Figure 12.4: The flowchart of probe test and grading of the die
- 126 -
In the test operation, the process step after assembly, the test strategy follows
the same grading systems as it has been described for die probe test. The
military grade, industrial grade, and commercial grade device are binned
separately by the sorter of automatic test handler ATH. Sorted devices are then
branded with the device part number and special digit to signify grading.
Commercial grade device is normally guaranteed to operate for
temperature range between 00C to 700C. In order to reduce the cost of testing,
the commercial grade device is normally tested with ambient temperature,
which is taken as 250C. Since the 00C and 750C temperature tests are not done.
The test strategy is to test the device with guard banding for 00C and 750C tests.
Commercial product is normally used in the consumer product. The average
selling price ASP of the product is low and there are not in critical operation
such as a car and commercial plane. Therefore, one ambient with proper guard
banding for 00C and 750C tests is sufficient.
Industrial grade device is normally guaranteed to operate for temperature
range between -400C to 850C. This grade of product is used in industrial
application such as the control system of the car fuel injector etc. Therefore, the
test strategy is to test at least two temperatures i.e. ambient and -400C cold
temperature. Depending on the criticality of the industrial operation, the product
may have to be subjected to an accelerated burn-in to wipe out the infant
mortality failure.
Military/space grade device is normally guaranteed to operate for
temperature range between -550C to 1250C. This grade of device is used in
space/military application such as the control system of weaponry system. The
device normally has to undergo four tests i.e. one ambient before burn-in and
three temperature tests after burn-in, which are ambient, +1250C, and -550C
tests.
Figure 12.5: A mixed signal automatic test equipment showing its test head and a mounted
load board
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A probe card is a test fixture. It is used to probe the integrated circuit die. A
mounted prober containing the probe pins arranged in bond pad layout pattern is
used to make contact with the bond pads (bond pad is the input/output, clock
input etc. that are to be connect via bond wire to the external world) of the die
during probe test. The other end of the prober contains a bundle of wire
connecting the prober and the probe card. The wafer is mounted on the x-y table
that its x-y position is controlled by the ATE.
A load board is a test fixture used for packaged device testing. For VLSI
digital testing, a load board may contain simple configuration wiring between
the input/output pins, clock pin, power supply pin etc. with the assigned pin
card of the ATE. For VLSI analogue device testing, a more complicated device
test fixture is required. The bottom end of the load board contains contact pads
when in use they are connected to the assigned pin cards etc of the ATE via
spring loaded pins. The top part contains a socket that can be mounted on the
automatic test hander ATH for automatic feeding testing or temperature testing.
A picture of a load board is shown in Fig. 12.6.
Figure 12.6: A top-view of a load board showing the test socket to be mounted on the ATH
at the center of the board
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Conditions
Characteristics
VO
(V)
Quiescent
Device Current
IDD Max.
0.4
Output Low
(Sink) Current
IOL min.
0.5
1.5
Output High
(Source)
Current
IOH min.
4.6
9.5
13.5
VIN
(V)
0,
5
0,
10
0,
15
0,
20
0,
5
0,
10
0,
15
0,
5
0,
10
0,
15
VDD
(V)
-55
-40
+85
+125
Min
Typ.
Max.
0.25
0.25
7.5
7.5
0.01
0.25
10
0.5
0.5
15
15
0.01
0.50
15
30
30
0.01
20
150
150
0.02
0.64
0.61
0.42
0.36
0.51
10
0.5
0.5
15
15
1.3
2.6
15
30
30
3.4
6.8
Units
mA
-0.64 -0.61
-0.42 -0.36
0.51
10
-1.6
-1.5
-1.1
-0.9
-1.3
-2.6
15
-4.2
-4
-2.8
-2.4
-3.4
-6.8
-1
Characteristics
Propagation Delay
Time TpHL, TpLH
Test Conditions
VDD (V)
5
10
15
Limits
Typ.
125
60
45
Units
Max.
250
150
90
ns
ground rail (VSS) pin (7), input pin (1), (2), (5), (6), (8), (9), (12), and (13), and
output pin (3), (4), (10), and (11).
The test set-ups described here assumed that the dc and ac parametric tests
are done at ambient temperature, which is taken as 250C.
Figure 12.9: Pin configuration of CD4011 Quad 2-input CMOS NAND gate
Figure 12.10: The input diode network of CD4011 NAND gate. The number in parenthesis
is the pin number
The open/short test is consisting of two tests lower diode test and upper diode
test. Set-up shown in Fig. 12.11(a) is testing the functionality of the upper
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diodes and the wire connecting the bond pads and leads of the package by
forcing 1.0mA of current from ATE to the every input pin and then measure the
voltage across the input pin with respect to VDD pin. The value measured should
be the forward voltage of a diode, which has a value >0.7V. The set-up to test
the functionality of lower diodes and the wire connectivity is shown in Fig.
5.11(b). It is done by sinking 1.0mA of current from ATE to the input pin and
measure the voltage between input pin and VSS pin. The measured value should
be the forward voltage of a diode, which should have a value <- 0.7V. Note that
for both tests, the power supply VDD pin (14) and VSS ground rail pin (7), are set
to 0V.
(a)
(b)
Figure 12.11: The set-up for open/short test for input pin 1 of CD4011 quad 2-input NAND
gate
If there is a shorted diode, the measured voltage will be zero in both tests.
Likewise if there is open circuit such as open diode or no connection between
bond pad and lead, the voltage measurement should be the maximum value of
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the voltage range set by the test program, which can be 2.047V for the case of
2.0V range setting. Thus, as a test engineer, you may to set the test limit as <
0.5V and > -0.5V for short circuit and < -1.5V and > 1.5 for open circuit, and
the in between values as good. If there is an open wire connecting VDD or VSS
bond pads and leads, all the tests will show as open failure. If the device fails
any one of the open/short test, the test program will issue command to halt the
test and issue to command to the automatic test handler ATH to yield the device
as reject. If the device passes all open/short test except the for output pins. The
program will execute the command to proceed to next test.
Figure 12.12: The set-up for gross functional test of a NAND gate of CD4011
Before the beginning of the gross functional test, the sequence test vector
patterns and expected output test vector patterns are programmed into the
memory of the ATE. The VSS is set to 0V and VDD is set to 5.0V by the ATE.
The pattern generator of the ATE issues test vector 0011 and 0101 sequentially
to inputs pin (1) and (2) of the NAND gate via the drivers of the pin cards. The
actual output patterns are then compared with the expected output patterns after
a programmed propagation delay and input to error logic of ATE to decide
whether the gate passes or fails gross functional test.
- 135 -
Figure 12.13: The set-up for IDD test for a NAND gate of CD4011
force voltage is different, which are 0.4V, 0.5V, and 1.5V respectively for
supply voltage 5V, 10V, and 15V test. Figure 12.14 shows the test set-up of IOL
test for one NAND gate. Normally all NAND gates can be tested
simultaneously.
Figure 12.14: The set-up for output low current IOL test
The measured current by the ATE is then compared with the set limit, which are
>0.51mA @5V VDD supply voltage, >1.3mA @10V VDD supply voltage, and
>6.8mA @15V VDD supply voltage.
- 137 -
Figure 12.15: The set-up for output high current IOH test
The measured current by the ATE is then compared with the set limit, which are
<-0.51mA @5V VDD supply voltage, <-1.6mA @10V VDD supply voltage, <1.6mA @10V VDD supply voltage, and <-3.4mA @15V VDD supply voltage.
- 138 -
(a)
(b)
Figure 12.16: The set-up for propagation delay test (a) logic 0 to logic 1 tpLH transition and
(b) logic 1 to logic 0 tpHL transition
There are many other dc and ac parameters to be tested for CD4011. Learners
are encouraged to learn them.
You may notice that so far we have not discussed test at temperature. You
may choose temperature test by heating up the chamber of ATH or cold down
the chamber of ATH. For high temperature testing, it is easy by heating up the
chamber of the handler to the desired temperature. To cold the temperature to 400C or -550C required to piped-in the liquid nitrogen, which is costly and at
time can pose the safety hazard due to cold burn. If it is permitted, you may
perform a guard banding study of each and every parameter so that by
- 139 -
tightening the test limits at room temperature can simulate the failure at either
cold or hot temperature.
engineering effort taken to add in DFT test circuitry in the integrated circuit die
and the circuitry would take up a portion of real estate of the die. However, this
can be offset by long-term benefit in time taken to identify failure and less
development cost for the equipment.
In this Section, learner will learn methods of design for test (DFT), which
includes the fault models, in-Circuit testing, ad hoc testing, scan test, and builtin self test. There are many advanced DFTs for testing to identify and locate
failure for controllability and observability. Learner is encouraged learn them.
as stuck-at-0. The suck-at-0 and stuck-at-1 can also be happened at the output of
the device.
Using the stuck-at-fault model, lets analyse to see how many test vector
patterns are necessary to effectively test the functionality of a 4-input NAND
gate. The layout of the 4-input NAND gat is shown in Fig. 12.18. Based on the
layout, stuck-at-0 (SA0) and stuck-at-1 (SA1) faults can be occurred at either
input A, B, C, or D, or all inputs, and output.
Theoretically, it requires 16 (24) test vector patterns in order to fully test its
functionality. However, if we apply the stuck-at-fault method, the 4-input
NAND can be fully tested with just five test vector patterns, which are 1111,
0111, 1011, 1101, and 1110. Lets find out how we derive to this conclusion.
The truth table of a 4-input NAND gate with stuck-at-fault occurrence is shown
in Fig. 12.19.
- 142 -
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No
Fault
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
SA0
A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SA1
A
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
SA0
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Output
SA1 SA0
B
C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
SA1
C
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
SA0
D
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SA1
D
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
The results show that whenever, there is a stuck-at-0 or stuck-at- 1 at any input
A, B, C, and D, there is a change of output for test vector 0111, 1011, 1101,
1110, and 1111. Thus, test vector pattern 0111, 1011, 1101, 1110, and 1111 are
sufficient to fully test the functionality of a 2-input NAND gate. The rest of test
- 143 -
vectors 0000, 0001, 0010, 0011, 0100, 0101, 0110, 1000, 1001, 1010, and 1100
are redundant.
Under the stuck-at-fault model, its easy to apply test vectors to the input of
an individual logic gate. However, in practice, there is problem to apply the test
vectors to the logic gates that are buried in a circuit and observing the results.
Supposing a circuit has a few combinational and sequential logic gates in
between its primary inputs and the inputs of a 4-input NAND gate that a
designer wants to test, it is not obvious what primary-input test vector, or
sequence of primary-input test vectors must be applied to generate the test
vector pattern 1111 at the NAND-gate inputs. Furthermore, its not obvious
what else is required to propagate the NAND gates output to a primary output
of the circuit.
Sophisticated test-generation program deals with this complexity and
attempt to create a complete test set for a circuit, which is a sequence of test
vector patterns that fully tests each logic gate in the circuit. However, the
computation required can be huge and its quite often just not possible to
generate a complete test vector patterns. With this difficulty, DFT methods
attempt to simplify test-pattern generation by enhancing the controllability and
observability of logic gates in a circuit. A circuit with good controllability and
easy to produce any desired output logic on the internal signals of the circuit by
applying an appropriate test-vector input combination to the primary inputs is
desired. Similarly, a circuit with good observability means that any internal
signal can be easily propagated to a primary output for comparison with an
expected value by the application of an appropriate primary-input combination
is needed. The most common method of improving controllability and
observability is to add test points to tap the additional primary inputs and
outputs during testing.
- 144 -
A technique classified in this category is the use of the bus in a busoriented system for test purposes. Each register has been made loadable from
the bus and capable of being driven onto the bus. Here, the internal logic values
that exist on a data bus are enabled onto the bus for testing purpose. Frequently,
multiplexer can be used to provide alternative signal path during testing. In
CMOS testing, transmission gate and multiplexers provide alternative paths to
routed external test signals. We can see it in the built-in circuit of the scan test
and built-in self test.
Any design should always have a method of resetting the internal state of
the circuit within single clock cycle or at most a few clock cycles. Apart from
making the testing easier, this also makes simulation faster as a few cycles are
required to initialize the circuit is considered short time.
In general, ad hoc testing techniques represent a number of approaches
developed over the years by designers to avoid the overhead of a systematic
approach to testing. While these general approaches are still valid as of today.
rest of the circuit is trying to drive onto the four input pins. The output of 4input NAND-gate can be observed directly on the output pin. With in-circuit
testing, each logic gate can be tested in isolation from the others.
A few key procedures and requirement are needed for performing in-circuit
testing. They are listed in the following sub-sections.
12.5.3.1 Initialization
The initialization is a mandatory to make all logic gates in the circuit to a reset
state. Since the preset and clear input pins of registers and flip-flops are
available in the circuit, one can use ATE to initialize them. However, Fig.
12.20(a) shows an example of a gray-code counter circuit cannot be initialized
because the flip-flops go into an unpredictable state when preset pin (PR) and
clear pin (CLR) are asserted high simultaneously. The right way to handle the
preset and clear inputs is shown in Fig. 12.20(b), which is having separated bias
voltage. The ATE can send logic 0 to clear the counter and then followed by
sending logic 1 to set the counter in ready mode.
(a)
(b)
Figure 12.20: A gray code counter circuit (a) it is not testable (b) it is testable
- 146 -
current driven the output may damage by having all outputs overdriven
simultaneously.
- 148 -
Figure 12.23: The timing diagram of the test for a 3-bit binary counter
The circuit has three combinational circuit blocks. Every block has its input and
output. The MSB combinational block at the right of the circuit received 3
inputs I0, I1, I2 and has one output CO2. If we have the controllability of node Io
and observability at node CO2 then we can have easily test the functionality of
this circuit block by applying the minimum number of test vectors (based on to
stuck-at-fault model) to it. Thus, the key issue is to make I0, I1, I2 control-able
- 149 -
via the chip boundary and CO2 observable via the chip boundary. We will do
similar kind of arrangements for all inputs and outputs to all the combinational
blocks identified in the design.
For better observability and controllability, we replace all the flip-flops of
this counter, with special flip-flops that has a multiplexer connected to the D
input of each flip flop and two additional input pins called scan enable (SE) and
Scan input (SI) for multiplexer of the flip-flop. As shown in Fig. 12.24, the 3-bit
binary counter is now DFT-able. The multiplexer can be selected by scan enable
pin (SE) to allow scan in data to be clocked into the input D of the flip-flop to
produce Q output and scan out results with the relevant edge of clock.
If there is any stuck-at-fault of the combinational block, the scan out result will
reveal the problem. The timing diagram of the scan test for the 3-bit binary
counter is shown in Fig. 12.25.
- 150 -
Figure 12.25: The timing diagram of the scan test for a 3-bit binary counter
- 151 -
If the initial data of the flip-flip is 100, the pseudo-random sequence data
generated six other random patterns after the six clock pulses, which are 011,
111, 110, 100, and 010. This random sequence will repeat for every seven clock
pulses.
A complete feedback shift register (CFSR) is shown in Fig. 12.27. This
linear shift register includes zero state that may be required in some test
situation. An n-bit LFSR can be converted to an n-bit CFSR by adding in an n-1
input NOR gate connected to all output except the MSB output.
After resetting, the initial content of the LFSR is 000. The data content of the
flip-flop (FF1, FF1, and FF0) for the seven clock pulses are 000, 011, 110, 100,
000, and 000. Thus, the compressed signature of the analyzer is 001100.
12.5.5.3 Setup of Built-in Self Test Circuit
The combination of signature analysis and the scan test technique shown in
previous sub-section creates a test structure known as built-in self test BIST or
built-in logic block observation BILBO. Fig. 12.29(a) shows the 3-bit BIST
register and how it is inserted in use for logic circuit test. The 3-bit register is a
scanable, resettable register that can serve as a pattern generator and signature
analyzer. The input C[0] and C[1] specify the mode of operation. In the reset
mode (10), all flip-flops are synchronously initialized to logic 0. In normal
mode (11), the flip-flops behave normally with their Q input feeds to D input. In
the scan mode (10), the flip-flops are configured as a 3-bit shift register between
scan-input (SI) and scan-output (S0). In the test mode (01), the register behaves
- 153 -
(a)
(b)
Figure 12.29: BIST (a) a 3-bit register and (b) PRSG and signature analyzer used for test
circuit
There are many other BIST techniques such as memory BIST, parallel BIST,
which are not covered in this text. Learner is encouraged to learn them.
- 154 -
picture of a de-capsulated quad flat pack QFP plastic packaged integrated circuit.
It shows that exposed die.
Visual inspection can be done to check the integrity of the quality of bond wire
and check the surface to see if there visible defect such as scratch, missing wire,
and chip-off that course the failure of functional test. 200X to 400X optical
inspection can be used to identify the failure due to static electricity defect (due
to handling), micro assembly defect, fabrication defect, and test operation. With
help of circuit layout and the test failure data, learner can identify the location of
failure on the die. If visual inspection and optical inspection can not locate and
identify the failure site, the use scanning electron microscope SEM will help the
reveal the failure site. The picture shown in Fig. 12.31 is a SEM picture
showing failure site of the transistor due to electrostatic discharge ESD.
Figure 12.31: A SEM picture showing the failure site of a MOS transistor
de-cap the package for ceramic package or x-ray the plastic package to locate
and confirm the failure site. For the case of open/short test, it can be due to
missing bond wire or bond wire shorted to adjacent bond wire.
In the case of functional failure like the case of memory array failure, test
data will show the address location of failure that can be traced to a particular
row and column of memory matrices on the integrated circuit with aid of the
layout diagram of the integrated circuit. In this manner, we can correlate the
failure data with physical site of failure.
In the case of ac failure, the correlation of failure data cannot be traced to
the physical failure site. This is because the failure is related with the physical
parameters of the transistor in the integrated circuit. As you have learnt in Unit
3 Parasitic Extraction and Performance, they are related to the dimension and
particularly the doping concentration, and threshold of the transistor. If such
failure occurred, we can check back the data of the process parameters used
during fabrication for further understanding of the failure.
Exercises
12.1. State three methods that can be used to minimize of the design constraints
due to latch-up problem.
12.2. As a design engineer you know that there is an npn parasitic bipolar
junction transistor in the n-MOS transistor strcuture. Name the method
used to in-active this transistor.
12.3. State the reason why there is no diode circuit at the output of the logic
gate to protect against ESD damage.
12.4. The output low voltage (VOL) specification of the CD4011 2-input NAND
gate is given as follow. Draw the test set-up diagram to perform this test.
Limit at Indicated Temperature (0C)
+25
Conditions
Characteristics
Output Low
Voltage
VOL max.
VO
(V)
VIN
(V)
VDD
(V)
0, 5
0, 10
0, 15
5
10
15
-55
-40
+85
+125
Min
Typ.
Max.
Units
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
- 158 -
12.7. A linear feedback shift register is shown in below. Draw the timing
diagram of the register.
12.8. The signature analyzer circuit shown below in scan in data sequence
100110. Find the compressed signature out code assuming the initialized
content of the analyzer is 000.
- 159 -
12.9. We notice most of the time, the failure site of a MOS transistor is found
at the drain site of the transistor. Can you explain the reason?
12.10. Do you think defect caused by assembly processes can be minimized or
eliminated?
12.11. Why it is necessary to ground the operator working in test area to prevent
the static electricity damaging the integrated circuit?
Bibliography
1.
2.
3.
4.
Neil HE Weste and David Harris, CMOS VLSI Design: A Circuits and
Systems Perspective, third edition, Pearson Addison Wesley, 2005.
M. Machael Vai, VLSI Design, CRC Press LLC, 2001.
John P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and
Simulation, Thomson, 2006.
John P. Uyemura, CMOS Logic Circuit Design, Kluwer Academic
Publishers, 2002.
- 160 -
Index
A
In-circuit testing....................................146
L
Layout versus schematic check ............123
Linear feedback shift register ...............152
Load board ............................................130
N
O
Observability.........................................145
Open/short test ......................................134
Output high current...............................138
Output low current................................137
C
CD4011 .................................................132
Ceramic package...................................156
Complete feedback shift register ..........153
Controllability.......................................145
P
Probe test ..............................................126
Propagation delay .................................139
Pseudo-Random Sequence Generator ..152
D
Design rule check..................................122
Device specification..............................132
Device under test...................................129
Dual in line............................................133
Q
Quad flat pack.......................................157
Quiescent device current.......................137
E
Electrical rule check..............................125
Electrostatic discharge ..........................134
Flip-flop ................................................147
Fuming nitric acid .................................156
Scan method..........................................149
Signature analyzer ................................154
Silicon control rectifier .........................123
Gray-code counter.................................147
Gross functional test .............................136
- 161 -
Index
- 162 -