9.

IMPROVED VERSION OF CLASS-B PUSH-PULL AMPLIFIER

The deadband in a class-B push-pull amplifier can be eliminated by properly biasing the
two transistors. Figure 9.1 illustrates the use of two diodes for achieving the proper bias for the
complementary push-pull configuration. We could have used resistors in place of diodes for biasing
the push-pull amplifier. We selected diodes because they provide temperature compensation as
well.

VCC

RC
Q1 npn
D1

D2

R1

v IN

Q2 pnp

RL

iO

vO
_

Q3 npn

R2

RE
VCC

Figure 9.1: Push-pull amplifier biased using two diodes

When the input signal is zero, the output voltage is zero. The voltage at the base of Q1 is
one-diode voltage level higher than zero. Diode D1 ensures that it is so. Likewise, the voltage at
the base of Q2 is one-diode voltage drop lower than zero as ascertained by the diode D2. The
transistor Q3, commonly called the driver, is designed as a class-A amplifier. When it operates at
its Q-point, Q3 in series with RC, D1, D2, and RE, - VCC and VCC forms a closed path for the
current. The voltage drop across RC is VCC VBE1 VCC VD1 where VD1 is assumed to be

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equal to VBE1. The diode D1 can in fact be an NPN transistor like Q1, which is connected as a
diode. The voltage at the node between the two diodes is expected to be zero in the absence of
the input signal. To ensure that it is so, we may have to include small resistors in series with the
diodes. The collector of Q3 is one-diode drop below zero. That is, at the Q-point, VC3 = VD2 =
VEB2. Once again, the diode D2 can in fact be a PNP transistor just like Q2 that is connected as
a diode. The diode D1 and RC form the current mirror. Thus, when the input signal is passing
through zero, the collector current through Q1 is almost equal to that through RC. Likewise, D2 and
Q2 are part of the current mirror.
When the input voltage is positive, the collector of Q3 goes more negative. It makes the
PNP transistor Q2 to turn ON while the NPN transistor Q1 is turned OFF. The voltage output vo
across RL is negative and the output current i O is in opposite direction to that shown in the figure.
The PNP transistor pulls the current through the load resistor.
The output voltage can be expressed as
v O = VCC + VEB,Q 2 + v CE ,Q 3 + i E R E

(9.1)

In order to ascertain the minimum value of the output voltage, the voltage drop across RE
should be small. From the minimum output voltage point of view, RE should be zero. However, we
need RE to satisfy the input resistance requirement, if there is any. There are, of course, many
ways we can meet the input resistance requirement. One of them is to replace Q3 by a Darlington
transistor with very high .
Let us imagine that the maximum voltage drop across RE when the input voltage is at its
peak is 1 V or so. When that happens, the voltage drop across Q3 can be close to its saturation
voltage VCE(SAT) which may be about 0.5 V or so. If VCC is 15 V and the emitter-to-base voltage
drop across Q3 is 0.7 V, then the minimum value of the output voltage, from (9.1), is 12.8 V.
Thus, the emitter-to-collector voltage drop of Q2 is 2.2 V, which is in general higher than its
saturation voltage.
When the input signal goes negative, the collector of Q3 goes positive, Q2 turns OFF, D1
and D2 are ON, and Q1 turns ON. The output voltage is now positive. Resistor RC carries the
collector current of Q3 and the base current of Q1.

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Let the voltage drop across RC be vRC. Now, we can express the output voltage as
v O = VCC v RC VBE ,Q1

(9.2)

From this equation it is clear that vRC should be very small in order to obtain as high an
output voltage as possible. We need RC for the proper biasing of Q1 and Q2 when the input
voltage is zero. When the input signal is at its minimum value, Q3 may be close to its cutoff. When
Q3 enters the cutoff mode, the only current through RC is the base current of Q1. Thus, RC can be
selected on the basis of the base current of Q1. At this time, let us assume that the voltage drop
across RC is about 1 V or so. Assuming VBE,Q1 = 0.7 V, the maximum value of the output voltage,
from (9.2), is 13.3 V. The collector-to-emitter voltage of the NPN transistor Q1 is 1.7 V, which is in
general higher than its saturation voltage. In order to obtain the symmetrical output voltage of 12.8
V, we can, in fact, allow a voltage drop of 1.5 V across RC.
Design the Circuit
Let us assume that each transistor has = 100, and is nearly unity. When the output
voltage is at its maximum value of 12.8 V, the collector current through NPN transistor is
approximately 128 mA for a 100- load resistor. The corresponding base current of Q1 is 1.28
mA. As mentioned earlier, let us allow 1.5 V as the maximum voltage drop across RC when VBE,Q1
is 0.7 V. Thus,
RC =

1 .5 V
= 1.17 k
1.28 mA

Let us select the nearest value of RC as 1 k. It is better to make the selection on the low
side. It will result in a little bit higher output voltage.
The emitter resistance is selected on the basis of dc biasing for Q3. In the absence of
the input signal, the expected voltage drop across RC is 14.3 V (VCC 0.7). The current through
RC is 14.3 mA. Assuming that IE3 is equal to IC3 and allowing for a voltage drop of about 1-V

across RE, we find that

RE =

1V
= 69.93
14.3 mA

The nearest resistor in the crib is 68 . Thus, RE is 68 .

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We can now design the biasing resistors R1 and R2. The voltage drop across R2 is

VR 2 = (14.3 mA)(68) + 0.7 = 1.672 V

If the input resistance requirement is not specified, we are at liberty to choose a current through
R2. I prefer it to be in the neighborhood of 10 times the base current of Q3 in order to minimize the

effect of changes in . If the input resistance requirement is given, then we have no choice other
than satisfying the requirement. The base current in Q3 is
I B3 =

14.3 mA
= 0.143 mA
100

Suppose the input resistance requirement is not given. Then the current through R2 can be
assumed as 10 IB3 = 1.43 mA. Thus,

R2 =

VR 2 1.672
=
= 1.17 k
IR2
1.43

Let us select R2 as 1.2k. We selected R2 on the higher side of its computed value in order
to keep the input resistance high.
The actual voltage at the base of Q3:

VB3 = 15 + (14.3 mA)(68) + 0.7 = 13.32 V

Thus, the voltage drop across R1:

VR1 = 15 (13.32) = 28.32 V

The current through R1:

I R1 = I R 2 + I B3 =

Finally, we compute R1:

R1 =

1.672
+ 0.143 = 1.536 mA
1 .2

28.32
= 18.43 k
1.536

Let us select R1 as 18.47 k (18 k in series with 470 ).

Initial selection of the components is complete.
EXACT ANALYSIS AT THE Q-POINT
Let us perform the exact analysis of the circuit with the following parameters:
R1 = 18.47 k, R2 = 1.2 k, RC = 1 k, RE = 68 , = 100 and = 0.99.

The Thevenin equivalent of the biasing circuit of Q3 can now be determined.

The Thevenin equivalent voltage:

VBB =

The Thevenin equivalent resistance:

RB =

BG/PA2/09A

15 1.2 15 18.47
+
= 13.17 V
19.67
19.67

1.2 18.47
= 1.127 k
19.67

65

May 7, 2002

15 13.17 0.7
= 0.141 mA
1.127 + 101 0.068

Thus the base current of Q3:

I B3 =

The emitter current of Q3:

I E 3 = 101 0.141 = 14.24 mA

The voltage drop across RE:

VRE = (14.24 mA)(68) = 0.97 V

The collector current of Q3:

I C3 = 100 0.141 = 14.1 mA

The voltage drop across RC:

VRC = (14.1 mA)(1 k) = 14.1 V.

This voltage drop should be acceptable although we would like it to be nearly equal to 14.3 V. If the
need be, we can add two resistors in series with the diodes. The value of each resistor must be 0.2
V/14.1 mA = 14.18 .
We do have another choice. We can modify the values of R1 and R2. Let us reduce R2 to 18.33
k (18 k in series with 330 ) and repeat the above calculations.
VBB =

15 1.2 15 18.33
+
= 13.157 V
19.53
19.53

RB =

1.2 18.33
= 1.126 k
19.53

I B3 =

15 13.157 0.7
= 0.143 mA
1.126 + 101 0.068

I C 3 = 100 0.143 = 14.3 mA

I E 3 = 101 0.143 = 14.443 mA

The collector current of 14.3 mA is exactly the current we were aiming to obtain.
Now the voltage drop across RC would be 14.3 V as desired.
The collector-to-emitter voltage of Q3 is
VCEQ,Q3 = 30 (14.3 mA)(1 k) 0.7 0.7 (14.443 mA)(68 ) = 13.32 V
Thus, the Q-point of Q3 is at
VCEQ,Q3 = 13.32 V and ICQ,Q3 = 14.3 mA.
The dc load line intersects the x-axis at 28.6 V (30 0.7 0.7). The dc equivalent
resistance is 1068.69 [1000 + 68/0.99]. Assuming the saturation voltage to be zero, the yintercept is at 26.76 mA [28.6/1068.69].

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The maximum current that is expected through Q3 is when it is on the verge of saturation
and Q2 is ON. This happens when the output voltage is at its minimum (negative value). Let i O be
the current through the load in the direction opposite to that as shown in the figure. Then, it would
be a positive quantity. The base current of Q2 is the i O /101 0.01 i O
Let us assume that all currents are in mA and all resistors are in k.
***

The minimum output voltage can be computed as follows:

The output voltage would be vo = - i O RL = 0.1 i O
The current through RC is (15 0.7 + i O RL) /RC = 14.3 + 0.1 i O mA
The total current in the collector of Q3 is 14.3 + 0.11 i O
Summing the voltages in the loop, we get
i O R L + VEB,Q 2 + v CE ,Q3 + i E ,Q3 R E = 15

Substituting the values, we have

i O (0.1) + 0.7 + v CE ,Q 3 + (14.3 + 0.11 i O )

0.068
= 15
0.99

If we assume that the collector-to-emitter saturation voltage of Q3 is 0.5 V, then

from the above equation the load current in the opposite direction as shown in the figure is
119.17 mA. Thus, the output voltage with the polarity as indicated in the figure for a 100-
load resistance is - 11.92 V. Hence, the minimum output voltage is 11.92 V.
***

The maximum output voltage can be obtained as follows:

Now Q1 is ON and Q2 is OFF. If i O is the output current in mA in the direction indicated in
the figure, then
iO
R C + VBE ,Q1 + i O R L = 15
101

Substituting the values, we obtain i O = 130.12 mA when VBE,Q1 is 0.7 V and RC = 1 k.

Thus, the maximum output voltage is about 13.01 V.
In this example, the symmetric peak-to-peak swing in the output voltage is limited by the minimum
value of the output voltage. If we limit the peak-to-peak output voltage swing to 22-V, we can safely
avoid the operation of Q3 in the cutoff and saturation regions.

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Voltage, Current, and Power gains

In order to gain some understanding of the voltage, current, and power gains of the
amplifier, we can draw its small-signal model as shown in Figure 9.2. The circuit is drawn when the
input signal is negative, Q1 is ON, and Q3 is OFF. The two identical diodes can be represented by
their equivalent resistances as shown.

rd

ib1

rd
_

iin

vin

ib3

r3

ic3

r1

io
RC

RB
RE

ic1

RL v
o
_

Figure 9.2: Small signal model of class-B amplifier when Q1 is ON

Since we have assumed that Q1 and Q3 are identical transistors, their base currents are
also equal. Thus, the equivalent resistance in the base circuit of each transistor is
r1 = r3 =

25 mV
175
0.143 mA

The ac equivalent resistance of each diode is

rd =

25 mV
= 1.75
14.3 mA

The resistance of each diode is very small as compared to other resistances in the circuit. Thus,
we can replace each diode with a short circuit and simplify the above equivalent circuit.
As stated earlier the transistor Q1 conducts when the input voltage is negative. With that
understanding we have reversed the polarity of the input voltage.

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The base current in Q3, in the direction shown, is

i B3 =

v in
r3 + ( + 1) R E

The collector current in Q3 is

i c 3 = i B3 =

v in
r3 + ( + 1) R E

The base current of Q1 can now be computed as

i b1 =

R C i c3
R C v in
=
R C + r1 + ( + 1)R L [R C + r1 + ( + 1)R L ][r3 + ( + 1)R E ]

Finally, the output current and the voltage are

i o = ( + 1) i b1 =
vo = iO R L =
The input resistance:

( + 1) R C v in
[R C + r1 + ( + 1)R L ][r3 + ( + 1)R E ]

( + 1) R C R L v in
[R C + r1 + ( + 1)R L ][r3 + ( + 1)R E ]

R in = R B || [r3 + ( + 1) R E ]

Thus, the input current: i in =

v in
R in

Note that in the above equations, the input voltage vin is a negative quantity. Thus, the voltage and
current gains are negative. That is,

AV =

( + 1) R C R L
[R C + r1 + ( + 1)R L ][r3 + ( + 1)R E ]

AI =

( + 1) R C R in
[R C + r1 + ( + 1)R L ][r3 + ( + 1)R E ]

When we substitute RL = 0.1 k, RE = 0.068 k, RC = 1 k, r1 = r3 = 0.175 k, and = 100 in

the above expressions, we obtain AV = - 12.72 and AI = -123.37. Note that RB = 1.126 k, and
Rin = 0.97 k. Finally, the power gain is approximately 1569.

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We can verify our design using the PSPICE program. The listing of the program is given
below. This program is called Push-Pull amplifier with Dual Supply (PPDS.CIR). Check the listing,
verify its accuracy, and then run it. I have selected an input voltage of 1.7 V from peak-to-peak.
With a voltage gain of 12.72 we will obtain an undistorted peak-to-peak output voltage of nearly 22
V (21.62 V to be exact).
Push-Pull class-B Amplifier, PPDS.CIR
VCC 1 0 DC 15
VEE 0 3 DC 15
VIN 9 0 SIN(0 0.85 10000)
RL 2 0 100
RC 1 8 1K
RE 4 3 68
R2 6 3 1.2K
R1 1 6 18.33K
C1 9 6 100UF
Q1 1 8 2 NPN1
Q2 3 5 2 PNP2
Q3 5 6 4 NPN1
D1 8 7 DIOD
D2 7 5 DIOD
.MODEL DIOD D
.MODEL NPN1 NPN BF=100 IS=1E-14
.MODEL PNP2 PNP BF=100 IS=1E-14
.TRAN 0.05US 150US 0 0.05US
.PROBE
.END
We have plotted the input and output voltages to obtain the voltage gain. We have also sketched
the input and output currents to compute the current gain. Compute these gains from these graphs
in order to verify our theoretical calculations.

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