Sl

No
Theory
1

Subject
Code
P1MAC03

2
3
4
5
6

P1VLC01
P1VLC02
P1VLC03
P1VLC04
P1VLC05

Practical
7
P1VLC06
Total Credits
Sl
No
Theory
1
2
3
4
5
6

M.TECH. VLSI DESIGN

SEMESTER I
Subject

Mathematical Foundations of Electronics

Engineering
VLSI Basic & Concepts
Advanced Digital System Design
VLSI Technology
Verilog Programming
Analog Integrated Circuit Design

3
3
3
3
3

0
1
0
1
1

0
0
0
0
0

3
4
3
4
4

VLSI Design Lab

2
23

Digital CMOS VLSI Design

Testing of VLSI Circuits
VLSI Signal Processing
ASIC Design
VLSI for wireless communication
Elective I

3
3
3
3
3
3

1
1
0
1
0
0

0
0
0
0
0
0

4
4
3
4
3
3

Embedded system and advanced VLSI

Design Lab

SEMESTER II
Subject

Subject
Code
P2VLC07
P2VLC08
P2VLC09
P2VLC10
P2VLC11
*****

Practical
7
P2VLC12
Total Credits
Sl
Subject
No
Code
Theory
1
*****
2
*****
3
*****
Practical
4
P3VLC13
Total Credits
Sl
No
Practical
1

Subject
Code
P4VLC14

23
SEMESTER III
Subject

Elective II
Elective III
Elective IV

3
3
3

0
0
0

0
0
0

3
3
3

Project Phase I

12

6
15

SEMESTER IV
Subject

Project Phase II

Total Credits
73
L Lecture; T Tutorial; P Practical; C Credit

24

12
12

Over all Total Credits =

Sl
No
1

LIST OF ELECTIVES FOR SEM II ELECTIVE-I

Subject
Subject
L
Code
PEVLC15
VLSI System Design
3

PEVLC16

PEVLC17

PEVLC18

PEVLC19

Solid State Device Modeling and

Simulation
Embedded System Design

DSP Processor Architecture and

Programming
FPGA Based Signal Processing

LIST OF ELECTIVES FOR SEM III ELECTIVE-II

Sl
No
1

Subject
Code
PEVLC20

Subject
Computer Aided Design for VLSI

PEVLC21

Physical Design of VLSI Circuits

PEVLC22

High Speed Switching Architecture

PEVLC23

Design of VLSI in Embedded System

PEVLC24

Advanced Micro Processor and

Microcontrollers

LIST OF ELECTIVES FOR SEM III ELECTIVE-III

Sl
No
1

Subject
Code
PEVLC25

Subject
Hardware software co-design

PEVLC26

Nano technology

PEVLC27

Introduction to MEMS System Design

PEVLC28

Wireless Sensor Networks

PEVLC29

Control System on Chip

LIST OF ELECTIVES FOR SEM III ELECTIVE-IV

Sl
No
1

Subject
Code
PEVLC30

Subject

Low Power VLSI Design

PEVLC31

Semiconductor memory design &

Processing

PEVLC32

PEVLC33

Computer architecture and Parallel

Processing
Data Converters

PEVLC34

Network on Chip

L Lecture; T Tutorial; P Practical; C Credit

SEMESTER I
P1MAC03 MATHEMATICAL FOUNDATIONS OF ELECTRONICS ENGINEERING L T P C
( VLSI)
3003
Aim: To give exposure to different applied mathematics techniques, this will be useful for
designing efficient (area/speed) electronic automation tools for VLSI design.
Objective: To impart knowledge on Fuzzy Logic, Differential Equations, Graph Theory and
Algorithms.
UNIT I Fuzzy Logic
9+3
Basic concepts of fuzzy logic fuzzy sets operations of fuzzy sets properties of fuzzy sets
fuzzy relations composition of fuzzy relations fuzzy propositions fuzzy quantifiers,
fuzzy processor.
UNIT II Queuing Models
9+3
Basics of queuing models Poisson queue systems transient state probability steady state
probabilities single and multi-server models with finite and infinite capacity Littles
formula - (M-G-1) queueing model Pollaczek-Khinchine formula
UNIT III Differential Equations
9+3
Solution of first-order differential equations using numerical methods. Solution of physical
situations that can be modeled by first-order differential equations. Solution of higher order
homogeneous differential equations with constant coefficients. Solution of nonhomogeneous higher-order differential equations using the method of Undetermined
Coefficients, Solution of non-homogeneous higher-order differential equations using the
method of Variation of Parameters
UNIT IV Graph Theory
9+3
Graphs Introduction Isomorphism Sub graphs Walks, Paths, Circuits Connectedness
Components Euler Graphs Hamiltonian Paths and Circuits Trees Properties of trees
Distance and Centers in Tree Rooted and Binary Trees.
UNIT V Algorithms
9+3
Algorithms: Connectedness and Components Spanning tree Finding all Spanning Trees of
a Graph Set of Fundamental Circuits Cut Vertices and separability.
Shortest Path
Algorithm DFS Planarity Testing Isomorphism
TOTAL: 45+15=60 Periods
REFERENCES:
1. G.J. Klir and B. Yuan, Fuzzy Sets and Fuzzy Logic: Theory and Applications, PHI
Learning Private Limited, New Delhi, 1997.
2. H. A. Taha, Operations Research: An Introduction, seventh edition, Pearson
Education, New Delhi, 2002.
3. G.H. Golub and C.H. Van Loan, Matrix Computations, third edition, Johns Hopkins
University Press, London, 1996.
4.
Narsingh Deo, Graph Theory: With Application to Engineering and Computer
Science, PHI, 2003.
5. R.J. Wilson, Introduction to Graph Theory, Fourth Edition, Pearson Education, 2003.
6. Differential Equations with Boundary-Value Problems, 7th ed. Zill & Cullen,
Thomson/Brooks Cole, 2009
7. V. Sundarapandian, Probability, Statistics and Queuing Theory, PHI Learning, New
Delhi, 2009.

URL:
https://noppa.lut.fi/noppa/opintojakso/bm20a3101/.../lecture_1_2.pdf
http://en.wikipedia.org/wiki/Fuzzy_set
http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/sbaa/report.fuzzysets.html
http://www.dia.fi.upm.es/~mgremesal/MIR/slides/Lesson%202%20(Fuzzy
%20Propositions).pdf
itlab.ee.nsysu.edu.tw/course/97aSC/part/ppt/Part06_(8.1-5).ppt
en.wikipedia.org/wiki/queueing_theory
www.cs.utexas.edu/~browne/.../papers/simplequeuingmodelspdf.pdf
web.pdx.edu/~stipakb/.../queuingmodelsingleserverformulas.html
www.slideshare.net/amitcyrus/queuing-theory
http://www.efunda.com/math/ode/linearode_consthomo.cfm
http://www.cliffsnotes.com/study_guide/Constant-Coefficients.topicArticleId-19736,articleId19720.html
http://www.btechguru.com/pro_one/keywordLevel~Electronics%20and
%20Communication~Differential%20equation%20~Higher%20order%20linear%20differential
%20equations%20with%20constant
%20coefficients~4134d566a650233c~0bf2d36945f81b5c~926241ff6153f10b~list.html
http://ocw.mit.edu/courses/mathematics/18-03-differential-equations-spring-2010/videolectures/lecture-7-first-order-linear-with-constant-coefficients/
http://www.math.neu.edu/~massey/Massey/Massey_docs/class/1stOrderLaplace.pdf
http://math.info/Differential_Equations/Laplace_Linear_DiffEqn_ConstCoef/
http://www.academicearth.org/lectures/laplace-transform-to-solve-linear-odes
http://www.sosmath.com/diffeq/second/variation/variation.html
http://tutorial.math.lamar.edu/Classes/DE/VariationofParameters.aspx
http://tutorial.math.lamar.edu/Classes/DE/UndeterminedCoefficients.aspx
http://www.cliffsnotes.com/study_guide/The-Method-of-UndeterminedCoefficients.topicArticleId-19736,articleId-19721.html
nptel.iitm.ac.in/courses/Webcourse-contents/IIT...2/node78.html
http://www.efunda.com/math/ode/linearode_undeterminedcoeff.cfm
http://www.csd.uoc.gr/~hy583/reviewed_notes/euler.pdf
http://webspace.ship.edu/deensley/discretemath/flash/ch7/sec7_7/hamiltongraphs.html
http://en.wikipedia.org/wiki/Rooted_binary_tree
www.cis.upenn.edu/~matuszek/cit594-2012/.../09-binary-trees.ppt
www.math.northwestern.edu/~mlerma/courses/cs310.../dm-bintrees.pdf
http://en.wikipedia.org/wiki/Graph_isomorphism
www.uow.edu.au/~bmaloney/wuct121/GraphsWeek10Lecture2.pdf
http://mathworld.wolfram.com/IsomorphicGraphs.html
http://www.cs.princeton.edu/~rs/AlgsDS07/15ShortestPaths.pdf
http://en.wikipedia.org/wiki/Dijkstra's_algorithm
http://en.wikipedia.org/wiki/Shortest_path_problem
Beyond the syllabus:
Normalitys, convexity and concavity of Fuzzy sets. Open and closed jackson networks in
Queueing theory. Coloring of graphs, Bellman-Ford algorithm for shortest path .

P1VLC01 VLSI BASICS & CONCEPTS

PC

L T

3003
AIM
To give an introduction to basic MOS transistor theory, MOS processing technologies and
HDL programming
OBJECTIVES
To impart knowledge on CMOS circuits and various factors to be considered for CMOS
circuit design.
Different processing technologies (n-well, p-well, twin tub )
HDL programming methods for sequential and combinational circuits
UNIT I VLSI BASICS, CMOS CIRCUIT AND LOGIC DESIGN
9
Basics of VLSI, VLSI Design flow, Front end and back end VLSI design, MOS transistor,
transistor as a switch ,CMOS MOS logic gate design, physical design of basics logic gates
,CMOS inverters and its Characteristics, Power dissipation Estimation of resistance,
capacitance, inductance ,CMOS logic structures design.
UNIT II VLSI CIRCUIT CHARACTERIZATION AND PERFORMANCE
9
Secondary order effects, CMOS gate transistor sizing, sizing routing conductors, charge
sharing, Design margin, yield, reliability, Scaling of MOS transistor dimensions and Layout
design rules
UNIT III CMOS CIRCUIT ESTIMATION AND LOGIC DESIGN
9
Power dissipation Estimation of resistance, capacitance, and inductance .CMOS logic
structures design, Clocking strategies.
UNIT IV CMOS PROCESSING TECHNOLOGY

Crystal growth process, CMOS technologies- p-well process, n-well process, twin tub
process and silicon on insulator process.
UNIT V BASICS OF FPGA AND ASIC

ASIC design flow, types of ASICs, Basic testing methods for ASICs,
FPGA flow, Device programming, Different FPGA structures.
TOTAL = 45 periods
BEYOND THE SYLLABUS
Epitaxy, Deposition, Ion-implantation, and Diffusion

REFERENCES:
1.
Weste, Eshraghian, Principles of CMOS VLSI design, 2 nd Edition Addison Wesley,
1994.
2. Douglas A Pucknell and Kamaran Eshragian, Basic VLSI design , 3rd edition, PHI, 1994.
3.Samir Palnitkar , Verilog HDL Guide to digital design and synthesis , III edition ,
Pearson Eduaction
4. S.IMAM & M.PEDRAM, Logic synthesis for Low Power VLSI Designs, Kluwer
Academic publishers, 1998.
URLs
1. http://www.nptel.iitm.ac.in/courses/10610503
2. http://www.aicdesign.org/scnotes/2002notes/Chapter02-2UP(8_13_02).pdf

P1VLC02 ADVANCED DIGITAL SYSTEM DESIGN

LTPC
3104

AIM
To expose the students to the fundamentals of digital logic based system design.
OBJECTIVES
To impart knowledge on
Basics on Synchronous & Async digital switching design.
Design & realisation of error free functional blocks for digital systems
UNIT I
9
Review of sequential circuits, Mealy & Moore Models, Analysis & Synthesis of Synchronous
sequential circuits, Introduction to VHDL, design units, data objects, signal drivers, inertial
and transport delays, delta delay, VHDL data types, concurrent and sequential statements.
UNIT II
9
Digital system design Hierachy, ASM charts, Hardware description language, Control logic
Design Reduction of state tables, State Assignments, Subprograms Functions, Procedures,
attributes, generio, generate, package, IEEE standard logic library, file I/O, test bench,
component declaration, instantiation, configuration
UNIT III
9
Analysis and synthesis of Asynchronous sequential circuits, critical and non-critical races,
Essential Hazard
UNIT IV
9
Combinational and sequential circuit design with PLDs , Introduction to CPLDs & FPGAs,
Combinational logic circuit design and VHDL implementation of following circuits first
adder, Subtractor, decoder, encoder, multiplexer, ALU, barrel shifter, 4X4 key board encoder,
multiplier, divider, Hamming code encoder and correction circuits
UNIT V
9
Fault Modeling
Fault classes and models Stuck at faults, Bridging faults, Transition and Intermittent faults.
Fault Diagnosis of combination circuits by conventional methods- Path sensitization
technique, Boolean different method and Kohavi algorithm.
TOTAL: 45+15(Tutorial) =60 Periods
TEXT BOOK:
1. Digital principles and design By Donald D.Givone Tata McGraw Hill
2. Digital Design By Morris Mano- 3rd Edition, PHI
Beyond the Syllabus
UML based modeling, Wireless sensor networks, Automatic test pattern genration
REFERENCE BOOKS:
1. Digital circuits and logic design By Samuel C.Lee, PHI. (Unit-V only)
2. Logic Design Theory By N.N.Biswas, PHI.
3. Switching and Finite Automata Theory By Kohavi ZVI, 2nd Edition, TMH.
URLs:
1. https://www.cs.washington.edu/education/courses/567/01au/project/sueDocs/tutorial2.pdf
2. http://www.ipfn.ist.utl.pt/EU-PhD/1stedition/BrownFPGA96.pdf
P1VLC03 VLSI TECHNOLOGY

LTPC
3 0 0 3
7

AIM
To make the students to learn the complete flow of IC fabrication, manufacturing and testing.
OBJECTIVE
To impart knowledge on
Lithography techniques
Crystal growth
Complete flow of IC fabrication
UNIT I
9
CRYSTAL GROWTH, WAFER PREPARATION, EPITAXY AND OXIDATION
Electronic Grade Silicon, Czochralski crystal growing, Silicon Shaping, processing
consideration, Vapor phase Epitaxy, Molecular Beam Epitaxy, Silicon on Insulators, Epitaxial
Evaluation, Growth Mechanism and kinetics, Thin Oxides, Oxidation Techniques and
Systems, Oxide properties, Redistridution of Dopants at interface, Oxidation of Poly Silicon,
Oxidation inducted Defects.
UNIT II
LITHOGRAPHY AND RELATIVE PLASMA ETCHING

Optical Lithography, Electron Lithography, X-Ray Lithography, Ion Lithography, Plasma

properties, Feature Size control and Anisotropic Etch mechanism, relative Plasma Etching
techniques and Equipments,
UNIT III
9
DEPOSITION, DUFFUSION, ION IMPLEMENTATION AND METALISATION
Deposition process, Polysilicon, plasma assisted Deposition, Models of Diffusion in Solids,
Flicks one dimensional Diffusion Equation Atomic Diffusion Mechanism Measurement
techniques - Range theory- Implant equipment. Annealing Shallow junction High energy
implantation Physical vapour deposition Patterning.
UNIT IV
PROCESS SIMULATION AND VLSI PROCESS INTEGRATION

Ion implantation Diffusion and oxidation Epitaxy Lithography Etching and DepositionNMOS IC Technology CMOS IC Technology MOS Memory IC technology - Bipolar IC
Technology IC Fabrication.
UNIT V
9
ANALYTICAL, ASSEMBLY TECHNIQUES AND PACKAGING OF VLSI DEVICES
Analytical Beams Beams Specimen interactions - Chemical methods Package types
banking design consideration VLSI assembly technology Package fabrication technology
TOTAL: = 45 periods
BEYOND THE SYLLABUS:
BiCMOS Technology
Key process steps in Device Fabrication.

REFERENCES:
1. S.M.Sze, VLSI Technology, Mc.Graw.Hill Second Edition. 1998.
2.Amar mukherjee, Introduction to NMOS and CMOS VLSI System design Prentice Hall
India.2000.
3.James D Plummer, Michael D. Deal, Peter B.Griffin, Silicon VLSI Technology fundamentals
practice and Modeling, Prentice Hall India.2000.
4. Wai Kai Chen,VLSI Technology CRC press, 2003
URLs
1. http://www.nptel.iitm.ac.in/video.php?subjectId=117106093
2. http://www.authorstream.com/Presentation/Niteesh-84640-vlsi-technologyentertainment-ppt-powerpoint/

P1VLC04 VERILOG PROGRAMMING

LTPC
310
4
AIM
To enable the student to understand and write the Verilog Programes
OBJECTIVE
To impart knowledge on
Different data types
Different programming methods
Verilog synthesis
Unit I Digital design with verilog HDL & Hierarchical modeling concepts
Design Flow, Trends in HDL, Design Methodologies, Modules, Instances, Basic Conceptslexical conventions, Data types, System tasks and compiler directives.
Unit 2 Modules and ports
Module definitions, port declaration, connecting ports, hierarchical name referencing.
Unit 3 Gate level and dataflow modeling
Gate level: Modeling using basic, verilog gate primitives, Different timings-rise, fall, min,
max, typical
Dataflow: continuos assignments, delay specification, expressions, operators and operands.
Unit 4 Behavioral Modeling
Structured procedures, initial and always statements, blocking and non blocking statements,
delay control,event control, conditional statement, multiway branching, loops, sequential
and parrelel blocks
Unit 5 Logic synthesis with verilog HDL
Synthesis Design flow, verilog synthesis, verification with gate level netlist, Design partition,
sequential circuit sysnthesis.
TOTAL: 45+15(Tutorial) =60 PERIODS
BEYOND THE SYLLABUS
Gotchas from system verilog, RTL modeling of Gotchas,Basics of Gotachas Programming
REFERENCES:
1. Verilog HDL by Samir Palnitkar, Sunmicro systems Press, Prentics Hall
2. Hdl Programming Fundamentals: Vhdl And Verilog( Series - Davinci Engineering )
(Hardcover - 2006/01/01) by Nazeih M. Botros
URLs:
1. http://www.asic-world.com/verilog/veritut.html
2. http://www.ece.umd.edu/courses/enee359a/verilog_tutorial.pdf

10

P1VLC05ANALOG INTEGRATED CIRCUIT

C

DESIGN

AIM
To expose the students to the fundamentals of Analog VLSI design

LTP
3104

OBJECTIVE
To impart knowledge on
Basics of Analog VLSI
Amplifiers using MOS loads
Noise analysis in amplifiers
To understand the Analog VLSI
UNIT I SINGLE STAGE AMPLIFIERS
9
Common source stage, Source follower, Common gate stage, Cascode stage, Single ended
and differential operation, Basic differential pair, Differential pair with MOS loads
UNIT II FREQUENCY RESPONSE AND NOISE ANALYSIS
9
Miller effect ,Association of poles with nodes, frequency response of common source stage,
Source followers, Common gate stage, Cascode stage, Differential pair, Statistical
characteristics of noise, , noise in differential amplifiers.
UNIT III OPERATIONAL AMPLIFIERS
9
Concept of negative feedback, Effect of loading in feedback networks, operational amplifier
performance parameters, One-stage Op Amps, Two-stage Op Amps, Input range limitations,
Gain boosting, slew rate, power supply rejection, noise in Op Amps.
UNIT IV STABILITY AND FREQUENCY COMPENSATION
9
General considerations, Multipole systems,Phase Margin, Frequency Compensation,
Compensation of two stage Op Amps, Slewing in two stage Op Amps, Other compensation
techniques.
UNIT V
BIASING CIRCUITS
9
Basic current mirrors, cascode current mirrors, active current mirrors, voltage references,
supply independent biasing, temperature independent references.
BEYOND THE SYLLABUS:
1. Noise in single stage amplifiers
2. PTAT current generation
3. Constant-Gm Biasing
REFERENCES:
1. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw Hill,
2001
2. Willey M.C. Sansen, Analog design essentials, Springer, 2006.
3. Grebene, Bipolar and MOS Analog Integrated circuit design, John Wiley & sons,Inc.,
2003.
4. Phillip E.Allen, DouglasR.Holberg, CMOS Analog Circuit Design, Second edition,
Oxford University Press, 2002
URLs:
11

1. uhaweb.hartford.edu/ilumokanw/Intro567.ppt
2. http://co-learn.in/sites/default/files/courses-pdfs/EE618-L1.pdf
P1VLC06 VLSI DESIGN LAB
C

L T P
0 02 2

AIM

To give hands on experience on Electronic Design Automation Tools for digital circuits. Also
to learn Verilog programming in detail
OBJECTIVE
At the end of this lab session student will understand
Writing HDL codes
Working on different Mentor Graphics tools
List of experiments
1. Write HDL code for half adder, full adder, MUX, DEMUX, encoder, decoder code and
simulate and synthesis
2. Write HDL code for synchronous and asynchronous Flip Flops and Counters and
simulate and synthesis
3. Verify the outputs of above experiment on SPARTAN kit
4. Draw schematic for an inverter and universal gates and simulate
5. Draw layout for above designs
6. Perform DRC and LVS check for the above designs using
BEYOND THE SYLLABUS
1. Implementation of sequence detection using FSM modeling.
2. Simulation of NMOS and CMOS circuits for any Boolean expression in SPICE.

12

SEMESTER II
P2VLC07 DIGITAL CMOS VLSI DESIGN
L T PC

3 1
4

AIM:
To have the detail study of Digital CMOS design

OBJECTIVE
To impart knowledge on
MOS device modeling
Diferente combinational logic circuits
Clocking methods for sequential circuits
UNIT I

MOS TRANSISTOR PRINCIPLES

9
MOS Technology and VLSI, Process parameters and considerations for, MOS and CMOS,
Electrical properties of CMOS circuits and Device modeling. CMOS Inverter Scaling CMOS
circuits, Scaling principles and fundamental limits.
UNIT II COMBINATIONAL LOGIC CIRCUITS
9
Propagation Delays, Stick diagram, Layout diagrams, Examples of combinational logic
design, Elmores constant, Dynamic Logic Gates, Pass Transistor Logic, Power Dissipation,
Low Power Design principles.
UNIT III SEQUENTIAL LOGIC CIRCUITS
9
Static and Dynamic Latches and Registers, Timing Issues, Pipelines, Clocking strategies,
Memory Architectures, and Memory control circuits, Synchronous and Asynchronous Design.
UNIT IV DESIGNING ARITHMETIC BUILDING BLOCKS
9
Data path circuits, Architectures for Adders, Accumulators, Multipliers, Barrel Shifters, Speed
and Area Tradeoffs
UNIT V IMPLEMENTATION STRATEGIES
9
Full Custom and Semicustom Design, Standard Cell design and cell libraries, FPGA building
block architectures,
FPGA interconnect routing procedures, Benchmark Circuits, Case
Studies.
TOTAL: 45+15(Tutorial)=
PERIODS
BEYOND THE SYLLABUS:
The Active and Poly layers
Electrostatic Discharge protection
REFERENCES
1. Jan Rabaey, Anantha Chandrakasan, B Nikolic, Digital Integrated Circuits: A
Perspective. Second Edition, Feb 2003, Prentice Hall of India.

Design

13

2. N.Weste, K. Eshraghian, Principles of CMOS VLSI Design. Second Edition, 1993

Addision Wesley,
3.
4. M J Smith, Application Specific Integrated Circuits, Addisson Wesley, 1997
5. Anantha Chandrakasan, W.J, Bowhill and F.Fox, Design of High Performance
Microprocessor Circuits, John Wiley, 2000.
URLs:
1.http://www.pdx.edu/nanogroup/sites/www.pdx.edu.nanogroup/files/2013_Combinational_an
d_Sequential_Logic_Circuits_0.pdf
2. http://www.ami.ac.uk/courses/ami4407_dicdes/u03/
P2VLC08 TESTING OF VLSI CIRCUITS
LTPC
3104
AIM
To make the student to understand the need for testing, difficulty in testing, and different
methods of testing
OBJECTIVES
To impart knowledge on
Various faults and fault models
Techniques for testing of combinational circuits, sequential circuits, memory and
embedded RAMs
UNIT I

Introduction to Testing - Faults in digital circuits - Modeling of faults - Logical Fault Models Fault detection - Fault location - Fault dominance - Logic Simulation - Types of simulation Delay models - Gate level Event-driven simulation.
UNIT II

Test generation for combinational logic circuits - Testable combinational logic circuit design Test generation for sequential circuits - design of testable sequential circuits.
UNIT III

Design for Testability - Ad-hoc design - Generic scan based design - Classical scan based
design - System level DFT approaches.
UNIT IV

Built-In Self Test - Test pattern generation for BIST - Circular BIST - BIST Architectures Testable Memory Design - Test algorithms - Test generation for Embedded RAMs
UNIT V

Logic Level Diagnosis - Diagnosis by UUT reduction - Fault Diagnosis for Combinational
Circuits - Self-checking design - System Level Diagnosis.
TOTAL: 45+15(Tutorial) = 60 periods
BEYOND THE SYLLABUS:
14

Testing Embedded Applications

REFERENCES:
1. M. Abramovici, M.A. Breuer and A.D. Friedman, "Digital Systems and Testable Design"
Jaico Publishing House, 2002.
2. P.K. Lala, "Digital Circuit Testing and Testability", Academic Press, 2002.
3. M.L. Bushnell and V.D. Agrawal, "Essentials of Electronic Testing for Digital, Memory and
Mixed-Signal VLSI Circuits", Kluwar Academic Publishers, 2002.
4. A.L. Crouch, "Design for Test for Digital IC's and Embedded Core Systems", Prentice Hall
International, 2002.
URLs:
1. http://www.ece.uc.edu/~wjone/Comb-TG.pdf
2. www.ece.mcgill.ca/~zzilic/649/hh.ppt
P2VLC09 VLSI SIGNAL PROCESSING
L T P C
30 0 3
AIM
To study the signal processing in VLSI prospective
OBJECTIVE
To impart knowledge on

Programming processor

Different convolution techniques

Arithmetic architectures
UNIT I
INTRODUCTION TO DSP SYSTEMS
9
Introduction To DSP Systems -Typical DSP algorithms; Iteration Bound
data flow graph representations, loop bound and iteration bound, Longest
path Matrix algorithm; Pipelining and parallel processing Pipelining of FIR
digital filters, parallel processing, pipelining and parallel processing for low
power.
UNIT II
RETIMING
9
Retiming - definitions and properties; Unfolding an algorithm for
Unfolding, properties of unfolding, sample period reduction and parallel
processing application; Algorithmic strength reduction in filters and
transforms 2-parallel FIR filter, 2-parallel fast FIR filter, DCT algorithm
architecture transformation, parallel architectures for rank-order filters,
Odd- Even Merge- Sort architecture, parallel rank-order filters.
UNIT III
FAST CONVOLUTION
9
Fast convolution Cook-Toom algorithm, modified Cook-Took algorithm;
Pipelined and parallel recursive and adaptive filters inefficient/efficient
single channel interleaving, Look- Ahead pipelining in first- order IIR filters,
Look-Ahead pipelining with power-of-two decomposition, Clustered LookAhead pipelining, parallel processing of IIR filters, combined pipelining and
parallel processing of IIR filters, pipelined adaptive digital filters, relaxed
look-ahead, pipelined LMS adaptive filter.
UNIT IV
BIT-LEVEL ARITHMETIC ARCHITECTURES
9
Scaling and roundoff noise- scaling operation, roundoff noise, state variable
description of digital filters, scaling and roundoff noise computation,
15

roundoff noise in pipelined first-order filters; Bit-Level Arithmetic

Architectures- parallel multipliers with sign extension, parallel carry-ripple
array multipliers, parallel carry-save multiplier, 4x 4 bit Baugh-Wooley
carry-save multiplication tabular form and implementation, design of
Lyons bit-serial multipliers using Horners rule, bit-serial FIR filter, CSD
representation, CSD multiplication using Horners rule for precision
improvement.
UNIT V

PROGRAMMING DIGITAL SIGNAL PROCESSORS

Numerical Strength Reduction subexpression elimination, multiple

constant multiplications, iterative matching. Linear transformations;
Synchronous, Wave and asynchronous pipelining- synchronous pipelining
and clocking styles, clock skew in edge-triggered single-phase clocking,
two-phase clocking, wave pipelining, asynchronous pipelining bundled data
versus dual rail protocol; Programming Digital Signal Processors general
architecture with important features; Low power Design needs for low
power VLSI chips, charging and discharging capacitance, short-circuit
current of an inverter, CMOS leakage current, basic principles of low power
design.
TOTAL: 45 PERIODS
BEYOND THE SYLLABUS
Folding and unfolding, Systolic architecture Design, Digital lattice Filter
Structures
REFERENCES
1. Keshab K.Parhi, " VLSI Digital Signal Processing systems,
Design and implementation ", Wiley, Inter Science, 1999.
2. Gary Yeap, Practical Low Power Digital VLSI Design, Kluwer
Academic Publishers, 1998.
3. Mohammed Ismail and Terri Fiez, Analog VLSI Signal and Information
Processing ", Mc Graw-Hill, 1994.
4. S.Y. Kung, H.J. White House, T. Kailath, VLSI and Modern Signal
Processing ", Prentice Hall, 1985.
5. Jose E. France, Yannis Tsividis, " Design of Analog - Digital VLSI Circuits
for Telecommunication and Signal Processing ", Prentice Hall, 1994.
URLs:

1. http://www.ece.umn.edu/users/parhi/SLIDES/chap13.pdf
2. www.ece.umn.edu/groups/ddp/index.html

16

P2VLC10 ASIC DESIGN

LTPC
310

4
AIM
To study the Design of ASIC, logic cells of various suppliers
OBJECTIVES
To impart knowledge on
CMOS and ASIC library design,
The types of programming, architecture of logic cells and I/O cells,
Different techniques of interconnection.
To understand about partitioning, floor planning, placement and routing techniques.
UNIT IINTRODUCTION TO ASICS, CMOS LOGIC AND ASIC LIBRARY DESIGN

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic
Cell Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic
Capacitance- Logical effort Library cell design - Library architecture.
UNIT II PROGRAMMABLE ASICS, PROGRAMMABLE ASIC LOGIC CELLS AND
PROGRAMMABLE ASIC I/O CELLS

Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT Xilinx LCA Altera FLEX - Altera MAX DC & AC inputs and outputs - Clock & Power inputs Xilinx I/O blocks.
UNIT III PROGRAMMABLE ASIC INTERCONNECT, PROGRAMMABLE ASIC DESIGN
SOFTWARE AND LOW LEVEL DESIGN ENTRY
9
Actel ACT -Xilinx LCA - Xilinx EPLD, Spartran IIIE (architecture,interfacing) - Altera MAX 5000
and 7000 - Altera MAX 9000 - Altera FLEX Altera Cyclone II(architecture , interfacing )
Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level design
language - PLA tools -EDIF- CFI design representation.
UNIT IV ASIC CONSTRUCTION, FLOOR PLANNING, PLACEMENT AND ROUTING
9
System partition - FPGA partitioning - partitioning methods - floor planning - placement physical design flow global routing - detailed routing special routing - circuit extraction DRC.
UNIT V LOGIC SYNTHESIS, SIMULATION AND TESTING
9
Basic concepts- identifiers- gate primitives, gate delays, operators, timing controls,
procedural assignments conditional statements, Data flow and RTL, structural gate level
switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches,
Structural gate level description of decoder, equality detector, comparator, priority encoder,
half adder, full adder, Ripple carry adder, D latch and D flip flop. Different counters and FSM
modeling
TOTAL: 45+15(Tutorial) = 60 periods
BEYOND THE SYLLABUS:
FPGA Fabrics, Permanently programmed FPGA

17

REFERENCES:
1. M.J.S .Smith, "Application Specific Integrated Circuits, Addison -Wesley Longman Inc.,
1997.
2. Farzad Nekoogar and Faranak Nekoogar, From ASICs to SOCs: A Practical Approach,
Prentice Hall PTR, 2003.
3. Wayne Wolf, FPGA-Based System Design, Prentice Hall PTR, 2004.
4. R. Rajsuman, System-on-a-Chip Design and Test. Santa Clara, CA: Artech House
Publishers, 2000.
5. F. Nekoogar. Timing Verification of Application-Specific Integrated Circuits (ASICs).
Prentice Hall PTR, 1999.
6. Xilinx, Altera document should be given
7. J.Bhasker: Verilog HDL primer, BS publication,2001
8. Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003
URLs:
1. http://www.ece.ncsu.edu/asic/tutorials/tutor1/tutor1.pdf
2. http://www.asic-world.com/

18

P2VLC11 VLSI FOR WIRELESS COMMUNICATION

LTPC
AIM
To study the wireless communication in VLSI perspective

300 3

OBJECTIVE
To impart knowledge on
Data converters
Coding algorithms and techniques
UNIT I
ANALOG TO DIGITAL CONVERSION
9
Performance metrics for Analog-to-digital converters, sampling, band-pass sampling,
quantization, Types of Analog-to-digital converters, Sigma Delta Analog-to-digital converters.
UNIT II
CODING THEORY ALGORITHMS AND ARCHITECTURE
9
Convolution codes, trellis diagram, viterbi algorithm, soft input decoding, soft output
decoding, Turbo codes, LDPC coding, concatenated convolution codes, weight distribution,
Space-Time codes, spatial channels, performance measure, Orthogonal space-time block
codes, spatial multiplexing.
UNIT III
TRANSCIEVER ARCHITECTURE AND ISSUES
9
Receiver Architectures, Superheterodyne receiver, Image rejection receiver,-Hartley and
Weaver, Zero IF receiver, Low IF receiver, Transmitter architecture, Superheterodyne
transmitter, Direct up transmitter, Two-step-up transmitter, Transceiever architectures for
modern wireless systems, Case study.
UNIT IV
OFDM SYSYTEM
9
Principle, propagation characteristics,principle, mathematical model, OFDM baseband signal
processing,Receiver design, Automatic gain control and DC offset compensation, codesign of
Automatic gain control and timing synchronization, codesign of filtering and timing
synchronization, Transmit chain setup.
UNIT V
ANALOG IMPAIRMENT AND ISSUES
9
Receiver sensitivity and noise figure, DC offsets, LO leakage, Receiver interferers and
intermodulation distortion, Image rejection, Quadrature balance and relation to Image
rejection, relation to EVM, Peak to average power ratio , Local oscillator pulling in PLL, effect
of phase noise in PLL, Effect of phase noise on OFDM systems, Effect of frequency errors on
OFDM systems.
TOTAL: 45
PERIODS
BEYOND SYLLABUS
Low Noise amplifiers, active & passive Mixers, Frequency synthesizers
REFERENCES
1. Pui-In Mak, Seng-Pan U, Rui Paulo Martins, Analog-baseband architectures and
Circuits for multistandard and low voltageWireless transceivers, springer, 2007.
2. Emad N. Farag, Mohamed I. Elmasry, Mixed signal VLSI Wireless design
Circuits and systems, Kluwer Academic Publishers, 2002.
3. Andre Neubauer, Jurgen Freudenberger, Volker Kuhn, Coding theory, Algorithms,
Architectures and Applications, John Wiley & Sons,2007.
4. Wolfgang Eberle, Wireless Transceiver Systems Design,Springer, 2008.
19

URLs:
1. http://www.scribd.com/doc/90696226/Coding-Theory-Algorithms-Architectures-AndApplications-Andre-Neubauer-Et-Al-2007
2. http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/adc.html

20

P2VLC12 EMBEDDED SYSTEMS AND ADVANCED VLSI CIRCUIT LAB

LTPC
2
AIM

0 0 2

To make the students to work on different tools and to develop applications on embedded
Micro controller.
OBJECTIVES
At the end of this lab session student will understand
Working on Xilinx
Working on Tanner EDA
Working on PIC controller
List of Experiments
1. Implementation of Elevator controller using PIC controller.
2.
Implementation of Alarm clock controller using PIC micro controller.
3.
Implementation of temperature sensor using PIC controller
4. Timing simulation of any sequential circuit with and without changing the user
constraints.
5. Power measurement, timing analysis for any one adder and multiplier
6. Perform Built in Self Test (BIST) for a design.
BEYOND THE SYLLABUS
1. Design and Implementation of CORDIC algorithm using FPGA
2. Design of 8 bit sliced processor

21

PEVLC15 VLSI SYSTEM DESIGN

C

ELECTIVE I

L T P

3 0
03
AIM
To introduces various subsystems of a system design, their control logic, verification and
testing.
OBJECTIVES
To impart knowledge on
CMOS subsystem deign
Different types of memory structure
Basic of system Verilog
UNIT I CMOS SUBSYSTEM DESIGN

Introduction Data path operations Parity generator Comparators Zero/one detectorsBinary counters Boolean operations Multiplication Shifters.
UNIT II MEMORY ELEMENTS

Read/write memory: - RAM- Register files FIFOs, LIFOs, SIPOs- Serial Access memory. Read
only memory Content Addressable memory - Finite State Machine FSM Design
procedure Control Logic implementation :- PLA Control implementation ROM Control
implementation Multilevel logic An example of control logic implementation.
UNIT III INTRODUCTION TO SYSTEM VERILOG

System Verilog origins, System Verilog standards, enhancement for hardware design,
advantages of system Verilog.
UNIT IV LITERAL VALUES AND DATA TYPES

Enhanced literal value assignments, external compilation unit declarations, simulation time
units and precision, system Verilog data types, type casting.
UNIT V SYSTEM VERILOG ARRAYS, STRUCTURES AND UNIONS

Assigning values to structures, packed and unpacked structures, arrays, structures and
unions,
Basic programming in System Verilog
BEYOND THE SYLLABUS
1. CMOS chip design options
2. CMOS subsystem design-data path operations

TOTAL: 45 periods

REFERENCES:
1. N.H.E.Weste and K.Eshraghian, Principles of CMOS VLSI Design, 2 nd Edition - Addition
Wesley,1993.
2. Jan .M.Rabaey, Digital Integrated Circuits a design perspective , PHI 1 st Editi
3. System Verilog For Design a Guide By system verilog for hardware modeling by staurt
southerland,Simon Davidman,Peter Flake, Kluwer Academic Publishers,2004
URLs
22

http://www.kitece.com/wp-content/uploads/2011/09/CMOS-VLSI-Part-B1.pdf
http://web.ewu.edu/groups/technology/Claudio/ee430/Lectures/L1-print.pdf
PEVLC16 SOLID STATE DEVICE MODELING AND SIMULATION

LTPC
3003

AIM
To introduce a basic knowledge of semiconductor physics, transistor modeling, opto
electronic device modeling and device parameter measurement.
OBJECTIVES
To impart knowledge on
Semiconductor physics, unipolar and bipolar device modeling
UNIT I BASIC SEMICONDUCTOR PHYSICS

Quantum Mechanical Concepts, Carrier Concentration, Transport Equation Band-gap, Mobility

and Resistivity, Carrier Generation and Recombination, Avalanche Process, Noise Sources.
UNIT II BIPOLAR DEVICE MODELING

Injection and Transport Model, Continuity Equation, Diode Small Signal and Large Signal
(Change Control Model), Transistor Models: Ebber Molls Model and Gummel Port Model,
Mextram model, SPICE modeling temperature and area effects.
UNIT III MOSFET MODELING

Introduction Interior Layer, MOS Transistor Current, Threshold Voltage, Temperature Short
Channel and Narrow Width Effect, Models for Enhancement, Depletion Type MOSFET, CMOS
Models in SPICE and study of Tanner tool.
UNIT IV PARAMETER MEASUREMENT

General Methods, Specific Bipolar Measurement, Depletion Capacitance, Series Resistances,

Early Effect, Gummel Plots, MOSFET: Long and Short Channel Parameters, Statistical
Modeling of Biopolar and MOS Transistors.
UNIT V OPTOELECTRONIC DEVICE MODELING

Static and Dynamic Models, Rate Equations, Numerical Technique, Equivalent Circuits,
Modeling of LEDs, Laser Diode and Photo detectors,
TOTAL: 45 Periods
BEYOND THE SYLLABUS
MOSFET CS small signal amplifier, modeling of body effect, MOS FET internal capacitance
and high frequency model
REFERENCES
1. Philip E. Allen, Douglas R.Hoberg, CMOS Analog Circuit Design Second Edition,
Oxford Press - 2002.
2. Kiat Seng Yeo, Samir S.Rofail, Wang-Ling Gob, CMOS / BiCMOS ULSI - Low Voltage,
low Power, Person education, Low price edition, 2003.
3. S.M.Sze Semiconductor Devices - Physics and Technology, John Wiley and sons,
1985.
4. Giuseppe Massobrio and Paolo Antogentti, Semiconductor Device Modeling with
SPICE Second Edition, McGraw-Hill Inc, New York, 1993.
URLs:
1. http://www.electronics-tutorials.ws/diode/diode_1.html
23

2. http://ecee.colorado.edu/~bart/book/book/chapter4/ch4_6.htm
PEVLC17 EMBEDDED SYSTEM DESIGN

LTPC
30 0

AIM
To give exposure to embedded architecture, study of embedded processors, networks of
embedded systems and real time characteristics of embedded systems.
OBJECTIVE
To impart knowledge on
Embedded computers architecture
BUS structure organization of different processors
UNIT I EMBEDDED ARCHITECTURE

Embedded Computers, Characteristics of Embedded Computing Applications, Challenges in

Embedded Computing system design, embedded system design process- Requirements,
Specification, Architectural Design, Designing Hardware and Software Components, System
Integration, Formalism for System -Design- Structural Description, Behavioral Description,
and Design Example: Model Train Controller
UNIT II EMBEDDED PROCESSOR AND COMPUTING PLATFORM

ARM processor- processor and memory organization, Data operations, Flow of Control,
SHARC processor- Memory organization, Data operations, Flow of Control, parallelism with
instructions, CPU Bus configuration, ARM Bus, SHARC Bus, Memory devices, Input/output
devices, Component interfacing, designing with microprocessor development and
debugging, Design Example : Alarm Clock.
UNIT III SYSTEM DESIGN TECHNIQUES

Design Methodologies, Requirement Analysis, Specification, System Analysis and

Architecture Design, Quality Assurance, Design Example: Telephone PBX- System
Architecture, Ink jet printer- Hardware Design and Software Design, Personal Digital
Assistants, Set-top Boxes.
UNIT IV PIC MICRO-CONTROLLER AND INTERFACING

Introduction, CPU architecture, registers, instruction sets addressing modes loop timing,
timers interrupts, interrupts, timing I/o expansion, I 2 C bus operation serial EPROM, analog
to digital converter, UART-Baud Rate-Data Handling-initialization, special features- serial
programming parallel slave port.
UNIT V EMBEDDED MICROCOMPUTER SYSTEMS

Motorola MC68H11 family architecture registers, addressing modes programs, interfacing

methods parallel i/o interface, parallel port interface, memory interfacing. High speed i/o
interfacing, interrupts interrupt service routine-features of interrupts interrupt vector and
priority, timing generation and measurements, input capture, output compare, frequency
measurement, serial i/o devices Rs232, Rs485-Analog interfacing, applications.
TOTAL: 45 periods

24

BEYOND THE SYLLABUS

Microprocessor interfacing-I/O addressing, memory mapped I/O and standard I/O
REFERENCES
1. Wayne Wolf, Computers as Components: Principles of Embedded Computing System
Design, Morgan Kaufman Publishers, 2001
2. John B Peat man, Design with micro-controller, Pearson education Asia, 1998.
3. Jonarthan W Valvano Brooks/code, Embedded micro computer systems, Real time
interfacing, Thomson learning 2001.
4. Frank Vahid and Tony Givargi, Embedded System Design: A Unified
Hardware/Software Introduction,s, John Wiley & Sons, 2000.
5. PIC microcontroller: an introduction to software and hardware interfacing By Han-Way
Huang
URLs:
1. http://www.unrobotica.com/public/libro8.pdf

25

PEVLC18 DSP PROCESSOR ARCHITECTURE AND PROGRAMMING

PC

LT
300

AIM:
To learn about programmable DSPs and architecture
OBJECTIVES
To impart knowledge on
VLIW architecture
Typical study about C5X/C3X processors,
ADSP processors and some advanced DSPs useful for real time applications.
UNIT I FUNDAMENTALS OF PROGRAMMABLE DSPS

Multiplier and Multiplier accumulator Modified Bus Structures and Memory access in P-DSPs
Multiple access memory Multi-port memory VLIW architecture- Pipelining Special
Addressing modes in P-DSPs On chip Peripherals.
UNIT II TMS320C5X PROCESSOR

Architecture Assembly language syntax - Addressing modes Assembly language

Instructions - Pipeline structure, Operation Block Diagram of DSP starter kit Application
Programs for processing real time signals.
UNIT III TMS320C3X PROCESSOR

Architecture Data formats - Addressing modes Groups of addressing modes- Instruction

sets - Operation Block Diagram of DSP starter kit Application Programs for processing real
time signals Generating and finding the sum of series, Convolution of two sequences, Filter
design
UNIT IV ADSP PROCESSORS

Architecture of ADSP-21XX and ADSP-210XX series of DSP processors- Addressing modes

and assembly language instructions Application programs Filter design, FFT calculation.
UNIT V

ADVANCED PROCESSORS

Architecture of TMS320C54X: Pipe line operation, Code Composer studio - Architecture of

TMS320C6X - Architecture of Motorola DSP563XX Comparison of the features of DSP family
processors.
TOTAL: 45 PERIODS
BEYOND THE SYLLABUS
Face reorganization using SIMD, Implementation of speech reorganization, Harmony
processor,
REFERENCES
1. B.Venkataramani and M.Bhaskar, Digital Signal Processors Architecture,
Programming and Applications Tata McGraw Hill Publishing Company Limited.
New Delhi, 2003.
2. User guides Texas Instrumentation, Analog Devices, Motorola.
26

URLs:
1. http://www.datasheetarchive.com/TMS320C5x+TUTORIALS-datasheet.html
2. https://www.dropbox.com/s/7w8uqju3f3jqqtv/DSP-Processor.pdf
PEVLC19 FPGA BASED SIGNAL PROCESSING
LTPC
3003
AIM
To enable the students to learn the efiiceint hardware architectures for various signal
processing applications.
OBJECTIVES
To impart knowledge on
Speech coding and standards
Multirate signal processing
UNIT I MULTIRATE SIGNAL PROCESSING
9
Decimation and Interpolation, Spectrum of decimated and interpolated signals, Polyphase
decomposition of FIR filters and its applications to multi-rate DSP, Sampling rate converters
Sub-band encoder
UNIT II FILTER BANKS
9
Uniform filter bank. Direct and DFT approaches. Introduction to ADSL Modem, Discrete multitone modulation and its realization using DFT. QMF, Computation of DWT using filter banks
UNIT III DDFS
9
ROM LUT approach, Spurious signals jitter. Computation of special functions using CORDIC,
Vector and rotation mode of CORDIC, CORDIC architectures
UNIT IV BLOCK DIAGRAM OF A SOFTWARE RADIO
9
Digital down converters and demodulators Universal modulator and demodulator using
CORDIC, Incoherent demodulation - digital approach for I and Q generation, special sampling
schemes. CIC filters. Residue number system and high speed filters using RNS. Down
conversion using discrete Hilbert transform. Under sampling receivers, Coherent
demodulation schemes
UNIT V SPEECH CODING AND STANDARDS
9
Models of vocal tract, Speech coding using linear prediction, CELP coder, an overview of
waveform coding, Vocoders, Vocoder attributes. Block diagrams of encoders and decoders of
G723.1, G726, G727, G728 and G729.
TOTAL: 45 periods
BEYOND THE SYLLABUS
1. DSP system definitions
2. DSP transforms
3. Different filter structures
REFERENCES
1. Meyer.U., Baese, Digital Signal Processing with FPGAs, Springer, 2001.
2. Reed. J H., Software Radio, Pearson, 2002.
3. Mitra.S.K., Digital Signal processing, McGrawHill, 1998.
4. Keshab K.Parhi, VLSI Digital Signal Processing systems, Design and implementation,
Wiley, Inter Science, 1999
URLs:
1. www.cadence.com/rl/resources/white_papers/fpga_wp.pdf
2. http://www.eee.hku.hk/~work3220/Speech%20coding%20-%20standards.pdf

27

ELECTIVE II
PEVLC20 COMPUTER AIDED DESIGN FOR VLSI
LTPC

3003
AIM
To make the students to understand the physical design of a chip
OBJECTIVES
To impart knowledge on
Different floor planning method
Different routing algorithms
UNIT I BASIC ALGORITHMS AND DATA STRUCTURES
9
Data Structures and Basic Algorithms Algorithmic Graph Theory and Computational
complexity Tractable and Intractable problems - General Purpose Methods for
Combinational Optimization.
UNIT II PARTITIONING FLOOR PLANNING PLACEMENT & ROUTING ALGORITHMS
9
Partitioning problem formulation classification of partitioning algorithms group
migration algorithms simulated annealing and evolution performance driven
partitioning - floor planning and pin assignment problem formulation classification of
floor planning algorithms classification of pin assignment algorithms placement
problem formulation classification of placement algorithms simulation based placement
partitioning based placement performance driven placement routing global routing
problem formulation classification of global routing algorithms detailed routing
problem formulation classification of detailed routing algorithms.
UNIT III SIMULATION, LOGIC SYNTHESIS & VERIFICATION
9
Simulation Different levels of simulation - Logic synthesis & Verification basic issues in
combinational logic synthesis binary decision diagrams - ROBDD principles
implementation and construction manipulation variable ordering applications to
verification and combinatorial optimization.
UNIT IV HIGH LEVEL SYNTHESIS & COMPACTION
9
Hardware models for high level synthesis internal representation of the input algorithm
allocation, assignment and scheduling - Compaction problem formulation classification
of compaction algorithms one dimensional compaction one and a half dimensional
compaction two dimensional compaction hierarchical compaction recent trends in
compaction.
UNIT V PHYSICAL DESIGN AUTOMATION OF FPGAS & MCMS
9
Physical Design Automation of FPGAs FPGA technologies physical design cycle for
FPGAs partitioning routing - Physical design automation of MCMS MCM technologies
MCM Physical design cycle partitioning placement routing -VHDL - Verilog implementation of simple circuits using VHDL and Verilog.
TOTAL: 45 periods
BEYOND SYSLLABUS
1. Imperative Programming
2. Declarative Programming
REFERENCES
1.N.A.Sherwani, Algorithms for VLSI Physical Design Automation, 3 rd Edition, Kluwer
Academic, 1999.
28

2. S.H.Gerez, Algorithms for VLSI Design Automation, John Wiley, 1998.

URLs:
1. http://nptel.iitm.ac.in/courses/IIT-MADRAS/CAD_for_VLSI_Design_I/index.php
2. http://www.ece.gatech.edu/research/yohdl/Courses/ECE4894/lec/intro.pdf
PEVLC21 PHYSICAL DESIGN OF VLSI CIRCUITS

LTPC
3003

AIM
To study about different techniques for placement and routing in physical design of VLSI
circuits.
OBJECTIVE
To learn about performance issues in circuit layout, cell generation and compaction.
UNIT I INTRODUCTION TO VLSI TECHNOLOGY
9
Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor
chaining, Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea
of gates, field programmable gate array(FPGA)-layout methodologies-PackagingComputational Complexity-Algorithmic Paradigms
UNIT II PLACEMENT USING TOP-DOWN APPROACH
9
Partitioning: Approximation of Hyper Graphs with Graphs, Kernighan-Lin Heuristic- Ratio cutpartition with capacity and i/o constraints. Floor planning: Rectangular dual floor planninghierarchical approach- simulated annealing- Floor plan sizing- Placement: Cost functionforce directed method- placement by simulated annealing- partitioning placement- module
placement on a resistive network regular placement- linear placement.
UNIT III ROUTING USING TOP DOWN APPROACH
9
Fundamentals: Maze Running- line searching- Steiner trees Global Routing: Sequential
Approaches- hierarchical approaches- multi commodity flow based techniques- Randomized
Routing- One Step approach- Integer Linear Programming Detailed Routing: Channel
Routing- Switch box routing. Routing in FPGA: Array based FPGA- Row based FPGAs
UNIT IV PERFORMANCE ISSUES IN CIRCUIT LAYOUT
9
Delay Models: Gate Delay Models- Models for interconnected Delay- Delay in RC trees.
Timing Driven Placement: Zero Stack Algorithm- Weight based placement- Linear
Programming Approach Timing Driving Routing: Delay Minimization- Click Skew ProblemBuffered Clock Trees. Minimization: constrained via Minimization- unconstrained via
Minimization- Other issues in minimization
UNIT V SINGLE LAYER ROUTING, CELL GENERATION AND COMPACTION 9
Planar subset problem (PSP) - Single layer global routing- Single Layer Global Routing- Single
Layer Detailed Routing- Wire length and bend minimization technique Over The Cell (OTC)
Routing- Multiple chip modules(MCM)- Programmable Logic Arrays- Transistor chaining- Wein
Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction
TOTAL: 45 periods
BEYOND SYSLLABUS
1. River routing
2. Left Edge channel routing algorithm
REFERENCES
1. Sarafzadeh, C.K. Wong, An Introduction to VLSI Physical Design, Mc Graw Hill
International Edition 1995
2. Naveed A. Sherwani Algorithm for VLSI Physical Design Automation, 3rd Edition ,
Springer, 1998.

29

3. Sadiq M. Sait, Habib Youssef VLSI Physical Design Automation, Theory and Practice
World Scientific Publishing Company, 1st Edition,1999.
URLs:
1. http://www.ifte.de/mitarbeiter/lienig/eabook.pdf
2. http://www.eecs.berkeley.edu/~newton/presentations/Arpa10_89/tsld008.htm
PEVLC22 HIGH SPEED SWITCHING ARCHITECTURE
AIM
To study about different High speed switching circuits

LTPC
3003

OBJECTIVE
To impart knowledge on
Different switching technologies
Different architectures
Ques architecture
UNIT I LAN SWITCHING TECHNOLOGY
9
Switching Concepts, switch forwarding techniques, switch path control, LAN Switching, cut
through forwarding, store and forward, virtual LANs.
UNIT II ATM SWITCHING ARCHITECTURE
9
Blocking networks - basic - and- enhanced banyan networks, sorting networks - merge
sorting, re-arrangable networks - full-and- partial connection networks, non blocking
networks - Recursive network construction, comparison of non-blocking network, Switching
with deflection routing - shuffle switch, tandem banyan switch.
UNIT III QUEUES IN ATM SWITCHES
9
Internal Queueing -Input, output and shared queueing, multiple queueing networks
combined Input, output and shared queueing - performance analysis of Queued switches.
UNIT IV PACKET SWITCHING ARCHITECTURES
9
Architectures of Internet Switches and Routers- Bufferless and buffered Crossbar switches,
Multi-stage switching, Optical Packet switching; Internally buffered Crossbars.
UNIT V IP SWITCHING
9
Addressing model, IP Switching types - flow driven and topology driven solutions, IP over
ATM address and next hop resolution, multicasting
Total: 45
Periods
BEYOND THE SYLLABUS
1. Switching fabric on a chip
2. IPv6 over ATM.
REFERENCES
1. Achille Pattavina, Switching Theory: Architectures and performance in Broadband ATM
networks ", John Wiley & Sons Ltd, New York. 1998
2. Elhanany M. Hamdi, High Performance Packet Switching architectures, Springer
Publications, 2007.
3. Christopher Y Metz, Switching protocols & Architectures, McGraw Hill Professional
Publishing, NewYork.1998.
4. Rainer Handel, Manfred N Huber, Stefan Schroder, ATM Networks - Concepts Protocols,
Applications, 3rd Edition, Addison Wesley, New York. 1999.

30

URLs:
1. http://www.niceindia.com/qbank/dc1621_high_speed_switching_architecture.pdf
2. http://k-12.pisd.edu/currinst/network/06_805A_2-1_SG.pdf

31

PEVLC23 DESIGN OF VLSI IN EMBEDDED SYSTEM

3003

LTPC

AIM
To study the importance of VLSI in embedded systems.
OBJECTIVES
To learn about custom single processor, multiprocessor and different communications
required in the design of embedded systems
UNIT I INTRODUCTION

Embedded system overview,Design challenge: Optimizing design metrics,

Processor Technology,
Generalpurpose Processors, Singlepurpose Processors, and Application Specific Processors, I
C
Technology: Full custom/VLSI, Semicustom ASIC, PLD, Trends, Design Technology.
UNIT II CUSTOM SINGLE

PURPOSE

PROCESSOR

RT level combinational components, RT level sequential components , Custom Single

purpose Processor Design, RTlevel Custom Single purpose Processor Design, Optimizing Custom Single
purpose Processors , Optimizing
the original program, Optimizing the FSMD,Optimizing the datapath, optimizing the FSM.
Generalpurpose Processors
Basic architecture, Data path, Control unit, Memory, Pipelining, Superscalar and VLIW
architectures, Application Specific instruction set Processors (ASIPs), Microcontrollers,
DSP, Less
General ASIP environments, selecting a Microprocessor/ General purpose Processor Design.
UNIT III ADVANCED COMMUNICATION PRINCIPLES

Parallel, serial and wireless Communications, Serial protocols: The I2C

Bus, The CAN bus, Fire wire bus, USB. Parallel protocols: PCI bus, AMBA bus, wireless
protocols: IrDA, Bluetooth, IEEE 802.11.
UNIT IV DIGITAL CAMERA EXAMPLE

Users perspective, Designer perspective, Specification, Informal functional specification,

Nonfunctional specification .Executable specification, Design, Implementation 1:8051based
design, Implementation 2: Fixed point FDCT, Implementation 3: Hardware FDCT.
UNIT V EMBEDDED SOFTWARE DESIGN

Embedded software design, hardware and software interaction, mixed

architecture/application models, heterogeneous MPSOC, Virtual architecture model, virtual
architecture in systemC, application examples in virtual architecture.
TOTAL: 45 periods
REFERENCES
1. Embedded System DesignA Unified Hardware/Software I ntroduction,Frank Vahid and Tony Givargis,John Wiley & Sons
,2002.
2. Embedded Software design and programming of multiprocessor system on chip, katalin
popovici, ahmed jeerya,Marilyn wolf,Springer publications,2010.
32

3. Embedded System Design Steve Heath,ButterworthHeinemann.

4. Specification and Design of Embedded systems, Gajski and Vahid,Prentice Hall.
PEVLC24 ADVANCED MICROPROCESSORS AND MICROCONTROLLERS
C

LTP
3 003

AIM
To study about the advanced processors in the VLSI industry
OBJECTIVE
To impart knowledge on
Pentium Processors architectures
ARM Processors architectures
Advanced micro controller architectures.
UNIT I MICROPROCESSOR ARCHITECTURE
9
Instruction Set Data formats Addressing modes Memory hierarchy register file Cache
Virtual memory and paging Segmentation- pipelining the instruction pipeline pipeline
hazards instruction level parallelism reduced instruction set Computer principles RISC
versus CISC.
UNIT II HIGH PERFORMANCE CISC ARCHITECTURE PENTIUM
9
CPU Architecture- Bus Operations Pipelining Brach predication floating point unitOperating Modes Paging Multitasking Exception and Interrupts Instruction set
addressing modes.
UNIT III HIGH PERFORMANCE RISC ARCHITECTURE ARM
9
Organization of CPU Bus architecture Memory management unit - ARM instruction setThumb Instruction set- addressing modes Programming the ARM processor.
UNIT IV MOTOROLA 68HC11 MICROCONTROLLERS
9
Instruction set addressing modes operating modes- Interrupt system- RTC-Serial
Communication Interface
UNIT V PIC MICROCONTROLLER
9
CPU Architecture Instruction set interrupts- Timers- I2C Interfacing UART- A/D Converter
PWM and introduction to C-Compilers.
Total: 45 Periods
BEYOND THE SYLLABUS
1. Programming the Pentium processor
2. A/D Converter PWM and UART
REFERENCES:
1. Daniel Tabak , Advanced Microprocessors McGraw Hill.Inc., 1995
2. James L. Antonakos , The Pentium Microprocessor Pearson Education , 1997.
3. Steve Furber , ARM System On Chip architecture Addision Wesley , 2000.
4. Gene .H.Miller . Micro Computer Engineering , Pearson Education , 2003.
5. John .B.Peatman , Design with PIC Microcontroller , Prentice hall, 1997.
6. James L.Antonakos , An Introduction to the Intel family of Microprocessors Pearson
Education 1999.
7. Barry.B.Breg, The Intel Microprocessors Architecture , Programming and
Interfacing , PHI,2002.
URLs:
1. http://www.cse.ohio-state.edu/~panda/775/slides/intel_power_perf_06.pdf
2. http://homepages.thm.de/~hg10013/Lehre/MMS/WS0304_SS04/Ioannis/PDF/arm.pdf

33

ELECTIVE III
PEVLC25 HARDWARE / SOFTWARE CO-DESIGN

LT PC
3 0

0 3
AIM
To make the student to understand the Hardware / Software Co-Design

OBJECTIVE
To impart knowledge on
Prototyping of S/W &H/W
Hardware/Software Partitioning
Hardware/Software co synthesis
UNIT I
SYSTEM SPECIFICATION AND MODELLING
9
Embedded Systems , Hardware/Software Co-Design , Co-Design for
System Specification and Modelling , Co-Design for System Specification
and Modelling , Co-Design for Heterogeneous Implementation - Processor
Synthesis , Single-Processor Architectures with one ASIC , Single-Processor
Architectures with many ASICs, Multi-Processor Architectures , Comparison
of Co-Design Approaches , Models of Computation ,Requirements for
Embedded System Specification .
UNIT II
HARDWARE/SOFTWARE PARTITIONING
9
The Hardware/Software Partitioning Problem, The Hardware/Software
Partitioning Problem, Hardware/Software Cost Estimation, Generation of
the Partitioning Graph , Formulation of the HW/SW Partitioning Problem ,
Optimization , HW/SW Partitioning based on Heuristic Scheduling, HW/SW
Partitioning based on Genetic Algorithms .
UNIT III
HARDWARE/SOFTWARE CO-SYNTHESIS
9
The Co-Synthesis Problem, State-Transition Graph,
Controller Generation, Distributed System Co-Synthesis

Refinement

and

UNIT IV
PROTOTYPING AND EMULATION
9
Introduction, Prototyping and Emulation Techniques ,Prototyping and
Emulation Environments ,Future Developments in Emulation and
Prototyping ,Target Architecture- Architecture Specialization Techniques
,System Communication Infrastructure, Target Architectures and
Application System Classes, Architectures for Control-Dominated Systems,
Architectures for Data-Dominated Systems ,Mixed Systems and Less
Specialized Systems
UNIT V
DESIGN SPECIFICATION AND VERIFICATION
9
Concurrency,
Coordinating
Concurrent
Computations,
Interfacing
Components, Verification , Languages for System-Level Specification and
Design System-Level Specification ,Design Representation for System
34

Level Synthesis, System Level Specification Languages, Heterogeneous

Specification and Multi-Language Co-simulation
TOTAL: 45
PERIODS

35

BEYOND THE SYLLABUS

Interfacing an external H/W or S/W and RTOS, Rapid proto typing, Co
simulation using HDL
REFERENCES
1.
Ralf Niemann , Hardware/Software Co-Design for Data Flow
Dominated Embedded Systems, Kluwer Academic Pub, 1998.
2.
Jorgen Staunstrup , Wayne Wolf ,Hardware/Software Co-Design:
Principles and Practice , Kluwer Academic Pub,1997.
3.
Giovanni De Micheli , Rolf Ernst Morgon, Reading in
Hardware/Software Co-Design Kaufmann Publishers,2001.
URLs:
1. http://www.cse.uconn.edu/~zshi/course/cse5097/ref/wolf94codesign.pdf
2. http://210.212.205.26/sudarshan/Main/Courses/20122013/OddSem/Hsc_12/lecses/refs/lec01/demicheli97hardwaresoftware.pdf.

36

PEVLC26 NANOTECHNOLOGY
LTPC
3003
AIM
To study about the nano machines and nano devices
OBJECTIVE
To Impart The Knowledge On
Solid state physics
Different Nano devices
UNIT-1 INTRODUCTION TO PHYSICS OF THE SOLID STATE
9
Structure-size dependence of properties-crystal structures-face centered cubic nano
particles-energy bands-insulators, semiconductors and conductors-reciprocal space-energy
bands and gaps of semiconductors-localized particles donors, acceptors and deep trapsmobility
UNIT-2 METHODS OF MEASURING PROPERTIES
9
Structure-atomic structures-crystallography-particle size determination surface structuremicroscopy-transmission electron microscopy-field ion microscopy-scanning microscopyspectroscopy-infrared and raman spectroscopy-photoemission and x ray spectroscopyUNIT -3 PROPERTIES OF INDIVIDUAL NANOPARTICLES
9
Introduction-metal nanoclusters-magic numbers-theoretical modeling of nanoparticalsgeometric structure-electronic structure-reactivity-fluctuations-semiconducting
nanoparticals-optical particals-photofragmentation rare gas and molecular clusters-inert
gas clusters-superfluid clusters-molecular clusters-method of synthesis-RF plasma-chemical
methods-thermolysis-pulsed laser methods
UNIT -4 CARBON NANOSTRUCTURES
9
Carbon molecules-carbon nanotubes-fabrication-structure-electrical properties-vibrational
properties-mechanical properties-application carbon nanotubes-computers-fuel cellschemical sensors-catalysis-mechanical reinforcement
UNIT -5 NANOMECHINES AND NANODEVICES
9
Microelectromechanical systems (MEMSs)-nanoelectromechanical systems(NEMSs)fabrication-nanodevices and nanomechines-molecular and superamolecular switches
Total: 45 Periods
BEYOND SYLLABUS
Nano biometricks, applications of nano technology in solar energy
REFERENCES
1. Poole. C.P. Jr., Owens. F. J., Introduction to Nanotechnology, Wiley, 2003
2. Waser Ranier, Nanoelectronics and Information Technology
(Advanced Electronic Materials and Novel Devices), Wiley-VCH 2003
3. Drexler. K.E., Nanosystems, Wiley 1992.
URLs:
1. http://snf.stanford.edu/Education/Nanotechnology.SNF.web.pdf
2. http://www.nanotec.org.uk/finalReport.htm

37

PEVLC27 INTRODUCTION TO MEMS SYSTEM DESIGN

LTPC
3 0 03
AIM
To give introduction to micro electro mechanical details
OBJECTIVE
To impart knowledge on
Introduction To MEMS
Mechanism for MEMs Design
UNIT I
INTRODUCTION TO MEMS
9
MEMS and Microsystems, Miniaturization, Typical products,
Micro sensors, Micro
actuation, MEMS with micro actuators, Microaccelorometers and Micro fluidics, MEMS
materials, Micro fabrication
UNIT II
MECHANICS FOR MEMS DESIGN
9
Elasticity, Stress, strain and material properties, Bending of thin plates,
Spring
configurations, torsional deflection, Mechanical vibration, Resonance, Thermo mechanics
actuators, force and response time, Fracture and thin film mechanics.
UNIT III ELECTRO STATIC DESIGN
9
Electrostatics: basic theory, electro static instability. Surface tension, gap and finger pull
up, Electro static actuators, Comb generators, gap closers, rotary motors, inch worms,
Electromagnetic actuators. bistable actuators.
UNIT IV CIRCUIT AND SYSTEM ISSUES
9
Electronic Interfaces, Feedback systems, Noise, Circuit and system issues, Case studies
Capacitive accelerometer, Peizo electric pressure sensor, Modeling of MEMS systems,
CAD for MEMS.
UNIT V
INTRODUCTION TO OPTICAL AND RF MEMS
9
Optical MEMS, - System design basics Gaussian optics, matrix operations, resolution.,
Case studies, MEMS scanners and retinal scanning display, Digital Micro mirror devices.
RF Memes design basics, case study Capacitive RF MEMS switch, performance issues.
TOTAL: 45 PERIODS
BEYOND SYLLABUS
Materials for MEMs, Fabrication process of Micro systems, Micro systems
packaging..
REFERENCES
1. Stephen Santuria, Microsystems Design, Kluwer publishers, 2000
2. .Nadim Maluf, An introduction to Micro electro mechanical system design, Artech
House, 2000
3. 2. Mohamed Gad-el-Hak, editor, The MEMS Handbook, CRC press Baco Raton, 2000.
4. 3. Tai Ran Hsu, MEMS & Micro systems Design and Manufacture Tata McGraw Hill,
New Delhi, 2002.
URLs:
1. http://www.coventor.com/products/mems/
2. http://www.intellisense.com/upload/0/20120529031051.pdf

38

PEVLC28 WIRELESS SENSOR NETWORKS

C
AIM
To give introduction to the wireless sensor networks
OBJECTIVE
To impart knowledge on
Architectures of sensor networks
Networking of sensors
Infra structures

LTP
3 003

UNIT I OVERVIEW OF WIRELESS SENSOR NETWORKS

9
Challenges for Wireless Sensor Networks-Characteristics requirements-required
mechanisms, Difference between mobile ad-hoc and sensor networks, Applications of sensor
networks- Enabling Technologies for Wireless Sensor Networks.
UNIT II ARCHITECTURES
9
Single-Node Architecture - Hardware Components, Energy Consumption of Sensor Nodes ,
Operating Systems and Execution Environments, Network Architecture - Sensor Network
Scenarios, Optimization Goals and Figures of Merit,.
UNIT III NETWORKING OF SENSORS
9
Physical Layer and Transceiver Design Considerations, MAC Protocols for Wireless Sensor
Networks, Low Duty Cycle Protocols And Wakeup Concepts - S-MAC , The Mediation Device
Protocol, Wakeup Radio Concepts, Address and Name Management, Assignment of MAC
Addresses, Routing Protocols
UNIT IV INFRASTRUCTURE ESTABLISHMENT
9
Topology Control, Clustering, Time Synchronization, Localization and Positioning, Sensor
Tasking and Control.
UNIT V SENSOR NETWORK PLATFORMS AND TOOLS
9
Operating Systems for Wireless Sensor Networks, Sensor Node Hardware Berkeley Motes,
Programming Challenges, Node-level software platforms, Node-level Simulators, Statecentric programming.
Total: 45 Periods
BEYOND THE SYLLABUS
1. Gateway Concepts
2. Energy-Efficient Routing
3. Geographic Routing
REFERENCES
1. Holger Karl & Andreas Willig, " Protocols And Architectures for Wireless Sensor Networks" ,
John Wiley, 2005.
2. Feng Zhao & Leonidas J. Guibas, Wireless Sensor Networks- An Information Processing
Approach", Elsevier, 2007.
3. Kazem Sohraby, Daniel Minoli, & Taieb Znati, Wireless Sensor NetworksTechnology, Protocols, And Applications, John Wiley, 2007.
4. Anna Hac, Wireless Sensor Network Designs, John Wiley, 2003.
5. Bhaskar Krishnamachari, Networking Wireless Sensors, Cambridge Press,2005.
6. Mohammad Ilyas And Imad Mahgaob,Handbook Of Sensor Networks: Compact Wireless
And Wired Sensing Systems, CRC Press,2005.
7. Wayne Tomasi, Introduction To Data Communication And Networking, Pearson
Education, 2007
URLs:
1. http://arri.uta.edu/acs/networks/WirelessSensorNetChap04.pdf
2. http://www.sensor-networks.org/
39

PEVLC29CONTROL SYSTEM ON CHIP

LTPC
3003

AIM
To learn the modern IC based design for any control applications
OBJECTIVES
To impart knowledge on
control components
SOC design of fuzzy logic controller
UNIT I

Introduction to control system concept-open loop and closed loop-control system

architecture-types of control methodology-digital control system-analysis of digital control
system-remote control concepts and applications
UNIT II

control components and detailed study-op amp transmitter- receivers- standard cell array
design-Gate array design-full custom design-structured design-IP base design
UNIT III

Study of CC2533 of Texas Instruments for Chip solution to remote control applications
UNIT IV

System on Chip design of a Fuzzy logic controller

UNIT V

Single chip design of a temperature controller, Single chip design of Engine control system
TOTAL: 45 periods
BEYOND THE SYLLABUS
System on chip test architectures, Reliability issues, High Speed I/O interface.
REFERENCES
1. Microcontroller based Applied digital control by Dogan Ibrahim, John
Wiley,2006
2. An optimized system on chip solution for 2.4GHz IEEE 802.15.4 remote control
application, Texas instrument, June 2010 and application notes
URLs:
1. www.isoi.in/Journal/BackIssues/vol38
2. www.fujitsu-ten.com/business/technica

40

ELECTIVE IV
PEVLC30 LOW POWER VLSI DESIGN

LTPC
3003

AIM
To learn about power dissipation in CMOS circuits, different power optimization techniques
OBJECTIVES
To Impart Knowledge On
CMOS circuits for memory clock and interconnect.
various techniques for Power estimation in circuits
UNIT I POWER DISSIPATION IN CMOS

Hierarchy of limits of power Sources of power consumption Physics of power dissipation

in CMOS FET devices- Basic principle of low power design.
UNIT II

POWER OPTIMIZATION

Logical level power optimization Circuit level low power design Circuit techniques for
reducing power consumption in adders and multipliers
UNIT III DESIGN OF LOW POWER CMOS CIRCUITS

Computer Arithmetic techniques for low power systems Reducing power consumption in
memories Low power clock, Interconnect and layout design Advanced techniques
Special techniques
UNIT IV POWER ESTIMATION

Power estimation techniques Logic level power estimation Simulation power analysis
Probabilistic power analysis.
UNIT V

SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER

Synthesis for low power Behavioral level transforms- Software design for low power TOTAL: 45 periods
BEYOND THE SYLLUBUS
Low voltage-low power adder, multipliers,
REFERENCES
1.
2.

K.Roy and S.C. Prasad , LOW POWER CMOS VLSI circuit design, Wiley,2000
Dimitrios Soudris, Chirstian Pignet, Costas Goutis, Designing CMOS Circuits For Low
Power, Kluwer,2002
3. J.B. Kuo and J.H Lou, Low voltage CMOS VLSI Circuits,Wiley 1999.
4. A.P.Chandrakasan and R.W. Broadersen, Low power digital CMOS design, Kluwer, 1995.
5. Gary Yeap, Practical low power digital VLSI design, Kluwer, 1998.
6. Abdellatif Bellaouar,Mohamed.I. Elmasry, Low power digital VLSI design,s Kluwer, 1995.
7. James B. Kuo, Shin chia Lin, Low voltage SOI CMOS VLSI Devices and Circuits. John
Wiley and sons, inc 2001
URLs:
1. www.cpdee.ufmg.br/~frank/lectures/Sill-LowPower2.ppt
2. http://www.cmosvlsi.com/lect18.pdf
41

PEVLC31 SEMICONDUCTOR MEMORY DESIGN & PROCESSING

C

LTP
3003

AIM
To study about basic semiconductor memories, their types and the faults in memories.
OBJECTIVES
Testing and packaging techniques of different memory types
UNIT I
RANDOM ACCESS MEMORIES
9
SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit
Operation-Bipolar SRAM Technologies-Silicon On Insulator (SOl) Technology-Advanced SRAM
Architectures and Technologies-Application Specific SRAMs.
DYNAMIC RANDOM ACCESS MEMORIES (DRAMS)
DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell
Structures-BiCMOS, DRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and
Architecture-Application Specific DRAMs.
UNIT II

NONVOLATILE MEMORIES
Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only
Memories (PROMs)-Bipolar PROMs-CMOS PROMs-Erasable (UV) - Programmable Road-Only
Memories (EPROMs)-Floating-Gate EPROM Cell-One-Time Programmable (OTP) EPROMSElectrically Erasable PROMs (EEPROMs)-EEPROM Technology And Architecture-Nonvolatile
SRAM-Flash Memories (EPROMs or EEPROM)-Advanced Flash Memory Architecture.
UNIT III
9
MEMORY FAULT MODELING, TESTING, AND MEMORY DESIGN FOR TESTABILITY AND
FAULT TOLERANCE
RAM Fault Modeling, Electrical Testing, Pseudo Random Testing-Megabit DRAM TestingNonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application
Specific Memory Testing
UNIT IV

SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS

General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory ReliabilityReliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test
Structures-Reliability Screening and Qualification, RAM Fault Modeling, Electrical Testing,
Pseudo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and TestingIDDQ Fault Modeling and Testing-Application Specific Memory Testing
UNIT V
9
PACKAGING TECHNOLOGIES
Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation
Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation
Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and
Test Structures. Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs)
FRAMs-Analog Memories-Magnetoresistive Random Access Memories (MRAMs)-Experimental
Memory Devices. Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory

42

MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future
Directions.
TOTAL: 45 periods
BEYOND THE SYLLABUS
CMOS memory circuits, Yield improvement techniques,
REFERENCES
1. Ashok K. Sharma, Semiconductor Memories: Technology, Testing, and Reliability, WileyIEEE Press, 2002.
2. Ashok K. Sharma , Semiconductor Memories, Two-Volume Set, Wiley-IEEE Press, 2003.
3. Ashok K. Sharma, Semiconductor Memories: Technology, Testing, and Reliability, Prentice
Hall of India, 1997.
4. Brent Keeth, R. Jacob Baker, DRAM Circuit Design: A Tutorial, Wiley-IEEE Press, 2000.
5.Betty Prince , High Performance Memories: New Architecture DRAMs and SRAMs Evolution and Function, Wiley, 1999.
URLs:
1. http://highered.mcgraw-hill.com/sites/dl/free/0072283653/109342/hodge_chapt08.pdf
2. http://www.radio-electronics.com/info/data/semicond/memory/different-types-semiconductormemory.php

43

PEVLC32 COMPUTER ARCHITETURE AND PARALLEL PROCESSING

LTPC
3003

AIM
To Study the Advanced Computer Architectures
OBJECTIVE
To impart knowledge on
Network properties of computers
Superscalar techniques
UNIT-1 PARELLEL COMPUTER PROGRAM AND NETWORK PROPERTIES
9
Multiprocessors and multicomputers-multivector and SIMD computers-PRAAM and VLSI
MODELS-architectural development tracks-conditions of parallelism-data and resources
dependences-hardware and software parallelism-grain size and latency-grain packing and
scheduling-static multiprocessor scheduling-program flow mechanisms-system interconnect
architecture-network properties and routing
UNIT-2 PROCESSORS AND MEMORY
9
Advanced processor technology-RISC scalar processors-superscalar and vector processorsmemory hierarchical technology-virtual memory technology-cache memory organizationsshared memory organizations
UNIT-3 PIPELINING AND SUPERSCALAR TECHNIQUES
9
Linear pipeline processors-asynchronous and synchronous models-clocking and timing
control speedup,efficiency,and throughput-nonlinear pipeline processors-reservation and
latency analysisCollison Free Scheduling- Pipeline Schedule Optimization-Instruction Pipeline DesignInstruction Execution Phases- Mechanisms for Instruction Pipelining-Dynamic Instruction
scheduling-Branch Handling Techniques-Arithmetic Pipeline Design Computer Arithmetic
Principles-Static Arithmetic Pipelines-Multifunctional Arithmetic Pipelines-Superscalar and
super pipeline design-Super pipelined Design
UNIT-4 MULTIPROCESSOR AND MULTICOMPUTERS
9
Multiprocessor system interconnects-cache coherence and synchronization mechanismsthree generations of multicomputers-message passing mechanisms-vector processing
principles vector instruction types-compound vector processing SIMD computer
organizations
Unit-5 SCALABLE, MULTI THREADED AND DATAFLOW ARCHITECTURES
9
Latency hiding technique-principles of multithreading-fine grain multicomputers-scalable
and multithreaded architectures
Total 45 periods
BEYOND THE SYLLNUS
Instruction level parallel processing, Memory hierarchi technology, Shared memory MIMD
architectures,
REFERENCE:
1. Dezso Sima, Terence Fountain, Peter Kacsuk, Advanced Computer
architecture A Design Space Approach , Pearson education , 2003.
2. Kai Hwang, Advanced Computer Architecture ", McGraw Hill
International, 1993.

44

3. John P.Shen, Modern processor design - Fundamentals of super scalar

processors, Tata McGraw Hill 2003.
URLs:
1.
http://www.niceindia.com/qbank/AN_1652_COMPUTER_ARCHITECTURE____PARALLEL_PROCE
SSING.pdf
2. http://people.engr.ncsu.edu/efg/506/sum99/001/lec1-intro.pdf
PEVLC33 DATA CONVERTERS

L T P C
3 0 0

AIM
To study the different data converters

OBJECTIVE

To impart the knowledge on

Sample And Hold Circuits
A to D and D to A conversions
UNIT I
BSICS OF DATA CONVERTERS
9
Sampling switches, Conventional open loop and closed loop sample and hold
architecture, Open loop architecture with miller compensation, multiplexed input
architectures, recycling architecture switched capacitor architecture.
UNIT II SWITCH
CAPACITOR
CIRCUITS
AND
COMPARATORS
9
Switched-capacitor amplifiers, switched capacitor integrator, switched capacitor
common mode feedback. Single stage amplifier as comparator, cascaded amplifier
stages as comparator, latched comparators.
UNIT III DIGITAL TO ANALOG CONVERSION
9
Performance metrics, reference multiplication and division, switching and logic
functions in DAC, resistor ladder DAC architecture, current steering, DAC architecture
UNIT IV ANALOG
TO
DIGITAL
9
Performance metric, flash architecture, Pipelined
approximation architecture, Time interleaved architecture.

CONVERSION
Architecture,

Successive

UNIT V PRECISION TECHNIQUES

9
Comparator offset cancellation; Op Amp offset cancellation, Calibration techniques,
range overlap and digital correction.
TOTAL=45
PERIODS
Beyond the syllabus
Nyquist rate D/A converters, A / D converters, Testing of data converters
1.

REFERENCES
Behzad Razavi, Principles of data conversion system design, IEEE press, 1995.
45

2.
Franco Maloberti, Data Converters, Springer, 2007.
3.
Rudy van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog
Converters Kluwer Acedamic Publishers, Boston, 2003.
URLs:
1. http://www-inst.eecs.berkeley.edu/~ee247/fa04/fa04/lectures/L11_f04.pdf
2. http://www.ee.ucla.edu/~brweb/director.html

46

PEVLC34 NETWORK ON CHIP

LTPC
3003

AIM
To give a basic introduction on Network on chip
OBJECTIVES
To impart the knowledge on
Embedded SOC Applications
Testing strategies of NOC
Software for Multiprocessor Networks on Chip
UNIT I
9
Embedded SOC Applications & Platform Elements Networking domain, multimedia domain,
wireless communications, Application trends, First order application partitioning,
Architecture, processing elements, on chip communication.
UNIT II
9
System Level Design Principles Platform based design paradigm, design phases, abstraction
mechanics, models of computation, system level design requirements, tradition HW/SW codesign, and system based transaction based modeling, current research on MPSOC design
methodologies
UNIT III
9
Testing strategies of NOC On packet switched networks for on chip communication, Testing
Strategies for Networks on Chip
UNIT IV
Clocking strategies on chip, parallel computer as NOC region

UNIT V CASE STUDY

9
Software for Multiprocessor Networks on Chip IPV4 format with QOS support, Intel IX2400
reference NPU, OSCI TLM standard,
TOTAL: 45 Periods
BEYOND THE SYLLABUS
Physical Network layer, Data-link layer in NOC design,
Network interface architecture and design issues
REFERENCES
1.Integrated system level modeling of network on chip enabled multi processor platforms ,
Tim Kogel
Visit Amazon's Tim Kogel Page
search results
Learn about Author Central
, Rainer Leupers, Heinrich Meyr , Springer publication.
2.Networks on Chip, Axel Jantsch and Hannu Tenhunen, Kluwer academic publishers,
Newyork.
URLs:
1. http://www.ida.liu.se/~petel/NoC/lecture-notes/lect1part1.pdf
2. http://www.dps.uibk.ac.at/~spellegrini/pub/noc-slides09.pdf

47

48