8 BIT CARRY SELECT ADDER

BLOCK DIAGRAM

PROGRAM CODE
library IEEE;
use ieee.std_logic_1164.all;
entity r_c4 is
port( a,b : in std_logic_vector( 3 downto 0);
c_in : in std_logic;
S : out std_logic_vector( 3 downto 0);
c_out : out std_logic);
end r_c4;
architecture RTL of r_c4 is
begin
process(a,b, c_in)
variable tempC : std_logic_vector( 4 downto 0 );
variable P : std_logic_vector( 3 downto 0 );
variable G : std_logic_vector( 3 downto 0 );
begin
tempC(0) := c_in;
for i in 0 to 3 loop
P(i):=a(i) xor b(i);
G(i):=a(i) and b(i);
S(i)<= P(i) xor tempC(i);
tempC(i+1):=G(i) or (tempC(i) and P(i));
end loop;

c_out <= tempC(4);

end process;
end;

library IEEE;
use ieee.std_logic_1164.all;
entity carry_select4 is
port( x,y : in std_logic_vector( 3 downto 0);
C_input : in std_logic;
Result : out std_logic_vector( 3 downto 0); C_output : out std_logic);
end carry_select4;
architecture RTL of carry_select4 is
component r_c4
port( a,b : in std_logic_vector( 3 downto 0);
c_in : in std_logic;
S : out std_logic_vector( 3 downto 0);
c_out : out std_logic);
end component;
For S0: r_c4 Use entity work.r_c4(RTL);
For S1: r_c4 Use entity work.r_c4(RTL);
signal SUM0, SUM1 : std_logic_vector( 3 downto 0 );
signal carry0, carry1 : std_logic;
signal zero, one : std_logic;
begin
zero<='0';
one<='1';
S0: r_c4 port map( a=>x, b=>y, c_in=>zero, S=>SUM0,
c_out=>carry0 );
S1: r_c4 port map( a=>x, b=>y, c_in=>one, S=>SUM1,
c_out=>carry1 );
Result<=SUM0 when C_input='0' else
SUM1 when C_input='1' else
"ZZZZ";
C_output<= (C_input and carry1) or carry0;
end;

RTL SCHEMATIC

TIMING REPORT
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 2.295ns

Timing Details:
--------------All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 37 / 5
------------------------------------------------------------------------Delay:
2.295ns (Levels of Logic = 5)
Source:
C_input (PAD)
Destination:
Result<3> (PAD)
Data Path: C_input to Result<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
4 0.001 0.525 C_input_IBUF (C_input_IBUF)
LUT3:I0->O
2 0.097 0.688 Mmux_Z_3_o_SUM0[1]_MUX_10_o111
(Mmux_Z_3_o_SUM0[1]_MUX_10_o11)
LUT5:I0->O
1 0.097 0.511 Mmux_Z_3_o_SUM0[3]_MUX_6_o12 (Mmux_Z_3_o_SUM0[3]_MUX_6_o12)
LUT3:I0->O
1 0.097 0.279 Mmux_Z_3_o_SUM0[3]_MUX_6_o11 (Result_3_OBUF)
OBUF:I->O
0.000
Result_3_OBUF (Result<3>)
---------------------------------------Total
2.295ns (0.292ns logic, 2.003ns route)
(12.7% logic, 87.3% route)
=========================================================================

Cross Clock Domains Report:

-------------------------=========================================================================

Total REAL time to Xst completion: 25.00 secs

Total CPU time to Xst completion: 25.28 secs
-->
Total memory usage is 242124 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

DESIGN SUMMARY
Design Summary
*
=========================================================================
Top Level Output File Name

: carry_select4.ngc

Primitive and Black Box Usage:

-----------------------------# BELS
:9
# LUT3
:3
# LUT4
:1
# LUT5
:4
# LUT6
:1
# IO Buffers
: 14
# IBUF
:9
# OBUF
:5

DEVICE UTILIZATION SUMMARY

Selected Device : 7a100tcsg324-3

Slice Logic Utilization:

Number of Slice LUTs:
Number used as Logic:

9 out of 63400 0%
9 out of 63400 0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 9
Number with an unused Flip Flop:
9 out of 9 100%
Number with an unused LUT:
0 out of 9 0%
Number of fully used LUT-FF pairs: 0 out of 9 0%
Number of unique control sets:
0

IO Utilization:
Number of IOs:
Number of bonded IOBs:

14
14 out of 210

Specific Feature Utilization:--------------------------Partition Resource Summary:

--------------------------No Partitions were found in this design.
---------------------------

6%

SIMULATION FOR CARRY SELECT ADDER