EE/JUNE 2012/ECE621/614/KJE521

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UNIVERSITI TEKNOLOGI MARA

FINAL EXAMINATION

COURSE

ADVANCED DIGITAL SYSTEMS/DIGITAL SYSTEM

DESIGN/DIGITAL SYSTEMS III

COURSE CODE

ECE621/614/KJE521

EXAMINATION

JUNE 2012

TIME

3 HOURS

INSTRUCTIONS TO CANDIDATES
1.

This question paper consists of four (4) questions.

2.

Answer ALL questions in the Answer Booklet. Start each answer on a new page.

3.

Do not bring any material into the examination room unless permission is given by the invigilator.

4.

Please check to make sure that this examination pack consists of:
i)
ii)

the Question Paper

an Answer Booklet - provided by the Faculty

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of 5 printed pages
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EE/JUNE 2012/ECE621/614/KJE521

QUESTION 1
a)

Describe briefly the advantages of VHDL over schematic capture method to describe
logic circuits.
(7 marks)

b)

Explain clock skew in digital system and the circumstances under which it can rise. How
a circuit can be minimized against clock skew?
(8 marks)

c)

Explain the differences between the two VHDL code fragments shown in Figure Q1c(i)
and Figure Q1c(ii).

PROCESS
BEGIN
WAIT UNTIL (Clock'EVENT AND Clock=T);
IF reset=T THEN
Q2 <= '0';
ELSE
Q2 <= D;
END IF;
END PROCESS;

PROCESS (Reset, Clock)

BEGIN
IF reset=T THEN
Q3 <= '0';
ELSEIF (Clock'EVENT AND Clock=T) THEN
Q3 <= D;
END IF;
END PROCESS;

Figure Q1c(i)

Figure Q1c(ii)
(10 marks)

QUESTION 2
a)

Minimize the following finite state machine shown in Table Q2a. Show each step of the
minimization process.
Present
State
A
B
C
D
E
F
G
H

Table Q 2a
Next State
Present Output
X=0
X= 1
X=0
X=1
1
H
C
0
D
C
0
1
H
B
0
0
F
H
0
0
0
C
F
1
F
G
0
0
G
1
0
C
A
C
1
0
(15 marks)

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EE/JUNE 2012/ECE621/614/KJE521

architecture FSM of se q design is

type state_type is (SO, SI, S2, S3);
signal next state, current state: st ate_type;
begin
state__reg: process (clock, reset)
begin
if (reset='l') then
current state <= SO;
elsif (clock'event and clock='l') then
current state <= next state;
end if;
end process;
comb logic: process(current state, a
begin
case current state is
when SO => x <= '0';
if a='0' then
next state <=
elsif a ='1' then
next_state <=
end if;
when SI => x <= '0';
if a='0' then
next state <=
elsif a='l' then
next state <=
end if;
when S2 => x <= '0';
if a='0' then
next state <=
elsif a='l' then
next_state <=
end if;
when S3 => x <= ' 1';
if a='0' then
next state <=
elsif a='l' then
next state <=
end if;
when others >
x <= ' 0' ;
next_state <= SO;
end case;
end process;
end FSM;

SCSI;

SI;
S2;

S2;
S3;

S3;
SO;

Figure Q2b

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b)

EE/JUNE 2012/ECE621/614/KJE521

Figure Q2b shows architecture of a VHDL behavioral code.

i)
ii)

Draw the finite state machine diagram describing the VHDL code
Draw the possible schematic for the FSM implementation
(10 marks)

QUESTION 3
a)

A Mealy sequential machine has the state table shown in Table Q3a:
Table Q3a
Present
State (PS)
SO
S1
S2
S3

i)

Next State (NS)

X=0
X=1
S1
so
SO
S2
S3
S2
SO
S1

x = o X=1
0
1
1
0

0
0
1
1

Complete the timing diagram shown in Figure Q3a. Clearly mark on the diagram
the times at which the value of Z should be read. All states changes occur after
the rising edge of the clock.
Draw the state diagram of the sequential machine.

ii)

CLK
X

I
I

I
I

PS

NS

z
Figure Q3a
(10 marks)
b)

An electronic combinational lock has a reset push button 'R' and three operating button
X, Y and Z. The lock will open only if the operating buttons are pushed in the correct
order. If the order is wrong, the reset button must be pushed to allow a new attempt.
Assuming the correct order of operating buttons is 'XYZ'. Construct the state diagram and
ASM chart for the Lock.
(15 marks)

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EE/JUNE 2012/ECE621/614/KJE521

QUESTION 4
a)

Figure Q4a shows an architecture declaration that is part of a testbench file and
generates signal a, b, c, and d. Draw a dimensioned timing diagram showing the
waveforms and physical times of events on the signal a, b, c, d for the first 65ns of the
simulation.
ARCHITECTURE behave OF testbench IS
SIGNAL a,b ,c,d: std logi C : - i 0 1 ;
BEGIN
P3: PROCESS
BEGIN
a <= I 1 ; WAIT FOR 10 ns;
b <= not ]b; c <= b; WAIT FOR 10 ns;
d <= 1'; WAIT FOR 10 ns ;
d <= 0'; a < = 0';
END PROCESS P3;
END ARCHITECTURE behave;

Figure Q4a
(7 marks)
b)

Consider the function / = 5^(2,3> 4,6,7)- Show how it can be realized using two twoinput LUTs. Give the truth table implemented in each LUT.
(8 marks)

c)

Figure Q4c shows a combinational logic circuit. Find all test vectors and fault tested that
test stuck-at-faults inputs along the path A-a-p-v-f.
AB-

E>

=o
Figure Q4c
(10 marks)

END OF QUESTION PAPER

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