Purple Techno Solutions

#39-8-28,Gateway Hotel Backside,

Labbipet, Vijayawada -10
Ph: 0866-6663311, 9985473300
Email: Bhanu@purpletechnosolutions.com
www.purpletechnosolutions.com

S.NO

VLSI (B.Tech.)
Projects Titles(2014-2015)

HDL

Design of FIR Filter Design Based on Faithfully Rounded Truncated MCM

VERILOG

Implementation of JPEG2000 using DWT

VERILOG

FPGA implementation of multi operand redundant adders

VERILOG

Multi bit Flip-Flop design for Area efficiency

VERILOG

MDC FFT/IFFT Processor With Variable Length

VERILOG

Built in generation of functional broadside tests using a fixed hardware

structure

VERILOG

Constant and high speed adder design using QSD number system

VERILOG

Digital-Serial FIR Filter Algorithms, Architecture and a CAD Tool

VERILOG

A Common Boolean Logic(CBL) implementation for modified CSLA

VERILOG

10

High speed vedic multiplier using barrel shifter

VERILOG

11
12

Comparative analysis and optimization of active power and delay of 1-bit full
adder at 45nm technology
A new approach to design fault coverage circuit with efficient hardware
utilization for testing applications

BACK END

VERILOG

13

Design of Parallel Carry-Save Pipelined RSFQ Multiplier

VERILOG

14

Single phase clock distribution using VLSI technology for low power

VERILOG

15

Design and implementation of efficient Quaternary Signed Digit Multiplier

VERILOG

16

High Speed FPGA implementation of FIR Filters for DSP Applications

VERILOG

17

Design and implementation of Floating Point Multiplier based on Vedic

Multiplication Technique

VERILOG

18

A Novel Approach for parallel CRC generation FOR High Speed Application.

VERILOG

19
20
21
22

High speed Modified Booth Encoder multiplier for signed and unsigned
numbers.
Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA
Implementation.
Efficient VLSI Implementation of DES and Triple DES Algorithm with
Cipher Block Chaining concept using Verilog and FPGA
Implementation of an Efficient Multiplier based on Urdhva Tiryakbhyam
Sutra

VERILOG
VERILOG
VERILOG
VERILOG

23

A Floating point Fused Dot Product Unit

VERILOG

24

Implementation of Power Efficient Vedic Multiplier using DBNS

VERILOG

Reach Us:
#11-13-1099/301,Sai Enclaves, Road No.1, Green Hills Colony, Saroor nagar, Hyderabad..
+91-9030880505

Purple Techno Solutions

#39-8-28,Gateway Hotel Backside,
Labbipet, Vijayawada -10
Ph: 0866-6663311, 9985473300
Email: Bhanu@purpletechnosolutions.com
www.purpletechnosolutions.com
25

LUT Optimization for Memory-Based Computation

Area Efficient parallel FIR Digital Filter Structures for Symmetric
Convolution based on Fast FIR Algorithm
Measurement and evaluation of power analysis attacks on Asynchronous SBox.

VERILOG

28

High Speed Booth Encoded Multiplier to Minimize the Computation time

VERILOG

29

Design Of Area Optimized AES 128 Algorithm Using Mix column

Transformation.

30

VLSI design Of a Digital Clock Using GALS Technique

VERILOG

31

Efficient Weighted Pattern Generation Technique with Low Hardware

Overhead

VERILOG

32

SCA-FF and SCAh-FF design for single cycle access test

VERILOG

33

Design and implementation of a high performance multiplier using HDL

A VLSI Implementation of Modulo Multiplier By Using Radix-8 Modified
Booth Algorithm
Platform-Independent Customizable UART Soft-Core
A Parallel Multiplier Accumulator Based On Radix 4 Modified Booth
Algorithms by Using Spurious Power Suppression Technique

VERILOG

37

Using Self-Immunity Technique 64-bit Register File Immunity Improvement

VERILOG

38

VERILOG

40

A Novel Nanometric Parity Preserving Reversible Vedic Multiplier

High Speed 3D DWT VLSI Architecture for Image Processing Using Lifting
Based wavelet Transform
Pulse Triggered Flip-Flop Design for low power

BACK END

41

Faster and Low Power Twin Precision Multiplier

VERILOG

42

Design and Analysis of Low Power Parallel Prefix VLSI Adder

VERILOG

43
44

VERILOG

46

FPGA Implementation of Booths and Baugh- Wooley Multiplier

Implementation of Area Efficient 16bit Adder in FPGA
Reliable and Higher Throughput Anti-Collision Technique for RFID UHF
Tag
Implementation of Bus Bridge between AHB and OCP

47

VLSI Implementation of OLS encoders

VERILOG

48

Implementation of OFDM System using IFFT and FFT

An Efficient FPGA implementation of Double Precision floating Point
Multiplier
FPGA Based High Speed Parallel Cyclic Redundancy Check
High speed carry save multiplier based linear convolution using Vedic
mathematics
FPGA Implementation of 2-D DCT Architecture for JPEG Image
Compression

26
27

34
35
36

39

45

49
50
51
52

VERILOG
VERILOG

VHDL

VERILOG
VHDL
VERILOG

VERILOG

VERILOG
VERILOG
VHDL
VHDL
VHDL
VERILOG
VERILOG
VERILOG

Reach Us:
#11-13-1099/301,Sai Enclaves, Road No.1, Green Hills Colony, Saroor nagar, Hyderabad..
+91-9030880505

Purple Techno Solutions

#39-8-28,Gateway Hotel Backside,
Labbipet, Vijayawada -10
Ph: 0866-6663311, 9985473300
Email: Bhanu@purpletechnosolutions.com
www.purpletechnosolutions.com
53

Performance Evaluation of Complex Multiplier Using Advance Algorithm

54

Design of High Speed Vedic Square by using Vedic Multiplication

Techniques

VERILOG

55

Realization of Basic Gates Using MUX in CMOS Design

BACK END

56

A Verilog Model of Universal Scalable Binary Sequence Detector

VERILOG

57
58
59
60

Hardware modeling of binary coded decimal adder in field programmable

gate array
High-Performance High-Valency Ling Adders
Short Bit-Width Twos Complement Multipliers
Design and Implementation of Two Variable Multiplier Using KCM and
Vedic Mathematics.

VHDL

VERILOG
VERILOG
VERILOG
VERILOG

Reach Us:
#11-13-1099/301,Sai Enclaves, Road No.1, Green Hills Colony, Saroor nagar, Hyderabad..
+91-9030880505