STA ASSIGNMENT 1

1) What is setup timing, for which cells do you verify setup time? Why do we need to do setup
timing analysis?
2) If we close design with setup timing violations, what is going to happen to the chip after
manufacturing?
3) Is setup time requirement for any given flop is constant or variable? On which factors setup
time value of a flop depends on?
4)

What is basic setup timing equation for R-R, R-I, R-O, I-O paths?

5) Does all R-R paths are valid timing paths? If Not, which condition R-R path may not be
valid?
6)

Does all R-I, R-O & I-O paths are valid? Which could be false paths? Why?

7) What is mean by feedthrough? Is a feedthrough is an I-O path? Do we need to do timing

analysis on a feed through path?
8)

What are valid timing start points? What are valid timing end points?

9)

What is hold timing? Why hold time value is required for any sequential element?

10) If we dont meet hold timing on any flop what will happen after silicon get manufactured.
11) Can tape out design without meeting setup timing violation? What is the impact if we do?
12) Can we tape out design without meeting hold timing? What is the impact if we do?
13) What is hold timing equation for R-R,I-R,I-O,R-O paths?