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Negative Bias Temperature Instability

Understanding the mechanism, modelling and affects

Tauseef Siddiqui
Masters of Science Communication Engineering (MSCE)
Institute of Integrated System (LIS), Technische Universitat Muenchen
Munich,Germany
tauseef.siddiqui@tum.de
Abstract A synopsis of negative bias temperature instability
(NBTI) found in PMOS devices has been discussed here. I have tried
to explain the physical mechanism involved in origin of the
phenomenon. I have also presented some of the models proposed to
explain this, later I have briefly explained various factors affecting
NBTI or its modelling depends. Although this is known for quite a
long time but still there are several aspects not well understood.

I.

INTRODUCTION

The phenomenon of Negative temperature Instability or


NBTI has been known since 1966, but in recent years has
become a dominant mechanism in current CMOS
technologies[1]. It is primarily due to increased gate electric
fields, increased scaling and operating temperatures, addition of
nitrogen to thermally grown SiO2. It has recently gained more
attention as a serious issue to device reliability. A lot of effort is
being made to understand the underlying physical mechanism,
research is being done to develop improved device and circuit
models.
Until today, various models have been proposed for
understanding and measuring NBTI yet the basic mechanism is
not completely understood. I have tried to incorporate the basics
of NBTI, contributing factors and its impact on general circuit
performance. The subjects of our interest are: (i) generation of
interface traps (Nit) and oxide charges (Not) and their
dependence on Gate Bias Voltage (Vgb), (ii) recovery of Nit and
Not and their dependence on above parameters (iii) impact of
nitrogen on Nit and Not. Understanding NBTI will help us in
determining the (i) reliability budgeting for a technology node
(ii) test conditions and burn-in (iii) TCAD and Spice models (iv)
process parameters for NBTI control.
II. WHAT IS NBTI ?
NBTI is a phenomenon resulting in increase in absolute
threshold voltage, a degradation of the mobility, drain current
and transconductance of p-channel MOSFETs. It was first
reported in 1967 by Deal and his colleagues[2]. It has been
generally accepted that the stress conditions i.e. negative bias at
elevated temperature leads to creation of interface traps and
oxide charges. Although NBTI stress may damage NMOS
devices but the damage is not initiated in the operational
configuration of the NMOS device therefore the PMOS devices
usually receive the major focus in Bias-temperature stress
issues. The current understanding believes that holes are
essential to generate NBTI degradation.

A. Understanding the phenomenon:


The mechanism is accelerated at high temperatures and
relatively low oxide voltages (or fields) and is mostly (not
always) lower than the voltage required for hot carrier
degradation.
We shall be seeing that the Vt shift and interface states
generation occur at the same rate[3]. The overall Vt shift is due
to trapped charges plus activated interface states. We can also
see it from our basic MOSFET physics that the Vt (threshold
voltage) of a device is proportional to the number of charges
over the capacitance of the gate oxide.
These charges in the device can be fixed positive charges as
well as charges that have populated an interface state (which
dependents upon the surface potential applied). Therefore,
changing the amount of fixed charges and interface states within
the device will result in a Vt shift. Other important device
parameters such as the drain current and transconductance are
subsequently affected. The damage can be therefore measured
by measuring these electrical device parameters.
The parameters affected by NBTI significantly influence
device performance such as, Vt shifts which affects matched
devices and analogue circuits. Drain current degradation affects
the device performance (driving capability) in a circuit. An
increase in the gate induced drain leakage (GIDL) current affects
the standby current which is critical for DRAM memories.
Depending upon the level of NBTI effect in particular
technology node, the impact can be quite drastic, ultimately
leading to timing issues and circuit failure.
As such its also important to understand the basics of
physical mechanism that leads the formation of interface traps
and oxide charges.
B. Interface Traps and Charges: a breif overview
As we have seen above that NBTI phenomenon generates
interface states and positive fixed oxide charges in the device
in operation. We briefly look into basic physical mechanism
of what these are and what electrochemical models have been
proposed to demonstrate their generation. An interface trapped
charge also known as interface trap, is a boundary trivalent Si
atom with an unpaired valence electron at the SiO2 /Si (i.e.
Oxide and Substrate) interface. We represent here it by Si 3
Si, where is the unpaired electron in its dangling bond.

Interface traps are also called as Pb centers [4]. They occur at


defects generated during oxide growth due to the naturally
occurring mismatch-induced stress at the SiO2 /Si interface.
They are quantified by Nit (number, in cm-2), Qit (charge
density, in C/cm2) and Dit (field, cm-2 eV-1). Based on their
charge state differences there are two types of Pb centers Pb0
and Pb1. Experimentally it has been found that Pb1 centers are
electrically inactive (at lower temperatures) and defects
arising from Pb0 are main contributors of the interface
traps[5]. Pb1 centers are typically generated at lower density
compared to Pb0 and are hence less important. When
electrons/holes occupy these centers they become charged and
hence vary the threshold voltage, else they remain neutral, see
Figure1. These defects act as generation/recombination
centers and contribute to leakage currents, low frequency
noise and reduced mobility, drain current and
transconductance[6]. In PMOS devices these traps are
occupied by holes making them positively charged and hence
making the threshold voltage more negative.
Interface traps

O (oxygen)

Si

The most widespread model is Reaction-Diffusion Model


proposed by Ogawa et al. The reaction limited process, where
interface traps are generated, is the interaction between the
inversion layer holes and Si-H bonds near interface [9, 10].
These holes interact with Si-H bonds leaving behind Sidangling bond (i.e. interface trap Nit) and hydrogen species,
figure 2. Hence Nit depends on the availability of the number
of holes and can be counted by released hydrogen atoms. The
interface traps generation has linear dependence on stress
time. Next is the diffusion limited process, where hydrogen
species move away from interface to oxide. The diffusion on
hydrogen from silicon to oxide has a power law time
dependence tn where n of 0.25[11].
Si3 SiH + h+ Si3Si + H+ (Reaction phase, h+: hole)
Si3 SiH + h+ Si3Si+ + H0, H0 + H0 = H2

Silicon Substrate
Figure1. SiO2/Si interface with traps which are occupied by holes in PMOS.

The oxide charges contributing to NBTI has not been well


understood. They can be mobile charges like Na, K, Li, oxide
trapped charge like electrons/holes and fixed charges. The
oxide charge is positive and present in SiO2. It is generally
believed that hole trapping is principal mechanism.
III.

NBTI MODELS: A BREIF OVERVIEW

Now having understood the interface traps and charges and


their contribution in causing NBTI. We discuss some proposed
electrochemical models for their creation. Rather going into the
details of the chemical process we focus on how complex is the
NTBI mechanism and highlight its strong dependence on
specific device process.
Amongst the first model was proposed by Jeppson and
Svensson, where surface defects generate the fixed charges and
interface states [7]. The defect is activated during stress
conditions and the number of interface states is equal to number
of fixed charges (Nit=Nf). The reaction is surface defect
dependent.
Si3SiH + O3 SiOSiO3 Si3Si + O3Si+ + O3SiOH + eAnother similar process proposed by Blat et al. where holes
and water related species are the primary mechanism for
NBTI [8]. During stress the hydrogen bond is broken resulting
in an interface state and a positively charged water species.
Here the number of interface states also depends on number of
positive charges.
Si3 SiH + A +p+ Si3Si + B+

Figure2. During Stress conditions H/H2 diffuse into the Poly generating Interface
Traps (Nit). During relaxation/recovery period H2 diffuses back[12,13]

The true value of n is important for prediction of the NBTI


lifetime. The hydrogen species released can either move towards
(a) poly/gate (b) combine with other H atoms to form H2 (c)
recombine back with Si- also known as Nit passivation. This is
a temperature dependent process in high temperature conditions
the hydrogen may diffuse into the poly and the chances of
recovery/passivation becomes less.
A. Why only PMOS and not NMOS?
A natural question arises that what makes PMOS more
susceptible to NBTI than compared to NMOS. It has been
observed and measured as in figure3 that PMOS is severely
affected in both positive and negative bias[14,15]. One of the
reasons proposed by Tsetseris et al. that the positive Hydrogen
H+ that interacts with SiH bond at interface i.e. Si3 SiH creates
the dangling bond originates from phosphorous hydrogen P-H
bond present in n-substrate. Where as in p-substrate in NMOS
has boron-hydrogen bond B-H which are difficult to break.
Another reason depends on the charge states of Nit (interface
traps) and Not (oxide charge). Under stress conditions and during
MOSFET operation the n-channel has negative and the pchannel has positive interface trap charge. But the oxide charge
is positive in both cases, therefore in n-channel we have Qoxide Qit while in p-channel we have Qoxide + Qit , so we see PMOS
device is severely affected.

Figure5:
Change in Vt
and SILC with
time for
various Vg.
Not is shown
by line. [17,
18]
Figure3: Variations in Threshold Voltage for PMOS and NMOS under positive
and negative bias conditions[14,15]

IV. FACTORS INFLUEINCING NBTI


Having seen the complexity of the NBTI mechanism, we
discuss important factors related process and modelling.
A. Recovery of NBTI:
NBTI measurements such as Vt, Nit/Dit, drain current etc were
made with some time delay after stressing the device. But this is
very important as the recovery process starts very immediately
after the stress damage. The stress degradation has two
components (1) permanent: remaining after the stress (2)
temporary: reversible and recovers[16]. It is attributed that
recovery was majorly by oxide charges Dot and that interface
traps (Nit/Dit) remained mostly unchanged[14]. As can be seen
in figure4 that during the stress period Nit and Vit changes are
similar but during the recovery phase Nit remains practically
constant.

Figure4: Variation of Vit and Nit during stress (negative bias voltage) and
recovery phases (positive bias voltage).[14]

B. Choice of Gate Bias (stress) and Substrate Voltage(bulk):


We have seen earlier that the degradation follows a power
law time constant n of 0.25. But for higher Vg and Vb the Vt
increases for longer time and both Vt and Nit show tn power
law with greater n than .25. Also at higher Vg the SILC (Stress
Induced Leakage Current) is observed. The onset time for SILC
coincides with coincides with the increased Vt, figure5. This is
because at high Vg electrons tunnel from gate into substrate and
cause impact ionization resulting in hot holes (HH) [17, 18].
This HH produces further traps (Nit) and oxide charges (Not).
Biasing Vb >0 also causes HH during the stress phase figure6,
while in recovery phase Nit recovery is same with or without
Vb bias. Hence during NBTI measurement Vg has to vary from
low to intermediate moderate value so that Nit follows Vt
figure 7

Figure6:
Increment of Nit
and Vt with time
for Vb=0V and
Vb>0V during
stress phase.
Increased Vt,
Nit and SILC
with time during
stress phase [19]

Figure7:
Coincidence of
Vt and Dt (Dt
= Nt//E) for
various values of
Vg. Vg was kept
below to the level
of impact
ionization. [17,
18]

C. AC and DC stress conditions:


As we have seen that during the recovery phase of device
there is still a portion of Nit and Vt that doesnt recover
back totally. It is important to know how the device
behaves under AC and DC stress conditions. When device
is applied stressing pulses it is said to be under AC stress.
Under the AC stress conditions device recovers during the
zero stress pulse and hence the degradation rate is higher in
DC stress, where permanent stress voltage is applied,
compared to AC stress, see figure. Also in the degradation
rate under AC stress depends on the duty cycle of applied
AC stress signal [20, 21].

Figure8: Vt shift under DC and AC Stress with different duty cycles [19]

D. Impact of Nitrogen on Substrate:


Nitrogen has been incorporated in the gate oxide to reduce the
boron penetration in low voltage PMOS devices. Presence of
nitrogen in the oxide has been reported to increase the NBTI
degradation, figure9 [22], by increasing the number of
interface hole traps[24]. The effect of nitrogen has not been
well understood. Surplus nitrogen concentration near
substrate/oxide region causes more NBTI degradation when
compared to gate/oxide region. This effect also depends on the
particular nitridization process. In figure9 we can see plasma
nitridization reduces the degradation compared to nitrous
oxide. Because here nitrogen diffuses from top of the oxide
near gate/oxide.

intricacies of presentation. I would like to thanks Technical


University Munich for providing required assistance.
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Figure9: Drain Current showing Plasma Nitrided Oxide is better [23]. Vt
degradation with Nitrogen concentration [22].

E. Impact on Circuits:
For digital circuits the switching capacity of the MOSFET is
reduced by increase in Vt and eff reduction due to NBTI. The
delay time Td
C|Vdd|
Td=

Id

WeffCox(Vdd-Vt)2

WeffCox
1 dId
2Vt
(Vg-Vt)Vd
=L
Id dVt Vg-Vt

The static noise margin of SRAM cells is degraded. In case of


the analog circuits the gate-drain capacitance CGD increase
because of the traps. The only parameter benefiting is Ioff as VT
becomes more negative and can be seen here
qVt
Ioff=It exp (
)
nkT

V.

[11]

[12]

2LC
=

There drain current ID is twice degrades as in linear region


Id

[10]

CONCLUSION:

NBTI mechanism and how it affects our modern day circuits


has been discussed. We could see that there are various
parameters affecting the measurement of NBTI and how they
must be carefully addressed beforehand. Even though the
problem of NBTI is fairly old but still is not well understood.
The reason for the generation of positive oxide charges is yet to
be fully understood. The value of n=.25 which is yet debatable
is important to predict the lifetime of the device. Impact of
nitrogen and its position in oxide is still not well known.
Currently work being done to model NBTI for prediction of
circuit lifetime and developing mitigation techniques
ACKNOWLEDGMENT
I would like to thank Mr. Erol Koser for his guidance and
mentorship. He guided throughout writing of the paper and

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