IIT Blackfin Presentation

The World Leader in High Performance Signal Processing Solutions
Blackfin
Presentation
ADI programmable processor Architecture
2.5G/3G Infrastructure
Medical Imaging
Industrial Imaging
Multiprocessing
TigerSHARC
High Performance
Performance
Wired Voice
Wireless Voice
VOIP/VON Blackfin
Industrial Control ADSP-BF53x
Media enabled SHARC
ADSP-21xx Fixed Point Low Cost
Power efficient Floating Point
Image compression
Fixed Point 3G Terminals
Digital Still/Video Camera Audio
MMOIP Infotainment
Telematics Industrial
Biometrics
What does Enable?
Human Interface Wireless Connectivity
Speech Recognition Bluetooth
Text To Speech GSM
Digital
Handwriting 3rd Generation
Signal
Audio
Processing
Digital Imaging
Wired Connectivity CODECs
USB MPEG
TCP/IP JPEG
MOST Network H.263
H.323/MEGACO H.264
Micro- Image
Processing Processing
Designed for
Operating High Level
Systems / Language
RTOS System Control / Applications Software
Blackfin Processors Perform
Signal Processing and Micro-controller Functions
Signal
Proc
Signal
Proc
ASIC Traditional
MCU model
Signal
Control
Proc
Networking Interfaces to sensors
RTC Broad peripheral mix
Watchdog Memory
RTOS
MMU
Byte addressable New model
Blackfin can perform all of

these functions
Blackfin – Micro Signal Architecture
The Micro Signal Architecture was crafted with the

requirements of a controller and a DSP in mind
Blackfin IS NOT just a DSP with an enhanced instruction set

Blackfin IS NOT just a processor with a couple of arithmetic units
added
Blackfin IS an architecture that is optimized to perform equally well

on both control and numeric algorithms
Blackfin CAN easily be programmed in assembler, C/C++, or mixed
Blackfin – A Convergent Processor
BLACKfinis a high performance dual MAC DSP with features

more normally seen on a 32-bit RISC microprocessor
z Supervisor and User Modes
z Memory Protection
z Byte addressing
z 8-, 16-, 32-bit math
z Multimedia processing extensions
Single Processor target for software development

Single development tools environment
Single Programming Model
Single Instruction Set
Simplified emulation of otherwise asynchronous cores
Blackfin
Native Hooks in core for Audio & Video processing
Video Compression
z Up to four 8-bit math operations in a single cycle
z ~300 cycle execution for an 8*8 DCT (the foundation of MPEG motion estimation)
z IEEE 1180 Rounding maximizes efficiency
z Motion Estimation Executes four partial Sum Absolute Differences in a single
cycle
z Huffman Coding Field Deposit / Extract instruction
Audio
z Voice Codecs: On-The-Fly Saturation for 2G, 3G
z Extended precision for Dolby decoding
Other
z Instruction Set Support for Complex Math, Bit Interleaving, Population Count,
Viterbi Dual Add-Compare-Select, and CRC
Blackfin – Dynamic Power Management lowers
power consumption
600 MHz, 1.2V 500 MHz, 1.2V
Frequency Only
Power (mW)
200 MHz, 1.2V Power Savings

Voltage & Frequency
500 MHz, 1.0V

200 MHz, 0.8V
Video Processing Audio Processing
Self contained, software programmable power management system that

allows for independent control of either frequency or voltage
Variable Frequency
Clock dividers (1x to 63x) enable low latency changes in system performance
Variable Voltage
On-Chip Voltage Regulator generates accurate voltage from 2.25 – 3.6V input
Core voltage programmable from 0.8V to 1.2V (50 mV increments)
Blackfin – MMU Protects You
Supervisor & Application Code

User Protection User User User
of Memory and
Registers Peer-Peer Protection
Protected System
Environment
Power Down
Supervisor Emulation
States
System Code and Event Handlers

Blackfin
Industry Standard RTOS and OS Support
Operating Systems
µCLinux – Now
Real Time Operating Systems

VDK from ADI - Now
Unicoi Fusion - Now
Accelerated Technology Nucleus - Now
Express Logic ThreadX - Now

Control Quadros RTXC - Now
Applications
Green Hills INTEGRITY– Now
Real Time
Green Hills VelOSity – Now
OS DSP Code
VCSE uITRON (API) - Now
Networking Stacks
RTOS Kadak Kwik-Net – Now
Unicoi Fusion Net – Now
Blackfin Express Logic Net-X – Now

Architecture
Core
L1
Core
Instruction
Timer 64 Memory
Performance Core LD0 32

Monitor Processor L1 Data
LD1 32
Memory
JTAG/
Debug
SD32
Core D0 bus
DMA Mastered 32 32 Core DA0 bus 32 Core D1 bus 32 Core DA1 bus 64 Core I bus
32
bus Core Clock (CCLK) Domain
System Bus Interface Unit System Clock (SCLK) Domain
16 DMA Core Bus (DCB)

16
Data
Watchdog Event Power DMA Controller EBIU
Real Time Clock Address
And Timers Controller Management 16
Control
DMA Ext Bus External Port Bus
(DEB) (EPB)
16 16
Peripheral Access Bus (PAB)
DMA Access Bus
(DAB) External Access Bus
(EAB)
ETHERNET UART0/1 1KB internal Programmable

TWI CAN SPORTs SPI PPI
MAC IRDA Boot ROM flags
PORTS
BF536/7 Only
Blackfin DSP : MSA Architecture
Fixed point DSP Math

z Dual 32/40 bit Data ALUs with 40-bit Accumulators
z Dual 16-bit MACs
z Dual 32-bit Data Address Generators (DAG) ALUs
Conventional addressing modes (with pointers) for C code
Modified Harvard Memory Architecture

z Two data ports and one code port for the unified 4G Byte
addressable memory architecture
Configurable hierarchical data and instruction
memories
z Caches or SRAM configured by the user
Instruction Set Optimizations
z Dual instruction lengths – 16 & 32 bits for “Control” and “DSP”
operations
z Dual instruction dispatch forms (16/32 bit & 64-bit (1x32, 2x16))
Blackfin : MSA Architecture
Address Arithmetic Unit Two 16-bit Multipliers

Two 32/40-bit ALUs
SP
FP
P5
I3
I2
L3
L2
B3
B2
M3
M2
Four 8-bit video ALUs
P4 I1 L1 B1 M1 DAG0 DAG1
P3
P2
I0 L0 B0 M0 Barrel Shifter
P1
P0 Sixteen 16-bit math
registers/Eight 32-bit
Sequencer math registers
Two DAGs, with byte
addressing support
R7
R6 16 16 Eight 32-bit pointer
R5 8 8 8 8
R4
R3
registers
R2 Barrel
R1 Shifter 40 40 Four sets of 32-bit
R0
Acc0 Acc1
index, modify, length
and base registers
Data Arithmetic Unit
Blackfin : Register Set
31 0
P0
Data Registers
31 15 Address P1
A0X A0 P2
Registers
A1 P3
A1X
P4
R0 R0.H R0.L P5
R1 R1.H R1.L
FP
R2
SP
R3
USP
R4 R4.H R4.L 31 0 31 0 31 0 31 0
R5 I0 L0 B0 M0
R6 I1 L1 B1 M1
R7 R7.H R7.L I2 L2 B2 M2
I3 L3 B3 M3
ASTAT Arithmetic Status LC0 Loop Counter

LT0 Loop Top
RETS Subroutine Return LB0 Loop Bottom
RETI Interrupt Return LC1

LT1
RETX Exception Return LB1
RETN NMI Return SYSCFG System Config
System
RETE Emulation Return SEQSTAT Sequencer Status
Registers
Blackfin : Data
Support for three data lengths.

z 32-bit, 16-bit and 8-bit data
Integer and fractional data types for 32-bit/16-bit data.
z 8-bit
data is always integer
z Signed/Unsigned data support for integers
LittleEndian data format.

ALU operands may be 16-bit or 32-bit.
Multiplier operand types are specified in the instruction.
Shifter operates on signed/unsigned operands
ASTAT FLAGs are updated upon ALU/MULT/SHIFT operations
Blackfin : ALU
2 ALUs exist in Blackfin MSA core

z Support arithmetic and logical operations on fixed point data
z ALU instructions operate on 16-bit, 32-bit and 40-bit integer
(Accumulation) operands
Key ALU Instruction Categories
z Fixed point addition and subtraction (register based and with
immediate values)
z Accumulation of multiplies
z Logical operations (OR, AND, XOR, NOR etc.)
z Functions : ABS, MAX, MIN, Division primitives etc.
Blackfin : Register View of Math
31 16 0
R2 Dual ALU / MAC

31 16 0
32 32 R3 functions are
“Vector” functions
Register MAC 0 MAC 1
File ALU 0 ALU 1 Two Pairs of
A0 A1 operands are
R6 R7 available
32 32
Blackfin : Multiplier & Accumulator
Blackfin supports 2 multipliers

z Can perform 2 Multiply and 2 Accumulates (2 MACs)/cycle
z 2 Accumulators – 40 bits each (8 guard bits)
Destination register may be an R register or an Accumulator.
Saturation to either 32/40 bits possible in Accumulator
Optional rounding possible for destination R register.
Input formats can be
z FU – Fractional Unsigned
z IS – Integer Signed
z M – Mixed signed and unsigned operands
Multiplier overflow status bits exist in ASTAT

Blackfin : Data Address Generators
31 0 31 0 31 0 31 0 31 0
I0 L0 B0 M0 P0
I1 L1 B1 M1 P1
I2 L2 B2 M2 P2
I3 L3 B3 M3 P3
P4
• Four sets of 32-bit Index, Base, Length Registers for
DSP Circular buffers. P5
• Four Modify Registers used with any of the Index
Registers access 16-bit and 32-bit aligned data FP
•Separate stack pointer for user and supervisor modes SP
aliased to SP
USP
Addressing modes : Indirect, auto-
increment/decrement, post modify with • Six 32-bit Pointer
non-unity stride, indexed with immediate Registers for general use to
access 8, 16 and 32-bit data
offset, Circular buffer and Bit reverse
Addressing modes
Blackfin : Addressing Modes
Indexed Addressing with index Indexed

Addressing with
register immediate offset
z R0 = [I2] ; z P5 = [P1 + 0x100] ;
z R0 = W[I2] ;
Post modify Addressing
Indexed Addressing with
z R5 = [P1 ++ P2] ;
pointer register
z R6 = W[P4++P5](Z) ;
z R1 = [P0] ;
z B [P1++] = R3 ; z R2 = [I2 ++ M1] ;
Autoincrement and Auto DAGand Pointer register

decrement addressing modifications
z R0 = W [P1++] (Z) z I1 += M2 ;
z R2 = [P2--]
Alignment exception support
Premodify Stack pointer
z [--SP] = R3 ;
Program Sequencer
The Program Sequencer controls all program flow
Maintains
z Loops
z Subroutines
z Jumps
z Idle
z Interrupts and Exceptions
Contains an 10-stage instruction pipeline

z Pipeline is fully interlocked -> all the data hazards are hidden from the
programmer
Avoiding Pipeline Stalls
Most common numeric operations have no instruction latency
VisualDSP++ Pipeline Viewer highlights Stall, Kill conditions
Unconditional Branches in the Pipeline
Branch target address calculation takes place in the AC stage

Branch Target address is sent to the Fetch address bus at EX1 stage
Latency for all unconditional branches is 4 cycles
1 2 3 4 5 6 7 8 9 10 11 12 13
IF1 I1 Br I2 I3 I4 I5 BT
DC I1 Br NOP NOP NOP NOP BT
AC I1 Br NOP NOP NOP NOP BT
EX1 I1 Br NOP NOP NOP NOP BT
EX2 I1 Br NOP NOP NOP NOP BT
EX3 I1 Br NOP NOP NOP NOP
EX4 I1 Br NOP NOP NOP
WB I1 Br NOP NOP
I1: Instruction Before the Branch Br: Branch Instruction BT: Instruction at the Branch Target
Conditional Branches (Jumps)
Conditional Branches are executed based on the CC bit.

A static prediction scheme (based on BP qualifier in instruction) is
used
Branch is handled in the AC stage.
In the EX4 stage, true CC bit is compared to the predicted value.
Prediction Not Taken Taken (BP)
Outcome Taken Not taken Taken Not taken
Latency 8 cycles 0 cycles 4 cycles 8 cycle

Hardware Loop
Supporttwo zero-overhead nested loops

Load Loop registers by using the Loop Setup (LSETUP) instruction
Registers can also be set manually

If more than 2 nested loops are required, the stack must be used
Events (Interrupts / Exceptions)
The Event Controller manages 5 types of Events:
Emulation
Reset
Non-Maskable Interrupt (NMI)
Exception
Interrupts
z Hardware Error
z Core Timer
z 9 General-Purpose Interrupts for servicing peripherals
Blackfin : Interrupt Management
IMASK Register – bits 0-15

z Indicates when the corresponding interrupt is enabled
ILAT Register – bits 0 - 15
z A set bit indicates an interrupt has been ‘latched’ to be serviced
IPEND Register – bits 0 – 15
z A set bit indicates an interrupt service is ‘pending’; that is, the highest bit
set indicates which service routine is being executed
RAISE n Instruction ( n = 0-15 )
z Forces a bit to be set in ILAT. It ‘raises’ the priority of the execution
EXCPT n Instruction ( n= 0-15 )
z Forces an exception to occur : EVSW bit is set in ILAT and ‘n’ determines
which exception routine to execute
Blackfin : Interrupts
Emulator 0 EMU
RESET 1 RST
Highest
Non Maskable Interrupt 2 NMI
Exceptions 3 EVSW
- 4 -
Hardware Error 5 IVHW

Timer 6 IVTMR
General Purpose 7 7 IVG7


Lowest
Blackfin : Configurable Memory System
Supports a Cache Memory Model and an SRAM Memory Model
Sustained Dual Data Accesses for DSP Applications
Supports accesses of 8,16, 32 bit data
Separate Multi-ported L1 Instruction and Data Memories
Cache Memory for Microcontrollers & SRAM for DSP Applications
Memory management for Cache Protection
L1 Instruction L2
SRAM & Cache Instruction
& Data
Processor SRAM
Core L1 Data
SRAM & Cache
Scratchpad
SRAM
DMA
Blackfin : Memory Architecture
Configurable Memory ? Why ?

z As processor speeds increase ( 300Mhz – 1 GHz ), it becomes increasingly difficult
to have large memories running at full speed – routing wire delays are very
significant
The Solution
z Solution is Hierarchical Memory with L1 memory not in the critical speed path
Two methods can be used to fill the L1 memory – Caching and Dynamic
Downloading – Blackfin Supports Both
z Micro-controllers have typically used the caching method, as they have large
programs often residing in external memory and determinism is not as important
z DSPs have typically used Dynamic Downloading as they need direct control over
which code runs in the fastest memory
MSA allows the programmer to chose one or both methods to optimize
system performance
Blackfin : L1 Instruction Cache
4KB 4KB
mini-bank mini-bank
Fill by L2
DMA
Code to Core
4KB 4KB
mini-bank mini-bank
16KB SRAM • 16 KB cache

Four 4KB single-ported • 4-way set associative with
mini-banks arbitrary locking of ways
Allows simultaneous DMA • True LRU
access to different banks
• No DMA access when
Entire 16K configured as
cache or SRAM configured as cache
Blackfin : L1 Data Memory
Fill A
16KB
4KB
super-bank A
SRAM DMA A
Data 0 Fill B
16KB
super-bank B
Data 1 DMA B
Two 16KB super-banks

Each super-bank can be cache or SRAM
4KB scratch SRAM (stack can be located here for fast context
switching)
Blackfin : L1 Data Super bank Architecture
4KB 4KB
mini-bank mini-bank
Four 4KB single-ported L2
mini-banks Fill
DMA
Data 0
Data 1
Multi-ported data 4KB 4KB

access when using mini-bank mini-bank
different mini-banks
• When Used as Cache • When Used as SRAM

– Each bank is 2-way set- – Dual Data Access
associative – DMA Access
– No DMA access
– Entire 16K Configured as
cache/SRAM
Blackfin : L1 Memory Configurations
L1
Data memory can be L1Instruction memory
configured in SRAM or Cache cannot be accessed directly
Modes through DAGs
z 32K SRAM z Use L2 memory for such
z 16K SRAM & 16K Cache accesses.
z 32K Cache
Core and DMA can access
Additional 4K Byte of Scratch L1 memory banks
pad SRAM
simultaneously.
z Stacks and heaps can be stored
in scratch pad SRAM DMA controller has higher
L1 memories operate at Core priority over core accesses.
Clock frequency
Write through and Write back
modes are supported
Blackfin : MMU
Memory Management MMU Property

Unit Descriptors
z Caching and Protection Look- z Page Size
Aside Buffers (CPLBs) z Dirty/Clean
z Cache/protection properties z Valid/Invalid
determined on a per memory z Write-through/Write-back
page basis (1K, 4K, 1M, 4M
z Cacheable/Non-cacheable
byte sizes )
z Supervisor/User access
z User/supervisor, and
task/task protection protection bits
z Read/Write protection bits
z Future products will support
address translation
System Clocking - Variable Frequency
Modification
on the fly
Modification requires
PLL Sequencing 1
÷ 1, 2, 4, 8 CCLK
CLKIN 10 PLL
1x - 63x 5
÷ 1 : 15 SCLK
CLKIN can be driven from

external oscillator or crystal SCLK =< CCLK
SCLK =< 133MHz
Reset values
On-chip Voltage Regulation
Generates core voltage

from external 2.25V to 3.6V
input
DSP TANTALUM C ERAM IC
INTERNAL OR Core voltage
CIRCUIT ELECTROLYTIC
VDDEXT programmable in 50mV
Ind10µH
VDDINT 2.25V -> 3.6V increments from 0.8V to
1.2V
10 µF .1µF
Optional bypass
EXTERNAL
VDDCTRL COMPONENTS Minimal external
-
+
Uz=4V components required
VREF
External Memory Interface
External Bus Interface
1M Byte Asynchronous
External Memory
19 Address 1M Byte Asynchronous

Interface
16 Data
512M Byte Synchronous

EBIU Overview
EBIU – External Bus Interface Unit

z 16-bit parallel interface
Comprisedof Asynchronous Memory Controller (AMC) and
Synchronous DRAM Controller (SDC)
z Share some pins
AMC supports devices such as SRAM, ROM, FIFOs, Flash
memory, and ASIC/FPGA designs
SDC supports PC-133 SDRAM devices
EBIU runs at the system clock rate (SCLK)
ADSP-BF537 External Memory Map
One memory region is

dedicated to SDRAM
z Up to 512MBYTE
Four ASYNC banks

z 1MByte each
Start
address SDRAM is
0x0000 0000.
Blackfin DMA capabilities
DMA Setup
Two Types of DMA transfers available
Register-based
z Program the DMA control registers directly
z Upon DMA completion, control registers are automatically updated
with their original setup values in Autobuffer Mode (multiple
transfers)
z The DMA Channel can also be configured to gracefully shut off
with Stop Mode (single transfer).
Descriptor-based
z Requires a set of parameters stored within memory to initiate a
DMA sequence.
z Supports chaining of multiple DMA transfers.
Descriptor Blocks
Descriptor Array Mode Descriptor List (Small Model) Mode Next_Desc_Ptr[15:0]
Next_Desc_Ptr[15:0] Start_Addr[15:0]
0x0 Start_Addr[15:0] Next_Desc_Ptr[15:0] Start_Addr[31:16]
Start_Addr[15:0]
0x2 Start_Addr[31:16] Start_Addr[15:0] DMA_Config
Start_Addr[31:16]
0x4 DMA_Config DMA_Config Start_Addr[31:16] X_Count
X_Count DMA_Config X_Modify
0x6 X_Count Descriptor
Block 1 X_Modify X_Count Y_Count
0x8 X_Modify
Y_Count X_Modify Y_Modify
0xA Y_Count Y_Count
Y_Modify
0xC Y_Modify Y_Modify
Start_Addr[15:0]
Descriptor List (Large Model) Mode
0xE
0x10 Start_Addr[31:16]
Next_Desc_Ptr[31:16]
0x12 DMA_Config Next_Desc_Ptr[31:16]
Next_Desc_Ptr[15:0] Next_Desc_Ptr[31:16]
0x14 X_Count Descriptor
Next_Desc_Ptr[15:0]
Block 2 Start_Addr[15:0] Next_Desc_Ptr[15:0]
0x16 X_Modify Start_Addr[15:0]
Start_Addr[31:16] Start_Addr[15:0]
0x18 Y_Count Start_Addr[31:16]
DMA_Config Start_Addr[31:16]
Y_Modify DMA_Config
0x1A X_Count DMA_Config
X_Count
0x1C Start_Addr[15:0] X_Modify X_Count
X_Modify
Start_Addr[31:16] Y_Count X_Modify
0x1E
Descriptor Y_Count
Y_Modify Y_Count
0x20 DMA_Config Block 3 Y_Modify
Y_Modify
……….…………
………………….
2-D Direct Memory Access
Data Capture & Storage
to Linear L2 Memory
Programmable
Programmable
XX&Y&YCount
Count&&
Stride
StrideValues
Values
A
A B C D E F G H B
K L M N O C
I J P D
E 2-D DMA to
F
G L1 Memory A, B, I, J
H
I
J
K
L
.
.
.
.
2-D DMA significantly decreases S/W overhead in video applications!
Blackfin Peripheral Interfaces
Parallel Peripheral Interface
External Clock
Up to 66MHz
PPICLK
SYNC
Appliances
Up To
16-bit
Parallel
Data
Bidirectional, half-duplex interface

PPI supports CCIR-656 Video Converter Interface
PPI - What is it?
Programmable bus width (8 – 16 bits)

Bidirectional (half-duplex) parallel interface
Synchronous Interface
z Driven by an external clock (PPI_CLK)
z Up to 66MHz rate (SCLK/2)
z Asynchronous to SCLK
Includes three frame syncs to control the interface timing

Applications
z High speed data converters
z Video CODECs
Used in conjunction with a DMA channel

PPI I/O Modes
8- or 10-bit data PPIx

PPI
w/embedded control
CCIR-656 ‘656-
Compatible
CLK PPI_CLK
Video Source
HSYNC
GP - Mode VSYNC PPI_FS1
Video Source FIELD PPI_FS2
PPI_FS3
PPI
8-16 bits data PPIx
CLK
PPI_CLK
SPORTs
Two synchronous serial ports

z Independent receive and transmit
z Internal or external generated clocks and frame TX Data 1
syncs TX Data 2
z Built in hardware for u-law & A-law companding Tx Clock
z Support for multi-channel TDM interfaces Tx Sync
z Dedicated DMA channels
z Generates optional interrupts
Rx Data 1
z Operates up to 1/2 System bus clock rate (SCLK)
RX Data 2
Rx Clock
Rx Sync
Serial Peripheral Interface (SPI)
Shift Registers Simultaneously Shift Data In And Out
Full duplex synchronous

serial interface SCK
Master and Slave mode PFx

supported
MOSI
Enable to communicate with
multiple devices
SPI_TDBR
SPI_RDBR
Up to SCLK/4 Operation
MISO
Universal Asynchronous Receiver/Transmitter
UART options
z 5-8 data bits ADSP-BF53x
z 1, 1½ or 2 stop bits
z None, even or odd parity
z Baud rate = SCLK/(16*DIVISOR)
z Supports half-duplex IrDA (9.6/115.2
Kbps rate)
z Autobaud detection support through the
use of the Timers
z Separate TX and RX DMA support
z Data is ALWAYS Transmitted/Received
LSB First
Industry Standard 16450 Compatible

Blackfin Timers
RTC Power
Eleven timers:
int
B
RTC clock
One Core Timer RTC
One Watchdog Timer
One Real-time Clock (RTC) Watchdog int
reset
Eight general purpose timers Timer NMI
z PWM Mode
z Pulse Capture Mode Core int
z External Clock Mode Timer
int int int
GP GP GP
Timer Timer Timer
Core Timer
Use to generate interrupts at multiples of CCLK rate

z 32-bit tick timer
Dedicated Interrupt Priority 6 (fixed)
Autoreload is optional
TPERIOD
32 bit
TSCALE TCOUNT IRQ 6

CCLK
8 bit 32 bit
Interrupt rate = CCLK x (TSCALE + 1) x TPERIOD

Watchdog Timer
Generating an event when the timer expires.
The event can be programmed to be:

za reset (software reset takes place)
z a non maskable interrupt
z a general purpose interrupt
Clocked by the system clock (SCLK).
Must be periodically serviced by software

Real-Time Clock
Typically used to implement real-time watch or “life counter”

z Time of day, alarm, stopwatch count-down, and elapsed time since last system
reset
Maintains time/day with 4 counters - Seconds, Minutes, Hours, Days
z Current time (Seconds, Minutes, Hours, Days) read/written in RTC Status
Register (RTC_STAT)
Equipped With Two Alarm features
z Daily and Day-And-Time
Uses dedicated 32.768 kHz crystal to RTXI / RTXO
z Setting pre-scalar (bit 0 in RTC_PREN) RTC can be pre-scaled to 1 Hz to count
time and days
Uses dedicated power supply pins
z Independent of any reset
Eight Peripheral Timers
Eight Identical Timers Can Be Configured In 3 Modes

z Pulse Width Modulation (PWM_OUT)
z Width and Period Capture (WDTH_CAP)
z External Event Counter (EXT_CLK)
Multiplexed Pins TMR7-0
One Programmable Interrupt Each
Three 32-bit Registers Each
Width (TIMERx_WIDTH)
z Period (TIMERx_PERIOD)
z Counter (TIMERx_COUNTER) (read-only)
One 16-bit Configuration Register Each (TIMERx_CONFIG)
Three Common Registers Affect All 8 Timers Simultaneously
z Timer Enable
z Timer Disable
z Timer Status (Interrupt requests, overflows, slave enables
General Purpose I/O
• Features:
− The processor supports up to 48 bi-directional GPIO (General
purpose Input/Output modules)
− To simplify the programming model, the 48 GPIOs are managed by
three different modules, each one associated PORTF, PORTG, and
PORTH
− Each module independently controls 16 GPIOs.
− Each GPIO can be configured as either an input or output by using
the GPIO Direction registers.
− For GPIO Input:
− Level or edge sensitive trigger of input source
− Rising or falling edge trigger of input source
− Single edge or both edges trigger of input source
General Purpose I/O Pins
48 bi-directional GPIO pins available
Each can be configured as an output, input, or an interrupt pin
SPORT1 PPI PGx

PPI D0 PG0
PPI D1
PPI D2
PPI D3
PPI D4
PPI D5
PPI D6
PPI D7 PG7
DR1SEC PPI D8 PG8
DT1SEC PPI D9
RSCLK1 PPI D10
RFS1 PPI D11
DR1PRI PPI D12
TSCLK1 PPI D13
TFS1 PPI D14
DT1PRI PPI D15 PG15
Two Interrupt
Requests (FLAGA/FLAGB)
What’s new in ADSP-BF534/6/7?

ADSP-BF537/BF536/BF534
• The BLACKfin family offers a variety of pin- and code-compatible
derivatives
ADSP- -BF537
ADSP BF537 ADSP- -BF536
ADSP BF536 ADSP- -BF534
ADSP BF534
500,600
500, 600MHz,
MHz, 500,600
500, 600MHz,
MHz, 400,600
400, 600MHz,
MHz,
Performance 1000,1200
1200MMACs
MMACs 1000,
1000,1200
1200MMACs
MMACs 1000,
1000,1200
1200MMACs
MMACs
1000,
On Chip RAM 132KBytes

132 KBytes 100KBytes
100 KBytes 132KBytes
132 KBytes
SparseMBGA,
Sparse MBGA, SparseMBGA,
Sparse MBGA, SpareMBGA,
Spare MBGA,
Package Options MiniBGA MiniBGA MiniBGA
MiniBGA MiniBGA MiniBGA
ADSP-BF537/BF536/BF534
Enhanced Blackfin Processors
System Peripherals User High System Integration
Dynamic Peripherals
Power Video I/O connects directly to
Management PPI ITU-R 656 encoders and
Up to 600MHz Video I/O decoders
Switching
Regulator Blackfin SPORTs support 8 Channels
Enhanced
Processor Core SPORTs 2
of I2S Audio
PLL
Core Voltage Regulator
SPI 1
Watchdog Microcontroller
features include
UART 2
JTAG Memory WDT, RTC, SDRAM controller
TWI
Up to Up to 32K
RTC 80K 64K 4K Bytes CAN
Bytes Bytes Bytes PM
Interfaces PM DM ROM Ethernet
New Blackfin features
FLASH/SRAM Timers 8
BF536/7 Only
Enhanced DMA GPIO 48
SDRAM
TWI
TWO WIRE INTERFACE
Fully compliant to the Philips I2C bus protocol

z See Philips I2C Bus Specification version 2.1
7-bit addressing
100 Kb/s (normal mode) and 400Kb/s (fast mode) data rates
General call address support
Supports Master and Slave operation

z Separate receive and transmit FIFO
SCCB (Serial Camera Control Bus) support
z Only in Master mode
Slave mode cannot be used because the TWI controller always issues
an Acknowledge in slave mode
DMA Enhancements
4 more DMA channels

z All twelve peripheral DMA channels can be assigned to any of the
connected peripherals.
SYNC Bit
z Allows more control over the DMA interrupt generation process.
DMA controller enhanced to provide the MAC further control
over the assigned DMA channels
Ex. Peripheral (MAC) detects incorrect checksum condition on
incoming data stream. The peripheral can skip the data stream by
issuing a RESTART command to the DMA channel. The DMA simply
reloads its current registers again.
DMA Enhancements (cont’d)
Handshaking Memory DMA

z Good for asynchronous FIFOs or off-chip interface controllers, between
Blackfin memory and hardware buffers
Two edge-sensitive DMA request inputs: DMAR0 and DMAR1
z Each is associated with one of the Memory DMA units: MDMA0 and
MDMA1
z Enables Memory DMA units to be synchronized by external hardware
When Handshake operation is enabled, the Memory DMA no

longer runs freely
Reduces the need of core interaction, it also increases data
throughput, since GPIO polling or GPIO-driven interrupts can be
avoided
Transfers can be done on block or word basis
ADSP-BF537 CAN Overview

What Is Controller Area Network?
CAN is a serial field bus with multi-master capabilities
All
CAN nodes are able to transmit data and several CAN
nodes can request the bus simultaneously
Automotive and Industrial Electronics
Developed by Bosch
First deployed in 1986
Up to 1 Mbps
CAN – Low Layer Specification Only
3-Wire Half-duplex Field Bus
Node 1 Node 2 Node N
Controller ADSP-BF534 ADSP-BF537

RX
RX
RX
TX
TX
TX
Transceiver Transceiver Transceiver
CAN_H
CAN_H
CAN_H
CAN_L
CAN_L
GND
GND
CAN_L
GND
Multi-master capabilities
120 Ohm resistors are used between CAN_H and CAN_L
Transceiver must be as close as possible to transmission line
Bit rate is limited by cable length and number of nodes
CAN Bit Rate vs Bus Length
Bus length (m) Max. bit rate (b/s)
40 1M
100 500k
200 250k
500 125k
6 km 10k
Full CAN vs Basic CAN Controllers
Basic CAN
z CAN controller features 1 receive buffer and 1 transmit buffer
z Software overhead
Full CAN
z CAN controller features dedicated buffers for individual messages
z Acceptance filtering done by hardware
Blackfin Provides Full CAN Implementation

z 8 dedicated transmit mailboxes
z 8 dedicated receive mailboxes
z 16 configurable transmit/receive mailboxes
z Acceptance mask and data filtering
z Automatic response to remote requests
Note: DMA is not supported on the CAN peripheral

BF537 BOOTING
SUPPORTED BOOT MODES
BMODE DESCRIPTION Pin Muxing
these pins are used by the respective
peripheral during booting
000 Bypass boot ROM -
(execute from external memory
0x2000 0000)
001 8/16-bit Parallel Flash on -
/AMS0
010 Reserved -
011 SPI Master PF11,PF12, PF13
(8/16/24-bit SPI devices)
100 SPI Slave PF11,PF12, PF13,PF14
101 TWI Master -
110 TWI Slave -
111 UART Slave PF0,PF1
Boot From 8/16-bit Prom/Flash
Physical connections:
Blackfin Blackfin
16-Bit Flash/PROM
8-Bit Flash/PROM
_______ ____
_______ ____
AMS(0) AMS
AMS(0) AMS ____
____ ___ ___
AOE OE
AOE OE
____ __ ___ ____ __ ___
AWE R/W or WR AWE R/W or WR
ADDR[N+1:1] ADDR[N:0] ADDR[N+1:1] ADDR[N:0]
DATA[7:0] DATA[7:0] DATA[15:0] DATA[15:0]
The Blackfin will boot from Asynchronous Bank 0 upon RESET which maps to
location 0x2000 0000 (DSP address).
SPI Master booting
Uses Slave Select 1 which maps to PF10

i.e., PF10 is used as chip select
On-Chip Boot Rom sets the Baud Rate Register to 133

(0x85)
Baud Rate = SCLK / (2 * SPI_BAUD)
E.g., :for a 25 MHz CLKIN: SCLK = 2*25 MHz = 50 MHz

Baud Rate = 50 MHz / (2 * 133) = 188 KHz
Support for 8-,16-, and 24-bit addressable parts

SPI Master booting
ADSP-BF537 VDDEXT
(Master SPI Device) SPI Memory
(Slave SPI Device)
10KΩ
SPICLK SPICLK
__
PF10 CS
MOSI MOSI
MISO MISO
Boot From A Host via SPI Slave Mode
(BMODE = 100)
HWAIT is used to hold off host when the Blackfin processor
is not able to consume any more data
z During the processing of Init or Zero fill blocks
z It can be any GPIO except PF11-14 Blackfin
(Slave SPI Device)
Host
(Master SPI Device)
SPICLK SPICLK
_____ _____
S_SEL SPISS
MOSI MOSI
MISO MISO
FLAG/Interrupt HWAIT
TWI Master boot (BMODE = 101)
Boot from a device whose slave address is 1010000x
z 1010: I2C
EEPROM device identifier
z 000: device “chip” select (A2, A1, A0)
z Memory device needs to be 16-bit addressable
z x: direction of transfer
ADSP-BF537 TWI DEVICE

SDA SDA
SCL SCL
A0
A1
A2
VSS
UART BOOTING (BMODE 111)
UART booting only possible thru UART0
HWAIT is used to hold off host when the Blackfin processor
is not able to consume any more data
z During the processing of Init or Zero fill blocks
z It can be any GPIO except PF0 or PF1
ADSP-BF537
UART HOST UART SLAVE
TX UART0_RX
RX UART0_TX
CTS/Interrupt HWAIT
Ethernet
ADSP-BF537 EMAC
OSI model - TCP/IP
OSI (Open OSI model TCP/IP model TCP/IP application protocols

Systems Application NFS
Application
Interconnection) Layer (7) HTTP FTP SMTP
Name
Presentation Server
• The standard Layer (6) XDRR
description or Session RPC

Layer (5)
"reference model" for
Transport Transport Transmission Control User Data Protocol
how messages Layer (4)
(TCP) Protocol TCP UDP
should be transmitted Network Internet (IP) Internet Protocol IP
Layer (3)
between any two
Data Link
points in a Layer (2)
Network Ethernet
IEEE 802.3
Token Ring DQDB
telecommunication Physical twisted optical Coaxial cable

network. Layer (1) Pair fiber
Comparison between OSI – TCP/IP model

OSI, TCP/IP, and Blackfin BF536/7
Web Server,
Layers 5, 6 and 7
Application
(Session, Presentation
and Application)
Application Protocol HTTP, FTP, Telnet etc.
Layers 3 and 4
(Network, Transport)
TCP/IP Stack lwIP, uIP, 3rd Party
Layer 2
EMAC Device Driver Driver for the ADSP-
(Data Link)
BF536/7 EMAC peripheral
provided by ADI
BF536/7 EMAC Peripheral
Layer 1
(Physical) SMSC LAN83C185,
PHY Transceiver Realtek RTL8201, etc.
TCP/IP Stack Header Structure
Application runs
DATA application layer on top of the
TCP/IP Stack
--------------------------------------------------------------------------------------------------------------------
TCP-Header DATA
UDP-Header DATA transport layer TCP/IP Stack

respectively
supports the transport
--------------------------------------------------------------------------------------------------------------------
and network layer
IP Header TCP/UDP-Header DATA network layer
--------------------------------------------------------------------------------------------------------------------
MAC Header IP Header TCP/UDP-Header
ADSP-BF536/7
DATA Trailer
data link layer Ethernet MAC
peripheral supports the
data link layer
header structure
Layer 1 - Physical
Thislayer consists of the physical and electrical interface to

the network: PHY Transceiver, 10BASE-T connector,
100BASE-TX, switches and routers
The PHY transceiver performs electrical signal conditioning

for transmission over the medium: RJ45 cable
The2-wire MII Management Interface allows layer 2 devices

such as the BF536/7 EMAC to monitor and control PHY
operation
z MII
is a 4-bit bidirectional interface running at 25 MHz
z RMII is a 2-bit bidirectional interface running at 50 MHz
100BASE-TX
MII
usestwo pairs of twisted-pair cable (Cat5 UTP or STP) in the

physical star topology (up to 500 m)
encoding
Blackfin Ethernet System Overview
ETxCLK
ETxD[3:0] TPO+
TPO-
ETxEN
MDI TPI+
Magnetics RJ45
COL
TPI-
CRS
ERxCLK
MII
ERxD[3:0]
ERxDV
ERxER
MDIO
25MHz
MDC
YINT
ADSP-BF537 PHY
Layer 2 – Data Link
This
layer enables the functional and procedural aspects of
network data transfer as well as physical layer error checking
Thereare two sub-layers: the Media Access Control (MAC)

sub-layer and the Logical Link Control (LLC) sub-layer
OnBF536/7, the MAC sub-layer is implemented as the EMAC

peripheral and the LLC sub-layer is implemented as the
EMAC device driver
Ethernet MAC (EMAC) Architecture and Features
BLACKFIN CORE
Independent DMA-driven RX and TX

channels
MII/RMII interface
10Mbit/s and 100Mbit/s operation
(Full or Half Duplex)
Automatic network monitoring
statistics
Flexible address filtering
Flexible event detection for interrupt
Validation of IP and TCP (payload)
checksums.
Remote-wakeup Ethernet frames
Network-aware system power
management
Clocking
25 MHz source for MII

PHY
PHYCLKOE
50 MHz source for RMII (PHY Clock Output Enable)
PHY*
The PHY can be clocked
with an external clock, or
the CLKBUF buffered clock
The CLK_BUF pin is
enabled by the PHYCLKOE
bit in the VR_CTL register
The default PLL
multiplier is 10x, so a 50
MHz CLKIN can violate max
CCLK frequency
Ethernet Pins on Ports H and J
PH0 until PH15 are multiplexed
Port H provides most of the
signals of the MII or alternate RMII
interface.
MII used 18 PH Pins
RMII used merely 11 PH Pins.
For MII and RMII operation, bits
of the Function Enable register
(PORTH_FER) must be set.
On PORT J, the two MII pins are
not multiplexed at all.
Layer 2 – Data Link – EMAC Device Driver
TheEMAC device driver configures and monitors the EMAC

peripheral and DMA engine to handle the flow of Ethernet
frames between memory buffers and the PHY
The device driver oversees the following core functions:

z Ethernet address and frame filtering
z Chained DMA transfers
z Interrupt management
z Collision detection
Two device driver models have been developed

corresponding to the lwIP and uIP TCP/IP stacks
Layers 3-6 – TCP/IP
Thereare currently two implementations of the TCP/IP

protocol set for BF536/7:
z lwIP – The ‘light-weight IP’ stack is a multi-threaded TCP/IP
implementation using VDK or another RTOS
Compliant with the system services model
Built into VisualDSP++ 4.0
For further information, consult www.sics.se/~adam/lwip/
z uIP – stand-alone TCP/IP implementation tailored to microcontroller
requirements
Event-based hierarchy (no RTOS required)
Very small memory footprint (stack code size ≈ 6 Kbytes)
ADSP-BF536/7 implementation available at www.blackfin.org
For further information, consult www.sics.se/~adam/uip/
Additional implementations are available from 3rd parties

z Quadros Systems RTXC Quadnet (www.quadros.com)
z Unicoi Systems FusionNet (www.unicoi.com)
z KADAK KwikNet TCP/IP Stack (www.kadak.com)
Layer 7 – Application
Thislayer contains the application protocol, high-level

software application and user interface
lwIP provides an API based on BSD sockets and runs under

VDK
uIP
allows the processor to run a single networked
application pointed to by UIP_APPCALL()
Example applications running on the ADSP-BF536/7 EZ-Kit:

z HTTP server
z HTTP client for streaming compressed audio
LwIP STACK based on VDK

lwIP stack overall structure
The stack consists of three major

components
Application
The TCP/IP library itself
An interface library to the kernel that

is being used lwIP stack library
A driver library to connect the stack to

the Ethernet controller kernel interface Ethernet driver
library library
Currently we have kernel interface
library for VDK
VDK BF537 EMAC
Currently we have driver libraries for ThreadX USB-LAN Extender
the BF537 and the USB-LAN
Folder structure
original example structure
TCP/IP STACK
Driver for ADSP-BF537 and SMSC LAN91C111
Documentation based on html
Examples for ADSP-BF533

ADSP-BF537
Host programs and Source Code for the examples

Source Code of the TCP/IP STACK
lwIP project wizard
The project wizard generates a VDK

based application which uses the
stack
It can generate an application for

either the BF537 or the USB-LAN
extender
It provides the code needed to

initialize and start the stack
operating
If DHCP is being used it will also

wait till the IP address is obtained
Configuration plugin - General tab
Displays the name of the

associated configuration file
Allows you to specify the

protocols to be supported by the
build stack
Eliminating a protocol will reduce

the size of the stack
Controls the level of statistical

data that the stack will accumulate
Configuration plugin - IP tab
Check IP Forward if you wish to
have the ability to forward IP
packets across network interfaces. If
you have only one network
interface, you should leave this box
unchecked.
Check IP options if IP options are to

be allowed. If this box is left
unchecked then packets with
unrecognized IP options are
dropped.
If IP Fragmentation is checked then

IP packets will be segmented
appropriately.
If IP Reassembly is checked then

support for re-assembling
fragmented packets is provided.
The number of network interfaces

must be specified
Configuration plugin - Network tab
If DHCP is not to be used by a

network adapter then you must
configure the appropriate setting for
the IP Address of the adapter, its
subnet mask and the IP address of
the gateway for the subnet.
The number and size of the buffers

to be supplied to the Ethernet driver
must be specified as appropriate to
the expected loading on the
adapter.
If more than one network interface

then they can be configured
separately.
Configuration plugin - TCP/UDP/ARP tab
Specify sufficient UDP ‘connection’s and
TCP connections depending on the
expected maximum number of
simultaneous UDP receives and active
connections.
Specify the maximum number of open

sockets and incoming queued
connections to be supported.
The MSS field specifies the maximum

size of TCP segment that the stack will
support.
The window size specifies the maximum

TCP receive window that the stack will
support.
The ARP table size specifies the

maximum number of address resolution
mapping entries that the stack will
maintain.
Configuration plugin - Debug tab
Specify the level of debug
checking and reporting the stack
should provide
Specify which events the stack

should provide
Configuration plugin - Memory tab
Specifies the number of pool

buffers and the size of each pool
buffer
Each frame is stored in a linked

list of pool buffers
Setting the pool buffer size to low

will increase processor overheads
Setting the pool buffer size to high

will increase memory overheads
Specifythe total size of memory

heap that the stack can utilise for
non pool buffer memory requests
Blackfin Processor Product Roadmap
Advanced Technology
In Development
Consumer Media BF56x

4xPPI, 4xSerial Ports, 10/100 Ethernet MAC, PCI, HPI
BF561-750
756 MHz BF56x
2xPPI, 32-bit EBIU
4xSerial Ports 2xPPI, 4xSerial Ports, USB2.0
BF561 BF53x
500–600 MHz
2xPPI, 32-bit EBIU PPI, 3xSerial Ports, USB2.0
4xSerial Ports
Automotive, Industrial and Instrumentation BF539

PPI, 10xSerial Ports, I2C, CAN
BF533-750
756 MHz
Performance
BF533 PPI, 16-bit EBIU BF536/537

4xSerial Ports PPI, 5xSerial Ports, I2C, CAN, 10/100 Ethernet MAC
BF532
400-600 MHz
BF531 PPI, 16-bit EBIU BF534
4xSerial Ports
PPI, 5xSerial Ports, I2C, CAN, 48xGPIO
Mobile Handsets, Smart Phones and PDAs
msp500 msp5xx
BF535
SoftFone SoftFone
PCI, USB
4xTimers, Watchdog Timer GSM/GPRS/EDGE; Multimode, multimedia
16xGPIO, RTC Full 4-slot receive; Low standy power wireless handsets;
Low standy power
PRESENT FUTURE
Introduction to VisualDSP++
VisualDSP++ 4.0
VisualDSP++ is an integrated development environment that

enables efficient management of projects.
z Key Features Include:
Editing
Building
z Compiler, assembler, linker

Debugging
z Simulation, Emulation, EZ-KIT
z Run, Step, Halt
z Breakpoints, Watchpoints
z Advanced plotting and profiling capabilities
z Pipeline and cache viewers

VisualDSP++
What comes with VisualDSP++?

z Integrated Development and Debugger Environment (IDDE), C/C++
Compiler, Assembler, Linker, VDK, Emulation and Simulation Support,
On-line help and documentation
Part #: VDSP-BLKFN-FULL
Floating License Part #: VDSP-BLKFN-PCFLOAT
VisualDSP++is a common development environment for all

ADI processor families
z Blackfin
ADSP-BF5xx
z TigerSharc
ADSP-TSxxx
z Sharc
ADSP-21xxx
z Each processor family requires a separate license

Features of VisualDSP++ 4.0
Integrated Development and Debugger Environment (IDDE)
z Multiple workspaces, projects, project groups
Project Wizard
z Create/configure a DSP project
Highlevel language support including C and C++
Expert Linker
z Graphical support for managing linker description files
z Code profiling support
Easy to use Online Help
BTC (Background Telemetry Channel) Support
z Data Streaming and Logging
Easy to test and verify applications with scripts (TCL, VB, Java)
VisualDSP++ RTOS/Kernel/Scheduler (VDK)
Integrated Source Code Control
Device Drivers and System Services
Software Development Flow
Linker
Description File
Code Generation .LDF
Generate
Assembly Assembler
Source .DOJ
(.ASM)
Linker
and / or .DXE
System
Generate
C/C++ C/C++ Compiler
Verification
Source .S
(.C/CPP)
.DXE
Hardware Evaluation
.DXE EZ-Kit Lite
VisualDSP++
Software Simulator
Verification .DXE Target Verification

ICE
NO YES
Working
Code? .DXE ROM Production
LOADER
.LDR
PROM
Burner
Invoking the Software Tools
• Software tools may be configured and called by the IDDE
− Software tools are configured via property pages
− The IDDE calls the software tools it needs to complete the build
− GUI front end to a command line ‘make’ utility
• Software tools can be invoked from a Command line
− C Compiler: ccblkfn sourcefile -switch [-switch...]
− Assembler: easmblkfn sourcefile -switch [-switch...]
− Linker: linker object [object…] -switch [-switch…]
− Loader: elfloader executable -switch [-switches...]
• For the complete list of switches see the appropriate tools manual
Integrated Development and Debugger
Environment (IDDE) Features
• IDDE allows one to manage the project build
• The user configures the project and the development tools via
property pages
• Project Property pages configure the project
– Project Property Page
– General Property Page
– Pre Build Property Page
– Post Build Property Page
• Development Tools Property Pages are used to configure the
development tools
– Assembler Property Page
– Compiler Property Page
– Linker Property Page
– Loader Property Page
Project Development
• Create a project
– All development in
VisualDSP++ occurs
within a project.
– The project file (.DPJ)
stores your program’s
build information:
source files list and
development tools
option settings
– A project group file
(.DPG) contains a list
of projects that make
up an application (eg
ADSP-BF561 dual core
application)
Project Property Page
• Configure project
options
– Define the target
processor and set up
your project options (or
accept default settings)
before adding files to
the project.
– The Project Options
dialog box provides
access to project
options, which enable
the corresponding build
tools to process the
project’s files correctly
Enable building for a specific revision of silicon
- No need to specify ‘-si-revision’ switch
- Automatic will attempt to determine revision of the attached target
- or specify a specific rev level (eg 0.3)
Property Pages
C/C++ Compiler Property Page
Assembler Property Page

Property Pages
Linker Property Page
Loader Property Page

Property Pages
General Property Page
Pre Build Property Page
Post Build Property Page

Selecting VisualDSP++ Sessions
• Sessions define Debug Environments

• Select Sessions pull down menu
– Choose Sessions List
– Select Session to activate
• Define New Session from Session List
– Select New Session
– Configure session as required e.g.
Debug target : ADSP-BF53x Family Simulator

Platform : ADSP-BF53x Single Processor Simulator
Session name : ADSP-BF533 ADSP-BF53x Single
Processor Simulator
• Click OK
– Session name will appear in Session
List
• Click Activate
– IDDE session will open
Debug Features
Single Step
Run
Halt
Set Breakpoints
Register Viewing
Memory
z Viewing
z Plotting
z Dump/Fill
Code Optimization Utilities
z Profiling
z Pipeline Viewer
z Cache Viewer
Compiled Simulation
High Level Language debug support
z Mixed mode
Online Help
Fully searchable and indexed online help
Includes quick overviews on using VisualDSP++ and all of its features.
Excellent supplement to the manual for things that are better represented
visually such as what various plot windows should look like.
Customizable by using the “Favorites” window

On Line Help Example

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The World Leader in High Performance Signal Processing Solutions

Blackfin can perform all of

The Micro Signal Architecture was crafted with the

 Blackfin IS NOT just a DSP with an enhanced instruction set

 Blackfin IS an architecture that is optimized to perform equally well

 BLACKfinis a high performance dual MAC DSP with features

 Single Processor target for software development

600 MHz, 1.2V 500 MHz, 1.2V

200 MHz, 1.2V Power Savings

500 MHz, 1.0V

Self contained, software programmable power management system that

Supervisor & Application Code

System Code and Event Handlers

 Real Time Operating Systems

 Accelerated Technology Nucleus - Now

 Express Logic ThreadX - Now

 Unicoi Fusion Net – Now

Blackfin  Express Logic Net-X – Now

Performance Core LD0 32

16 DMA Core Bus (DCB)

ETHERNET UART0/1 1KB internal Programmable

 Fixed point DSP Math

 Modified Harvard Memory Architecture

Address Arithmetic Unit  Two 16-bit Multipliers

ASTAT Arithmetic Status LC0 Loop Counter

RETI Interrupt Return LC1

 Support for three data lengths.

 LittleEndian data format.

2 ALUs exist in Blackfin MSA core

R2 Dual ALU / MAC

 Blackfin supports 2 multipliers

 Multiplier overflow status bits exist in ASTAT

 Indexed Addressing with index  Indexed

 Autoincrement and Auto  DAGand Pointer register

The Program Sequencer controls all program flow

 Contains an 10-stage instruction pipeline

 Branch target address calculation takes place in the AC stage

 Conditional Branches are executed based on the CC bit.

Prediction Not Taken Taken (BP)

Outcome Taken Not taken Taken Not taken

Latency 8 cycles 0 cycles 4 cycles 8 cycle

 Supporttwo zero-overhead nested loops

 Registers can also be set manually

 IMASK Register – bits 0-15

Hardware Error 5 IVHW

General Purpose 8 8 IVG8

General Purpose 14 14 IVG14

 Configurable Memory ? Why ?

 16KB SRAM • 16 KB cache

 Two 16KB super-banks

Multi-ported data 4KB 4KB

• When Used as Cache • When Used as SRAM

 Memory Management MMU Property

CLKIN can be driven from

 Generates core voltage

19 Address 1M Byte Asynchronous

512M Byte Synchronous

 EBIU – External Bus Interface Unit

 One memory region is

 Four ASYNC banks

 Bidirectional, half-duplex interface

 Programmable bus width (8 – 16 bits)

 Includes three frame syncs to control the interface timing

Blackfin IS NOT just a DSP with an enhanced instruction set

Blackfin IS an architecture that is optimized to perform equally well

BLACKfinis a high performance dual MAC DSP with features

Single Processor target for software development

Real Time Operating Systems

Accelerated Technology Nucleus - Now

Express Logic ThreadX - Now

Unicoi Fusion Net – Now

Blackfin Express Logic Net-X – Now

Fixed point DSP Math

Modified Harvard Memory Architecture

Address Arithmetic Unit Two 16-bit Multipliers

Support for three data lengths.

LittleEndian data format.

2 ALUs exist in Blackfin MSA core

Blackfin supports 2 multipliers

Multiplier overflow status bits exist in ASTAT

Indexed Addressing with index Indexed

Autoincrement and Auto DAGand Pointer register

Contains an 10-stage instruction pipeline

Branch target address calculation takes place in the AC stage

Conditional Branches are executed based on the CC bit.

Supporttwo zero-overhead nested loops

Registers can also be set manually

IMASK Register – bits 0-15

Configurable Memory ? Why ?

16KB SRAM • 16 KB cache

Two 16KB super-banks

Memory Management MMU Property

Generates core voltage

EBIU – External Bus Interface Unit

One memory region is

Four ASYNC banks

Bidirectional, half-duplex interface

Programmable bus width (8 – 16 bits)

Includes three frame syncs to control the interface timing

Used in conjunction with a DMA channel

Two synchronous serial ports

Full duplex synchronous

Master and Slave mode PFx

Use to generate interrupts at multiples of CCLK rate

Generating an event when the timer expires.

The event can be programmed to be:

Clocked by the system clock (SCLK).

Must be periodically serviced by software

Typically used to implement real-time watch or “life counter”

Eight Identical Timers Can Be Configured In 3 Modes

Fully compliant to the Philips I2C bus protocol

General call address support

Supports Master and Slave operation

4 more DMA channels

Handshaking Memory DMA

When Handshake operation is enabled, the Memory DMA no

CAN is a serial field bus with multi-master capabilities

Automotive and Industrial Electronics

First deployed in 1986

Blackfin Provides Full CAN Implementation

Uses Slave Select 1 which maps to PF10

On-Chip Boot Rom sets the Baud Rate Register to 133

E.g., :for a 25 MHz CLKIN: SCLK = 2*25 MHz = 50 MHz

Support for 8-,16-, and 24-bit addressable parts

Thislayer consists of the physical and electrical interface to

The PHY transceiver performs electrical signal conditioning

The2-wire MII Management Interface allows layer 2 devices

usestwo pairs of twisted-pair cable (Cat5 UTP or STP) in the

Thereare two sub-layers: the Media Access Control (MAC)

OnBF536/7, the MAC sub-layer is implemented as the EMAC

Independent DMA-driven RX and TX

25 MHz source for MII

TheEMAC device driver configures and monitors the EMAC

The device driver oversees the following core functions:

Two device driver models have been developed

Thereare currently two implementations of the TCP/IP

Additional implementations are available from 3rd parties

Thislayer contains the application protocol, high-level

lwIP provides an API based on BSD sockets and runs under

Example applications running on the ADSP-BF536/7 EZ-Kit:

The stack consists of three major

An interface library to the kernel that

A driver library to connect the stack to