Analog Devices Incorporated Blackfin

Analog Devices Incorporated
Blackfin
CS 433
Prof. Luddy Harrison
Processor Presentation Series
CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 1

Note on this presentation series
z These slide presentations were prepared by

students of CS433 at the University of Illinois at
Urbana-Champaign
z All the drawings and figures in these slides were
drawn by the students. Some drawings are based
on figures in the manufacturer’s documentation for
the processor, but none are electronic copies of
such drawings
z You are free to use these slides provided that you
leave the credits and copyright notices intact

Presentation Outline
z Introduction
z Architecture Overview
z Processor Core
z Signal Chain
z Instruction Set
z Blackfin Platforms
z Targeted Application
z References

Introduction
z New type of 16-32-bit embedded processor
z Combine RISC MCU and DSP functionalities
z Specifically designed for the computational
demands and power constraints for embedded
audio, video and communications applications
z Micro Signal Architecture (MSA) based 32-bit RISC-
like instruction set and dual 16-bit multiply
accumulate (MAC) signal processing and 8-bit video
processing
z Performs equally well in both signal processing and
control processing applications

Introduction
z Advanced memory management that supports
memory-protected and non memory-protected
embedded operating systems
z Supported by ADI's CROSSCORE development tool
chain, which includes the VisualDSP++ Integrated
Development and Debugging Environment (IDDE),
and by Green Hills' MULTI IDE tool suite

Introduction
z The Blackfin Family of Processors
z ADSP-BF535 was the first released
z followed in March 2003 by three pin-compatible
devices, the ADSP-BF531, ADSP-BF532, and
ADSP-BF533
z In January of 2005, Analog Devices introduced
three Blackfin processors with embedded
connectivity: ADSP-BF536, ADSP-BF537, and
ADSP-BF534
z dual-core symmetric multiprocessor, the ADSP-
BF561
Blackfin Processor Specifications
Feature ADSP ADSP ADSP ADSP ADSP ADSP ADSP ADSP
- - - - - - - -
BF535 BF531 BF532 BF533 BF561 BF536 BF537 BF534
Max Clock 350 400 400 750 600 400 600 500
Speed
(MHz)
Memory 308 52 84 148 328 100 132 132
(Kbytes)
External 32- 16- 16- 16- 32- 16- 16- 16-

Memory
(bus)
bit bit bit bit bit bit bit bit
Parallel No Yes Yes Yes Yes Yes Yes Yes
Peripheral
Interface
(2)
Feature ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP ADSP-
BF535 BF531 BF532 BF533 BF561 BF536 - BF534
BF537
UARTs, Yes Yes Yes Yes Yes Yes Yes Yes
Timers
SPORTs, Yes Yes Yes Yes Yes Yes Yes Yes

SPI
Programma Yes Yes Yes Yes Yes Yes Yes Yes

ble Flags
TWI- No No No No No Yes Yes Yes

Compatible

Feature ADSP ADSP ADSP ADSP ADSP ADSP ADSP ADSP
- - - - - - - -
Watchdog Yes Yes Yes Yes Yes Yes Yes Yes
Timer
RTC Yes Yes Yes Yes No Yes Yes Yes
Core 1-1.6 0.8- 0.8- 0.8- 0.8- 0.8- 0.8- 0.8-

Voltage (V)
1.2 1.2 1.4 1.2 1.2 1.2 1.2
Core No Yes Yes Yes Yes Yes Yes Yes
Voltage
Regulation

Feature ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP- ADSP-
Package Size 260 160 160 160 256 182 182 182
PBGA Mini- Mini- Mini- Mini- Mini- Mini- Mini-
BGA, BGA, BGA, BGA, BGA, BGA, BGA,
176 176 169 297 208 208 208
LQFP, LQFP, Sparse PBGA Sparse Sparse Sparse
169 169 PBGA Mini- Mini- Mini-
Sparse Sparse BGA BGA BGA
PBGA PBGA
Lead-Free No Yes Yes Yes Yes Yes Yes Yes

Package
Option

Recommended Operating
Conditions
Parameter Min Nor Max Unit
VDDINT Internal Supply Voltage (ADSP- 0.8 1.2 1.32 V

BF531 and ADSP-BF532)
VDDINT Internal Supply Voltage (ADSP- 0.8. 1.26 1.32 V
BF533)
VDDENT External Supply Voltage 2.25 2.5 3.6 V
VDDRTC Real-Time Clock Power Supply 2.25 3.6 V

Voltage
VIH High Level Input Voltage1, 2 2.0 3.6 V
@VDDEXT =maximum
VIHCLKIN High Level Input Voltage3 @ 2.2 3.6 V
VDDEXT =maximum
VIL Low Level Input Voltage2, 4 @ -0.3 0.6 V
VDDEXT =minimum
Electrical Characteristics
Parameters Test Condition Min Max Unit

VOH High Level Output Voltage @ VDDEXT = 3.0V, IOH = 2.4 V
–0.5 mA
VOL Low Level Output Voltage @ VDDEXT = 3.0V, IOL = 0.4 V
2.0 mA
IIH High Level Input Current @ VDDEXT = maximum, 10 uA
VIN = VDD maximum
IIHP High Level Input Current JTAG @ VDDEXT = maximum, 20 uA
VIN = VDD maximum
IIL Low Level Input Current @ VDDEXT = maximum, 10 uA
VIN = 0 V
IOZH Three-State Leakage Current @ VDDEXT = maximum, 10 uA
VIN = VDD maximum
IOZL Three-State Leakage Current @ VDDEXT = maximum, 10 uA

VIN = 0 V
IIN Input Capacitance fIN = 1 MHz, TAMBIENT = 8 pF
25°C, VIN = 2.5 V

Pin Descriptions
Pin Name I/O Function Driver Type
ADDR19–1 O Address Bus for Async/Sync Access A2
DATA15–0 I/O Data Bus for Async/Sync Access A2
ABE1–0/SDQM1– O Byte Enables/Data Masks for A2
0 Async/Sync Access
BR3 I Bus Request A2
BG O Bus Grant A2
BGH O Bus Grant Hang A2
AMS3–0 O Bank Select A2
ARDY I Hardware Ready Control
AOE O Output Enable A2

Pin Descriptions
Pin Name I/O Function Driver

Type
ARE O Read Enable A2
AWE O Write Enable A2
SRAS O Row Address Strobe A2
SCAS O Column Address Strobe A2
SWE O Write Enable A2
SCKE O Clock Enable A2
CLKOUT O Clock Output B4
SA10 O A10 Pin A2
SMS O Bank Select A2
Pin Descriptions
TMR0 I/O Timer 0 C5
TMR1/PPI_FS1 I/O Timer 1/PPI Frame Sync1 C5
TMR2/PPI_FS2 I/O Timer 2/PPI Frame Sync2 C5
PF0/SPISS I/O Programmable Flag 0/SPI Slave C5
Select Input
PF1/SPISEL1/TM I/O Programmable Flag 1/SPI Slave C5
RCLK Select Enable 1/External Timer
Reference
PF2/SPISEL2 I/O Programmable Flag 2/SPI Slave C5
Select Enable 2
PF3/SPISEL3/PPI I/O Programmable Flag 3/SPI Slave C5
_FS3 Select Enable 3/PPI Frame Sync 3

Pin Descriptions
15 Select Enable 4 / PPI 15
PF8/PPI11 I/O Programmable Flag 8/PPI 11 C5

Pin Descriptions
PPI3–0 I/O PPI3–0 C5
PPI_CLK I PPI Clock C5
RSCLK0 I/O SPORT0 Receive Serial Clock D6
RFS0 I/O SPORT0 Receive Frame Sync C5
DR0PRI I SPORT0 Receive Data Primary
Pin Descriptions
DR0SEC I SPORT0 Receive Data Secondary
TSCLK0 I/O SPORT0 Transmit Serial Clock D6
TFS0 I/O SPORT0 Transmit Frame Sync C5
DT0PRI O SPORT0 Transmit Data Primary C5
DT0SEC O SPORT0 Transmit Data Secondary C5
RSCLK1 I/O SPORT1 Receive Serial Clock D6
RFS1 I/O SPORT1 Receive Frame Sync C5
DR1PRI I SPORT1 Receive Data Primary
DR1SEC I SPORT1 Receive Data Secondary
TSCLK1 I/O SPORT1 Transmit Serial Clock D6

Pin Descriptions
TFS1 I/O SPORT1 Transmit Frame Sync C5
DT1PRI O SPORT1 Transmit Data Primary C5
DT1SEC O SPORT1 Transmit Data Secondary C5
MOSI I/O Master Out Slave In C5
MISO I/O Master In Slave Out C5
SCK I/O SPI Clock D6
RX I UART Receive
TX O UART Transmit C5
RTXI I RTC Crystal Input
RTXO O RTC Crystal Output
Pin Descriptions
TCK I JTAG Clock
TDO O JTAG Serial Data Out C5
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST I JTAG Reset
EMU O Emulation Output C5
CLKIN I Clock/Crystal Input
XTAL O Crystal Output
RESET I Reset
NMI I Nonmaskable Interrupt

Pin Descriptions
Pin Name I/O Function Driver

Type
BMODE1–0 I Boot Mode Strap
VROUT1–0 O External FET Drive
VDDEXT P I/O Power Supply
VDDINT P Core Power Supply
VDDRTC P Real-Time Clock Power Supply
GND G External Ground

Introduction
Packaging
z Ball Grid Array (BGA) package
z Improved electrical performance due to shorter distance
between the chip and the solder balls
z Improved thermal performance by use of thermal vias, or
heat dissipation through power and ground planes
incorporated in the substrate
z Occupies less board real estate (less package area per I/O)
z Significantly reduced handling-related lead damages due
to use of solder balls instead of metal leads. This also
reduces rework prior to board level attachment
z When reflow attached to boards, the solder balls self align
leading to higher manufacturing yields

Introduction
Packaging
z MiniBGA Package
z 10x10 mm MiniBGA, approximately 50% smaller
than most other DSPs
z 144-ball chip array package (CAP) footprint, just
one square centimeter
z Height is just 1.25 millimeters

Architecture Overview
Single Core BlackFin 16/32 bit Processor
High Speed IO
System Control Block
16-bit
Voltage Event Watchdog Memory Real Time
JTAG PLL External
Regulator Controller Timer DMA Clock Bus
Interface
Blackfin Core
80KB 64KB
INST DATA
SRAM/CACHE
L1 Memory
System Interface Unit
PPI/GPIO
Timer UART Peripheral

SPORT0 SPORT1 SPI
(3) IrDA Blocks

z High Performance Processor Core
z 10-stage RISC MCU/DSP pipeline
z mixed 16-/32-bit Instruction Set Architecture
z fully SIMD compliant
z instructions for accelerated video and image processing
z full signal processing / analytical capabilities
z efficient RISC MCU control tasking capabilities
z High Bandwidth DMA Capability
z multiple, independent DMA controllers
z automated data transfers with minimal overhead from the
processor core

z Video Instructions
z native support for 8-bit data
z instructions specifically defined to enhance performance in
video processing applications
z allows OEMs to adapt to evolving standards and new
functional requirements without hardware change
z Efficient Control Processing
z powerful and flexible hierarchical memory architecture
z superior code density
z variety of microcontroller-style peripherals
z great deal of design flexibility while minimizing end system
costs

z Hierarchical Memory
L1 Instruction L2 Data &

SRAM & Cache Instruction
SRAM
BlackFin (some model)
Processor L1 Data
SRAM & Cache
DMA
Scratchpad SRAM

z Hierarchical Memory
z both Level 1 (L1) and Level 2 (L2) memory blocks
z L1 connected directly to the processor core, runs at full
system clock speed
z L2 offers slightly reduced performance, but still faster than
off-chip memory
z L1 memory can be configured as SRAM, cache, or a
combination of both
z support a full Real Time Operating System with an isolated
and secure environment for robust systems and
applications

z Addressing
z two address generation units that can each generate an
independent address in each cycle
z supports a variety of addressing modes, including: register
indirect, register-indirect with post increment or post-
decrement, register indirect indexed addressing with a
short or long immediate offset, register-indirect addressing
with pre-decrement for stack pushes, and register-indirect
addressing with post-increment for stack pops.

z Addressing
z can also perform some addition, subtraction, and shifting
operations on the address registers
z Pipelines
z first-generation ADSP-BF535 pipeline has eight stages
z second-generation ADSP-BF5xx pipeline has ten stages
z feature fully interlocked pipelines
z static branch prediction for all conditional branches with
programmer (or compiler) specify the prediction for each
branch

z Pipelines
z instructions generally execute in one cycle in the absence
of memory access related delays and pipeline stalls
z jump, call, and most return instructions require four or more
cycles
z Instruction Set
z algebraic syntax highly orthogonal
z uses both 16- and 32-bit instructions
z arithmetic instructions can take operands from the data
registers, the pointer registers, the accumulators, or
immediate operands
z also support SIMD operations

z Instruction Set
z supports multi-length instruction encoding
z control-type instructions are encoded as compact 16-bit
words
z mathematically intensive signal processing instructions
encoded as 32-bit values
z intermix and link 16-bit control instructions with 32-bit
signal processing instructions into 64-bit groups to
maximize memory packing
z code density comparable to industry-leading RISC
processors.

z Dynamic Power Management
z gated clock core design that selectively powers down
functional units on an instruction-by-instruction basis
z support multiple power-down modes for periods where little
or no CPU activity is required
z support a self contained dynamic power management
scheme whereby the operating frequency AND voltage can
be independently manipulated to meet the performance
requirements of the algorithm currently being executed
z Peripherals
z DMA controllers
z general-purpose I/O pins
z real-time clocks

z Peripherals
z timers with pulse width modulation (PWM) and pulse
measurement capability
z watchdog timer
z serial ports
z UART ports
z Serial Peripheral Interface (SPI) ports
z Easy to Use
z utilized in many applications previously requiring both a
high performance signal processor and a separate efficient
control processor

z Major Benefits
z High-performance signal processing and efficient control
processing capability enabling a variety of new markets
and applications
z Dynamic Power Management (DPM) enabling the system
designer to specifically tailor the device power consumption
profile to the end system requirements
z Easy to use mixed 16-/32-bit Instruction Set Architecture
and development tool suite ensuring that product
development time is minimized
z Low cost, priced starting at $4.95/each in 10K unit

Dual Core BlackFin 16/32 bit Processor
JTAG Test
IRQ CONTROL IRQ CONTROL Emulation
WATCHDOG WATCHDOG
TIMER Blackfin Core Blackfin Core TIMER
UART IRDA
VOLTAGE
REGULATOR
SPI
L1 L1 L1 L1 L2
Instruction MMU Data Instruction MMU Data SRAM SPORT0
Memory Memory Memory Memory 128 KB
SPORT1
IMDMA
Core System /Bus Interface Controller
GPIO
DMA
Controller
TIMERS
Boot DMA
ROM Controller
External Port
Flash/SDRAM
Control PPI0 PPI1

Dual Core BlackFin 16/32 bit Processor
z Dual-Core Processors Add Flexibility

z employs discrete and often different tasks that run
on each of the cores
z one core runs the operating system or kernel, the
other core is dedicated to the application’s high-
intensity processing functions
z ability to segment these types of functions allows
a parallel design process, eliminating critical path
dependencies in the project

Processor Core
SP
FP I3 L3 B3 M3
P5 I2 L2 B2 M2 DAG0 DAG1
P4 I1 L1 B1 M1
P3 I0 L0 B0 M0
P2 SEQUENCER
P1
P0
ALIGN
DECODE
R7 16 16
R6 8 8 8 8
LOOP BUFFER
R5
R4
R3 CONTROL UNIT
R2 Barrel
R1 40 40
Shifter
R0
ACC0 ACC1
DATA ARITHMETIC UNIT

Processor Core
z General-purpose register files
z Data register file
z Data types include 8-, 16-, or 32-bit signed or
unsigned integer and 16- or 32-bit signed
fractional
z 32-bit reads AND two 32-bit writes
z Address register file
z Stack pointer
z Frame pointer

Processor Core
z Data arithmetic unit
z Two 16-bit MACs
z Two 40-bit ALUs
z Four 8-bit video ALUs
z Single barrel shifter

Processor Core
z Address arithmetic unit
z Memory fetches
z Index, length, base, and modify registers
z Circular buffering

Processor Core
z Program sequencer unit
z Conditional jumps and subroutine calls
z Nested zero-overhead looping
z Code density

Signal Chain
Telematics
Power Management
GPS Bluetooth
RF RF
GSM INTERFACE
GYRO ADC Processor

DIGIAL OUTPUT
MIC VOICEBAND
AMP STEREO Power
ADC ADC/DAC Amplifier
AMP ADC
BOOT
SDRAM
FLASH

Signal Chain
Navigation/GPS
Power
Management
GPS GSM/CDMA
RF Wireless
Phone
Processor Module
GYRO ADC DIGITAL OUTPUT
BOOT
FLASH

Signal Chain
Car Audio Amplifier
INPUT TO MULTICHANNEL Power

CODECS CODECS Management
Stereo &
Headphone
Multi-channel
Amplifier
DACs
Processor
CD Audio DIGITAL OUTPUT

Drive
Boot
Flash

g
Hands Free/Voice Activated
Control
POWER
MANAGEMENT
MIC VOICEBAND
DIGITAL OUTPUT
AMP ADC
PROCESSOR
MIC VOICEBAND VOICEBAND POWER

AMP ADC DAC AMPLIFIER
ANALOG OUTPUT
BOOT
FLASH

Signal Chain
Digital Camera
Video Gamma Correction
AMP LCD
Encoding Reference
Memory
Camera Int/Ext
CCD CCD/AFE
Processor/
Sensor Processor
Controller
USB to PC/PCMCIA
Video
Audio Compression Memory
Audio
Microphone AMP Codec
Audio
Speaker AMP
System V-Ref Power Signal Thermal

Digital Pot Interface Supervisory
Timing Management Control Management

Signal Chain
Camcorder
Mic Audio Audio Audio Audio
In AMP Codec AMP Out
Zoom, Focus, Gamma

AMP LCD
Motor Control Correction
CCD CCD AFE Application Memory Int/Ext

Sensor Processor Processor
Video Output to PC/PCMCIA

Codec
Video Video Video

Compression Decompression AMP TV
Encoder out
Thermal
System V-Ref Power Signal
Digital Pot Interface Supervisory Management
Timing Management Control

Signal Chain
Video Capture Board
Video Video Compress Video Decompress

Camera AMP Codec/ Codec/
Decoder
Processor Processor
AMP Display
Application Application
Camera AMP Video
Processor Processor
Switch
AMP Display
Camera AMP Storage

Board Video
Processor Medium
Camera AMP
Thermal

Signal Chain
Image/Video – Document Scanner
CCD CCD AFE

Sensor Processor
Control AMP LCD GAMMA

Application
Input Device Correction
Processor
Display
Sensor Digitizer
Motor
Motor
Control USB to
PCMCIA
Thermal

Instruction Set
Description
z Seamlessly integrated DSP/CPU features are

optimized for both 8-bit and 16-bit operations.
z A multi-issue load/store modified Harvard
architecture, which supports two 16-bit MAC or four
8-bit ALU + two load/store + two pointer updates per
cycle.
z All registers, I/O, and memory are mapped into a
unified 4G byte memory space, providing a
simplified programming model.

Instruction Set
Description
z Microcontroller features, such as arbitrary bit and

bit-field manipulation, insertion, and extraction;
integer operations on 8-, 16-, and 32-bit data types;
and separate user and supervisor stack pointers.
z Code density enhancements, which include
intermixing of 16- and 32-bit instructions (no mode
switching, no code segregation). Frequently used
instructions are encoded in 16 bits.

Program Flow Control
z Program Flow Control

z Jump
z JUMP (destination_indirect)
z JUMP (PC + offset)
z JUMP offset
z JUMP.S offset
z JUMP.L offset
z IF CC JUMP
z IF CC JUMP destination
z IF !CC JUMP destination


z Call
z CALL (destination_indirect)
z CALL (PC + offset)
z CALL offset
z RTS, RTI, RTX, RTN, RTE (Return)
z RTS ; // Return from Subroutine (a)
z RTI ; // Return from Interrupt (a)
z RTX ; // Return from Exception (a)
z RTN ; // Return from NMI (a)
z RTE ; // Return from Emulation (a)

z LSETUP, LOOP
z There are two forms of this instruction. The first is:
LOOP loop_name loop_counter
LOOP_BEGIN loop_name
LOOP_END loop_name
z The second form is:
LSETUP (Begin_Loop, End_Loop)Loop_Counter

Load / Store
z Load / Store
z Load Immediate
z register = constant
z A1 = A0 = 0
z Load Pointer Register
z P-register = [ indirect_address ]
z Load Data Register
z D-register = [ indirect_address ]
z Load Half-Word – Zero-Extended
z D-register = W [ indirect_address ] (Z)

Load / Store
z Load / Store
z Load Half-Word – Sign-Extended
z D-register = W [ indirect_address ] (X)
z Load High Data Register Half
z Dreg_hi = W [ indirect_address ]
z Load Low Data Register Half
z Dreg_lo = W [ indirect_address ]
z Load Low Data Register Half
z Dreg_lo = W [ indirect_address ]

Load / Store
z Load / Store
z Load Byte – Sign-Extended
z D-register = B [ indirect_address ] (X)
z Store Pointer Register
z [ indirect_address ] = P-register
z Store Data Register
z [ indirect_address ] = D-register
z Store High Data Register Half
z W [ indirect_address ] = Dreg_hi

Load / Store
z Load / Store
z Store Low Data Register Half
z W [ indirect_address ] = Dreg_lo
z W [ indirect_address ] = D-register
z Store Byte
z B [ indirect_address ] = D-register
z Move
z Move Register
z dest_reg = src_reg

Instruction Set
Move
z Move
z Move Conditional
z IF CC dest_reg = src_reg
z IF ! CC dest_reg = src_reg
z Move Half to Full Word – Zero-Extended
z dest_reg = src_reg (Z)
z Move Half to Full Word – Sign-Extended
z dest_reg = src_reg (X)

Instruction Set
Move
z Move
z Move Register Half
z dest_reg_half = src_reg_half
z dest_reg_half = accumulator (opt_mode)
z Move Byte – Zero-Extended
z dest_reg = src_reg_byte (Z)
z Move Byte – Sign-Extended
z dest_reg = src_reg_byte (X)

Instruction Set
Stack Control
z Stack Control
z --SP (Push)
z [ -- SP ] = src_reg
z --SP (Push Multiple)
z [ -- SP ] = (src_reg_range)
z SP++ (Pop)
z dest_reg = [ SP ++ ]
z SP++ (Pop Multiple)
z (dest_reg_range) = [ SP ++ ]

Instruction Set
Control Code Bit Management
z Stack Control
z LINK, UNLINK
z LINK uimm18m4 ; /* allocate a stack frame of specified size (b) */
z UNLINK ; /* de-allocate the stack frame (b)*/
z Control Code Bit Management
z Compare Data Register
z CC = operand_1 == operand_2
z CC = operand_1 < operand_2
z CC = operand_1 <= operand_2
z CC = operand_1 < operand_2 (IU)
z CC = operand_1 <= operand_2 (IU)

Instruction Set

z Compare Pointer
z CC = operand_1 == operand_2
z CC = operand_1 < operand_2
z CC = operand_1 <= operand_2
z CC = operand_1 < operand_2 (IU)
z CC = operand_1 <= operand_2 (IU)
z Compare Accumulator
z CC = A0 == A1
z CC = A0 < A1
z CC = A0 <= A1
Instruction Set

z Move CC
z dest = CC
z dest |= CC
z dest &= CC
z dest ^= CC
z CC = source
z CC |= source
z CC &= source
z CC ^= source

Instruction Set
Logical Operations

z Negate CC
z CC = ! CC
z Logical Operations
z & (AND)
z dest_reg = src_reg_0 & src_reg_1
z ~ (NOT One’s Complement)
z dest_reg = ~ src_reg

Instruction Set
Logical Operations
z Logical Operations
z | (OR)
z dest_reg = src_reg_0 | src_reg_1
z ^ (Exclusive-OR)
z dest_reg = src_reg_0 ^ src_reg_1
z BXORSHIFT, BXOR
z dest_reg = CC = BXORSHIFT ( A0, src_reg )
z dest_reg = CC = BXOR ( A0, src_reg )
z dest_reg = CC = BXOR ( A0, A1, CC )
z A0 = BXORSHIFT ( A0, A1, CC )

Instruction Set
Bit Operations
z Bit Operations
z BITCLR
z BITCLR ( register, bit_position )
z BITSET
z BITSET ( register, bit_position )
z BITTGL
z BITTGL ( register, bit_position )
z BITTST
z CC = BITTST ( register, bit_position )
z CC = ! BITTST ( register, bit_position )

Instruction Set
Bit Operations
z Bit Operations
z DEPOSIT
z dest_reg = DEPOSIT ( backgnd_reg, foregnd_reg )
z dest_reg = DEPOSIT ( backgnd_reg, foregnd_reg ) (X)
z EXTRACT
z dest_reg = EXTRACT ( scene_reg, pattern_reg ) (Z)
z dest_reg = EXTRACT ( scene_reg, pattern_reg ) (X)
z BITMUX
z BITMUX ( source_1, source_0, A0 ) (ASR)
z BITMUX ( source_1, source_0, A0 ) (ASL)

Instruction Set
Shift / Rotate Operations
z Bit Operatoins
z ONES (One’s Population Count)
z dest_reg = ONES src_reg
z Shift / Rotate Operations
z Add with Shift
z dest_pntr = (dest_pntr + src_reg) << 1
z dest_pntr = (dest_pntr + src_reg) << 2
z dest_reg = (dest_reg + src_reg) << 1
z dest_reg = (dest_reg + src_reg) << 2

Instruction Set

z Shift with Add
z dest_pntr = adder_pntr + ( src_pntr << 1 )
z dest_pntr = adder_pntr + ( src_pntr << 2 )
z Arithmetic Shift
z dest_reg >>>= shift_magnitude
z dest_reg = src_reg >>> shift_magnitude (opt_sat)
z dest_reg = src_reg << shift_magnitude (S)
z accumulator = accumulator >>> shift_magnitude
z dest_reg = ASHIFT src_reg BY shift_magnitude (opt_sat)
z accumulator = ASHIFT accumulator BY shift_magnitude
Instruction Set

z Logical Shift
z dest_pntr = src_pntr >> 1
z dest_pntr = src_pntr >> 2dest_pntr = src_pntr << 1
z dest_pntr = src_pntr << 2dest_reg >>= shift_magnitude
z dest_reg <<= shift_magnitude
z dest_reg = src_reg >> shift_magnitude
z dest_reg = src_reg << shift_magnitude
z dest_reg = LSHIFT src_reg BY shift_magnitude

Instruction Set
Arithmetic Operations

z ROT (Rotate)
z dest_reg = ROT src_reg BY rotate_magnitude
z accumulator_new = ROT accumulator_old BY
rotate_magnitude
z Arithmetic Operations
z ABS
z dest_reg = ABS src_reg
z Add
z dest_reg = src_reg_1 + src_reg_2

Instruction Set
z Add/Subtract – Prescale Down
z dest_reg = src_reg_0 + src_reg_1 (RND20)
z dest_reg = src_reg_0 - src_reg_1 (RND20)
z Add/Subtract – Prescale Up
z dest_reg = src_reg_0 + src_reg_1 (RND12)
z dest_reg = src_reg_0 - src_reg_1 (RND12)
z Add Immediate
z register += constant

Instruction Set
z DIVS, DIVQ (Divide Primitive)
z DIVS ( dividend_register, divisor_register )
z DIVQ ( dividend_register, divisor_register )
z EXPADJ
z dest_reg = EXPADJ ( sample_register, exponent_register )
z MAX
z dest_reg = MAX ( src_reg_0, src_reg_1 )
z MIN
z dest_reg = MIN ( src_reg_0, src_reg_1 )

Instruction Set
z Modify – Decrement
z dest_reg -= src_reg
z Modify – Increment
z dest_reg += src_reg
z dest_reg = ( src_reg_0 += src_reg_1 )
z Multiply 16-Bit Operands
z dest_reg = src_reg_0 * src_reg_1 (opt_mode)
z Multiply 32-Bit Operands
z dest_reg *= multiplier_register

Instruction Set
z Multiply and Multiply-Accumulate to Accumulator
z accumulator = src_reg_0 * src_reg_1 (opt_mode)
z accumulator += src_reg_0 * src_reg_1 (opt_mode)
z accumulator –= src_reg_0 * src_reg_1 (opt_mode)
z Multiply and Multiply-Accumulate to Half-Register
z dest_reg_half = (accumulator = src_reg_0 * src_reg_1)
(opt_mode)
z dest_reg_half = (accumulator += src_reg_0 * src_reg_1)
(opt_mode)
z dest_reg_half = (accumulator –= src_reg_0 * src_reg_1)
(opt_mode)
Instruction Set
z Multiply and Multiply-Accumulate to Data Register
z dest_reg = (accumulator = src_reg_0 * src_reg_1) (opt_mode)
z dest_reg = (accumulator += src_reg_0 * src_reg_1) (opt_mode)
z dest_reg = (accumulator –= src_reg_0 * src_reg_1) (opt_mode)
z Negate (Two’s Complement)
z dest_reg = – src_reg
z dest_accumulator = – src_accumulator
z RND (Round to Half-Word)
z dest_reg = src_reg (RND)

Instruction Set
z Saturate
z dest_reg = src_reg (S)
z SIGNBITS
z dest_reg = SIGNBITS sample_register
z Subtract
z dest_reg = src_reg_1 - src_reg_2
z Subtract Immediate
z register -= constant

Instruction Set
External Event Management
z External Event Management

z Idle
z IDLE
z Core Synchronize
z CSYNC
z System Synchronize
z SSYNC
z EMUEXCPT (Force Emulation)
z EMUEXCPT

Instruction Set
External Event Management

z Disable Interrupts
z CLI
z Enable Interrupts
z STI
z RAISE (Force Interrupt / Reset)
z RAISE
z EXCPT (Force Exception)
z EXCPT

Instruction Set
Cache Control

z Test and Set Byte (Atomic)
z TESTSET
z No Op
z NOP
z MNOP
z Cache Control
z PREFETCH
z PREFETCH [ Preg ] ; /* indexed (a) */
z PREFETCH [ Preg ++ ] ; /* indexed, post increment (a) */

Instruction Set
Cache Control
z Cache Control
z FLUSH
z FLUSH [ Preg ] ; /* indexed (a) */
z FLUSH [ Preg ++ ] ; /* indexed, post increment (a) */
z FLUSHINV
z FLUSHINV [ Preg ] ; /* indexed (a) */
z FLUSHINV [ Preg ++ ] ; /* indexed, post increment (a) */
z IFLUSH
z IFLUSH [ Preg ] ; /* indexed (a) */
z IFLUSH [ Preg ++ ] ; /* indexed, post increment (a) */

Instruction Set
Video Pixel Operations
z Video Pixel Operations

z ALIGN8, ALIGN16, ALIGN24
z dest_reg = ALIGN8 ( src_reg_1, src_reg_0 )
z dest_reg = ALIGN16 (src_reg_1, src_reg_0 )
z dest_reg = ALIGN24 (src_reg_1, src_reg_0 )
z DISALGNEXCPT
z DISALGNEXCPT
z BYTEOP3P (Dual 16-Bit Add / Clip)
z dest_reg = BYTEOP3P ( src_reg_0, src_reg_1 ) (LO)
z dest_reg = BYTEOP3P ( src_reg_0, src_reg_1 ) (HI)

Instruction Set
z Video Pixel Operation

z BYTEOP3P (Dual 16-Bit Add / Clip)
z dest_reg = BYTEOP3P ( src_reg_0, src_reg_1 ) (LO, R)
z dest_reg = BYTEOP3P ( src_reg_0, src_reg_1 ) (HI, R)
z Dual 16-Bit Accumulator Extraction with Addition
z dest_reg_1 = A1.L + A1.H, dest_reg_0 = A0.L + A0.H
z BYTEOP16P (Quad 8-Bit Add)
z (dest_reg_1, dest_reg_0) = BYTEOP16P (src_reg_0,
src_reg_1)
z (dest_reg_1, dest_reg_0) = BYTEOP16P (src_reg_0,
src_reg_1) (R)
Instruction Set
z Video Pixel Operation

z BYTEOP1P (Quad 8-Bit Average – Byte)
z dest_reg = BYTEOP1P ( src_reg_0, src_reg_1 )
z dest_reg = BYTEOP1P ( src_reg_0, src_reg_1 ) (T)
z dest_reg = BYTEOP1P ( src_reg_0, src_reg_1 ) (R)
z dest_reg = BYTEOP1P ( src_reg_0, src_reg_1 ) (T, R)
z BYTEOP2P (Quad 8-Bit Average – Half-Word)
z dest_reg = BYTEOP2P ( src_reg_0, src_reg_1 ) (RNDL)
z dest_reg = BYTEOP2P ( src_reg_0, src_reg_1 ) (RNDH)
z dest_reg = BYTEOP2P ( src_reg_0, src_reg_1 ) (TL)
z dest_reg = BYTEOP2P ( src_reg_0, src_reg_1 ) (TH)
Instruction Set
z BYTEOP2P (Quad 8-Bit Average – Half-Word)
z dest_reg = BYTEOP2P ( src_reg_0, src_reg_1 ) (RNDL, R)
z dest_reg = BYTEOP2P ( src_reg_0, src_reg_1 ) (RNDH, R)
z dest_reg = BYTEOP2P ( src_reg_0, src_reg_1 ) (TL, R)
z dest_reg = BYTEOP2P ( src_reg_0, src_reg_1 ) (TH, R)
z BYTEPACK (Quad 8-Bit Pack)
z dest_reg = BYTEPACK ( src_reg_0, src_reg_1 )
z BYTEOP16M (Quad 8-Bit Subtract)
z (dest_reg_1, dest_reg_0) = BYTEOP16M (src_reg_0,
src_reg_1)
z (dest_reg_1, dest_reg_0) = BYTEOP16M (src_reg_0,
src_reg_1) (R)
Instruction Set
Vector Operations

z SAA (Quad 8-Bit Subtract-Absolute-Accumulate)
z SAA ( src_reg_0, src_reg_1 )
z SAA ( src_reg_0, src_reg_1 ) (R)
z BYTEUNPACK (Quad 8-Bit Unpack)
z ( dest_reg_1, dest_reg_0 ) = BYTEUNPACK src_reg_pair
z ( dest_reg_1, dest_reg_0 ) = BYTEUNPACK src_reg_pair
(R)
z Vector Operations
z Add on Sign
z dest_hi = dest_lo = SIGN (src0_hi) * src1_hi + SIGN
(src0_lo) * src1_lo
Instruction Set
Vector Operations
z Vector Operations
z VIT_MAX (Compare-Select)
z dest_reg = VIT_MAX ( src_reg_0, src_reg_1 ) (ASL)
z dest_reg = VIT_MAX ( src_reg_0, src_reg_1 ) (ASR)
z dest_reg_lo = VIT_MAX ( src_reg ) (ASL)
z dest_reg_lo = VIT_MAX ( src_reg ) (ASR)
z Vector ABS
z dest_reg = ABS source_reg (V)
z Vector Add / Subtract
z dest = src_reg_0 +|+ src_reg_1

Instruction Set
Vector Operations
z Vector Operations
z Vector Add / Subtract
z dest = src_reg_0 –|+ src_reg_1
z dest = src_reg_0 +|– src_reg_1
z dest = src_reg_0 –|– src_reg_1
z dest_0 = src_reg_0 +|+ src_reg_1,
z dest_1 = src_reg_0 –|– src_reg_1
z dest_0 = src_reg_0 +|– src_reg_1,
z dest_1 = src_reg_0 –|+ src_reg_1
z dest_0 = src_reg_0 + src_reg_1,
z dest_1 = src_reg_0 – src_reg_1
z dest_0 = A1 + A0, dest_1 = A1 – A0
z dest_0 = A0 + A1, dest_1 = A0 – A1

Instruction Set
Vector Operations
z Vector Operations
z Vector Arithmetic Shift
z dest_reg = src_reg >>> shift_magnitude (V)
z dest_reg = ASHIFT src_reg BY shift_magnitude (V)
z Vector Logical Shift
z dest_reg = src_reg >> shift_magnitude (V)
z dest_reg = src_reg << shift_magnitude (V)
z dest_reg = LSHIFT src_reg BY shift_magnitude (V)
z Vector MAX
z dest_reg = MAX ( src_reg_0, src_reg_1 ) (V)

Instruction Set
Vector Operations
z Vector Operations
z Vector MIN
z dest_reg = MIN ( src_reg_0, src_reg_1 ) (V)
z Vector Negate (Two’s Complement)
z dest_reg = – source_reg (V)
z Vector PACK
z Dest_reg = PACK ( src_half_0, src_half_1 )
z Vector SEARCH
z (dest_pointer_hi, dest_pointer_lo ) = SEARCH src_reg
(searchmode)

Instruction Set
Parallel Issue Instructions
z Parallel Issue Instructions
z Supported Parallel Combinations
z A 32-bit ALU/MAC instruction || A 16-bit instruction || A 16-bit instruction ;
z A 32-bit ALU/MAC instruction || A 16-bit instruction ;
z MNOP || A 16-bit instruction || A 16-bit instruction ;
z 32-Bit ALU/MAC Instructions
z 16-Bit Instructions
z The two 16-bit instructions in a multi-issue instruction must each
be from Group1 and Group2 instructions
z Only one of the 16-bit instructions can be a store instruction
z If the two 16-bit instructions are memory access instructions, then
z both cannot use P-registers as address registers. In this case, at
least
z one memory access instruction must be an I-register version.

Instruction Set
Parallel Issue Instructions
z Parallel Issue Instructions

z Examples
z Two Parallel Memory Access Instructions
saa (r1:0, r3:2) || r0=[i0++] || r2=[i1++] ;
z One Ireg and One Memory Access Instruction in
Parallel
r7.h=r7.l=sign(r2.h)*r3.h + sign(r2.l)*r3.l || i0+=m3 || r0=[i0];
z One Ireg Instruction in Parallel
r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 ;

Blackfin Platforms
z Blackfin eMedia Platform
z ideally suited for IP set-top boxes, media servers, portable
entertainment devices, DTVs, residential data/media
gateways and networked digital media adapters
z Multiple digital video formats - Windows Media 9 Series /
VC-1, MPEG-2, MPEG-4, H264 AVC and future format
z Multiple audio formats including WMA, MP3, MP3 PRO,
AAC, and others
z G.711, G.728, G.729AB, G.723.1A, AMR for Speech
z On-screen user interfaces and displays

Blackfin Platforms
z Blackfin eMedia Platform
z A wide range of home-network protocols, such as UPnP,
TCP/IP, Ethernet, HPNA 2.0, 802.11a/b/g and HomePlug
z Access and management of centralized or distributed
media
z Remote firmware upgrade to enable new formats and
technologies as they are introduced
z Blackfin Car Telematics Platform
z serve the embedded processing market for feature-rich,
multimedia car telematics applications

Blackfin Platforms
z meets the computational demands and power constraints
of in-vehicle safety systems, audio, video, and wireless
communications
z functions implemented on the Blackfin Processor include
GPS, hands free operation, microphone array, voice-
activated control, GSM interfaces, and car audio
play/record of MP3 and WMA content
z fully supported with speech recognition and text-to-speech
algorithms available from Scansoft, Inc. and with the noise-
and echo-cancellation algorithms from Bitwave and Clarity

Blackfin Platforms
z includes a collection of telematics function modules that
reduce code-development time and enable faster time-to-
market
z Blackfin BRAVO Platform
z deliver audio, streaming video, networked camera and
videophone capabilities with up to full D1,
MPEG4/MPEG2/DivX/WMV9 30 fps full color, full motion
video in CIF resolution over broadband networks

Blackfin Platforms
z include an Ethernet port to interface with cable, xDSL,
Ethernet, USB, IEEE 802.11x and fiber, and support
Microsoft Windows Media, ISMA and QuickTime protocols
z delivering full duplex audio and videophone functions for
broadband networks
z uses a scalable bit rate and Ethernet port to enable
operation over cable, xDSL, Ethernet, 3G and fiber
z video capabilities of up to 30 frames/second performance
in CIF resolutions and still images at 4CIF resolution

Blackfin Platforms
z enables any cable-connected standard NTSC/PAL TV (with
RCA output connectors and camera input connectors) to a
high-quality videophone
z enables a PC browser to display what the camera sees,
supporting an HTTP server function with MJPEG and
MPEG4 video to enable access and control from any
standard PC with a Microsoft Internet Explorer or Netscape
browser or QuickTime player
z optional trigger function enables the browser to sound an
alarm when the camera senses predefined changes in
motion or position

Targeted Application
z Digital Media Processing
z Digital Camera
z Camcorder
z Video Capture Board
z Document Scan/Fax
z Portable Information Appliances
z video-enabled handheld devices (PDAs)
z web phones/terminals
z e-mail terminals

z Portable Information Appliances
z Internet audio players
z Automotive Telematics, Infotainment, and
Driver Assistance
z Telematics
z Navigation/GPS
z Car Audio Amplifiers
z Hands Free
z Voice Activated Control

z Networking and Internet Appliances
z VoIP Gateways
z Multi-Service Applications
z IP-PBX, PBX Adapters
z Networked Set-Top-Box
z Internet-smart handheld devices (PDAs)
z Internet gaming devices
z VoIP phones/terminals
z NetTV

z Wireless
z Wireless Terminals
z GSM Voice Wireless Handsets
z GPRS Wireless Terminals
z EDGE Wireless Terminals
z TD-SCDMA Wireless Terminals
z W-CDMA/UMTS Wireless Terminals

z Wireless
z W-CDMA/UMTS Wireless Terminals
z Entertainment Wireless Terminals
z Smart phone Wireless Terminals
z 2.5G and 3G Wireless Base Stations

References
z Blackfin Processor
z http://www.analog.com/processors/processors/bla
ckfin/index.html
z Getting Started With Blackfin Processor
z http://www.analog.com/UploadedFiles/Associated
_Docs/356225839blk_ug_40.pdf
z Blackfin Processor Architecture Overview
ckfin/blackfinArchOverview.html

References
z Blackfin Processor Core Basics
ckfin/blackfinCoreBasics.html
z Analog Devices ADSP-BF5xx
ckfin/pdf/blackfin_summary.pdf
z Blackfin Target Market Backgrounder
ckfin/blackfinMarketsApplications.html

References
z Blackfin Processor Instruction Set
Reference
z http://www.analog.com/processors/epManualsDis
play/0,2795,,00.html?SectionWeblawId=207&Con
tentID=39274&Language=English
z Blackfin Embedded Processor Data Sheet
z http://www.analog.com/UploadedFiles/Data_Shee
ts/144127970ADSP_BF531_2_3_a.pdf

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CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 1

z These slide presentations were prepared by

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 2

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 3

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 4

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 5

External 32- 16- 16- 16- 32- 16- 16- 16-

SPORTs, Yes Yes Yes Yes Yes Yes Yes Yes

Programma Yes Yes Yes Yes Yes Yes Yes Yes

TWI- No No No No No Yes Yes Yes

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 8

RTC Yes Yes Yes Yes No Yes Yes Yes

Core 1-1.6 0.8- 0.8- 0.8- 0.8- 0.8- 0.8- 0.8-

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 9

Lead-Free No Yes Yes Yes Yes Yes Yes Yes

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 10

VDDINT Internal Supply Voltage (ADSP- 0.8 1.2 1.32 V

VDDRTC Real-Time Clock Power Supply 2.25 3.6 V

Parameters Test Condition Min Max Unit

IOZL Three-State Leakage Current @ VDDEXT = maximum, 10 uA

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 12

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 13

Pin Name I/O Function Driver

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 15

PF10/PPI9 I/O Programmable Flag 10/PPI 9 C5

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 16

DR0SEC I SPORT0 Receive Data Secondary

TSCLK0 I/O SPORT0 Transmit Serial Clock D6

TFS0 I/O SPORT0 Transmit Frame Sync C5

DT0PRI O SPORT0 Transmit Data Primary C5

DT0SEC O SPORT0 Transmit Data Secondary C5

RSCLK1 I/O SPORT1 Receive Serial Clock D6

RFS1 I/O SPORT1 Receive Frame Sync C5

DR1PRI I SPORT1 Receive Data Primary

DR1SEC I SPORT1 Receive Data Secondary

TSCLK1 I/O SPORT1 Transmit Serial Clock D6

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 18

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 20

Pin Name I/O Function Driver

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 21

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 22

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 23

Timer UART Peripheral

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 24

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 25

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 26

L1 Instruction L2 Data &

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CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 31

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 32

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 33

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 34

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 35

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 36

z Dual-Core Processors Add Flexibility

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 37

DATA ARITHMETIC UNIT

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 38

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 39

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