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Step 1. Specification
Example: Sequence detector
Design a circuit that detects if two or more consecutive 1s appear on its input
Key assumption: changes in the input, w, are synchronous with the clock
If changes are asynchronous, then additional states are required to detect input
transitions
A =y2y1 = 00,
B =y2y1 = 01,
C =y2y1 = 10
Step 7. Implementation
One-Hot Encoding
Use as many state variable as there are states.
Only one of them may be 1 or hot at once.
Treat unused states as dont cares.
Only sometimes advantageous
1. Use design technique previously described to design the next state logic, output logic
and flipflop circuits.
2. Use schematic diagrams or structural VHDL to describe these circuits. E.g. use
components for the flipflops etc.
3. Use CAD to simulate behavior
4. Use CAD to automatically implement the circuit in a chip, such as a PLD
5. Process blocks do not synthesize as sequential circuits by default. This behavior must
be defined explicitly.
This first process defines a combinational logic block. The second block defines a clocked flipflop
sequential block and the last line defines another combinational logic block.
Note that since STD_LOGIC has 9 different possible states, when others and else must be
used as appropriate.
Mealy FSM
Moore FSM
Requires more state definitions than Mealy.
State Minimization
Successor state.
If input w=0 is applied to FSM in state Si and machine moves to state Su, then Su is a 0-successor.
If input w=1 is applied to FSM in state Si and machine moves to state Sv, then Sv is a 1-successor.
Generally, for multiple inputs, successors of Si are referred to as K-successors of Si, where K is the
set of all possible combinations of the inputs.
Si and Sj are said to be equivalent if for every possible input sequence, same output sequence is
produced.
A partition consists of one or more blocks where each block comprises a subset of states that
may be equivalent, but are not equivalent to states in other blocks.
Procedure
Example
Moore FSM
Mealy FSM