Chapter 2

CPU architecture and Instruction Set

PIC Architecture
RISC-Like Features
Harvard architecture
Instruction pipelining
Register file concept
Single-cycle instruction
All instructions single-word
LWI (Long Word Instruction)
Reduced instruction set

CpE 112 : Klinkhachorn

Tradition Neumann Architecture

Input

CPU

Memory
(Program&Data)

Output

Fetches instruction
and data from one
memory.
Limits operating
bandwidth.

CpE 112 : Klinkhachorn

Harvard Architecture
Memory
(Program)

Input

CPU

Uses two separate

memory space for
instruction and data.

Output
Increases throughput

Memory
(Data)

Different program and

data bus widths are
possible
CpE 112 : Klinkhachorn

Harvard Architecture

CpE 112 : Klinkhachorn

Pipelining of Instructions

CpE 112 : Klinkhachorn

Pipelining of Instructions (Cont.)

CpE 112 : Klinkhachorn

Architecture - x12
Clock/Counter
384x12
to
2048x12

ROM
EPROM
Program
Memory

Program
Bus

Instruction
Reg

Program
Counter
Data
Bus
STACK1
STACK2

RAM
File
Registers

RAM Addr

Addr Mux
Direct Addr

24x8
24x8
to
to
73x8
73x8

Indirect
Indirect Data
Data
Address
Address
FSR
STATUS Reg

T0CKI

I/O Ports

Ports

Mux
MCLR
OSC1
OSC2

Instruction
Decode &
Control

Timing
Generation

Watchdog
Timer
PowerPower-on
Reset
Device Rst
Timer

ALU
W Reg

*From Microchip Seminar 2000

CpE 112 : Klinkhachorn

PIC16C508/509

$1.00
For OTP

CpE 112 : Klinkhachorn

PIC12C5XX

CpE 112 : Klinkhachorn

Architecture - x14
Clock/Counter

ROM
EPROM
FLASH

Program
Counter

Program
Memory

STACK1

Program
Bus
Instruction Reg

Data Bus

RAM
File
Registers

STACK8
RAM Addr
Addr Mux
Direct Addr

36x8
to
368x8

Indirect Data
Address
FSR

T0CKI

I/O Ports

STATUS Reg

OSC1
OSC2

Mux

Interrupts

MCLR
Instruction
Decode &
Control

Timing
Generation

Ports

Peripheral(s)

Brown-out
Reset
Watchdog
Timer

ALU

Power-on
Reset
OSC Start
-upTimer

W Reg

In-Circuit
Debugger

*From Microchip Seminar 2000

Low Volt
Program

CpE 112 : Klinkhachorn

PIC16C71X

CpE 112 : Klinkhachorn

PIC16C71X

CpE 112 : Klinkhachorn

Architecture - x16
IR BUS <16>
12

BSR<7:4>
IR BUS<7:0>

IR
IRLATCH
LATCH<16>
<16>

BITOP
WREG<8>
<8>
BITOP WREG

INSTRUCTION
INSTRUCTION
DECODER
DECODER

DATA
DATA
RAM
RAM
ALU
SHIFTER

LITERAL
LITERAL

Up
Upto
to
1536
1536bytes
bytes

8 x 8 mult

8
FSR0\
FSR1

CONTROL
OUTPUTS

TABLE
TABLELATCH
LATCH<16>
<16>

PRODH
PRODH PRODL
PRODL

DECODER
DECODER

ROM
ROMLATCH
LATCH<16>
<16>

DATA BUS <8>

BSR
BSR

DATA LATCH

4 3
PCLATH<8>
IR <2:0> PCLATH<8>

TABLE
TABLEPTR<16>
PTR<16>

IR <7>
Q1, Q2,
Q3, Q4
CHIP_RESET
AND OTHER
CONTROLS
SIGNALS

Clock Generator
Power On Reset
Watchdog Timer
OSC Startup Timer
Test Mode Select

OSC1, OSC2

Ports

PCH
PCH PCL
PCL

16

SYSTEM
SYSTEM
INTERFACE
INTERFACE
BUS
BUS

13

STACK
STACK
16
16XX16
16

VDD, VSS

PROGRAM
MEMORY
(EPROM/ROM)
Up to 16K words

16

Peripherals
MCLR/VPP

16

TEST

*From Microchip Seminar 2000

CpE 112 : Klinkhachorn

PIC17C4X

CpE 112 : Klinkhachorn

PIC17C4X

CpE 112 : Klinkhachorn

Architecture - x16 Enhanced

Table Pointer <2>

21

21

Data RAM
(up to
4K Bytes)

Inc/dec logic
PCLATU

Program Memory
(up to 2M Bytes)

12 (2)

PCLATH

PCU PCH

PRODH PRODL

PORTS

Address<12>
Address<12>

PERIPHERALS

BSR

BIT OP

FSR1

T1OS1
T1OSO

Timing Generation

4X PLL
Brown-out
Reset

*From Microchip Seminar 2000

ALU<8>

12

Instruction
Register
Power-up
Timer

OSC2/CLK0
OSC1/CLK1

Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset

MCLR

8
8

FSR2
TABLELATCH

WREG

FSR0

31 Level Stack

8
8

12

PCL

Program Counter

8x8
Multiply

Instruction
Instruction
Decode
Decode
and
and
Control
Control

VDD,VSS

CpE 112 : Klinkhachorn

PIC18CXXX

CpE 112 : Klinkhachorn

PIC18CXXX

CpE 112 : Klinkhachorn

Mid-Range PIC

16F877

PIC16F87X
28/40-pin 8-Bit CMOS FLASH Microcontrollers
Microcontroller Core Features:
High-performance RISC CPU
Only 35 single word instructions to learn
All single cycle instructions except for program branches which are two cycle
Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle
Up to 8K x 14 words of FLASH Program Memory
Up to 368 x 8 bytes of Data Memory (RAM)
Up to 256 x 8 bytes of EEPROM data memory
Pinout compatible to the PIC16C73B/74B/76/77
Interrupt capability (up to 14 sources)
Eight level deep hardware stack
Direct, indirect and relative addressing modes
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

CpE 112 : Klinkhachorn

PIC16F87X (Cont.)
28/40-pin 8-Bit CMOS FLASH Microcontrollers
Microcontroller Core Features:
Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
Programmable code-protection
Power saving SLEEP mode
Selectable oscillator options
Low-power, high-speed CMOS FLASH/EEPROM technology
Fully static design
In-Circuit Serial Programming (ICSP) via two pins
Single 5V In-Circuit Serial Programming capability
In-Circuit Debugging via two pins
Processor read/write access to program memory
Wide operating voltage range: 2.0V to 5.5V
High Sink/Source Current: 25 mA
Commercial and Industrial temperature ranges
Low-power consumption:
< 2 mA typical @ 5V, 4 MHz
20 uA typical @ 3V, 32 kHz
< 1 uA typical standby current
CpE 112 : Klinkhachorn

PIC16F87X (Cont.)
28/40-pin 8-Bit CMOS FLASH Microcontrollers
Peripheral Features:
Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler
Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
Two Capture, Compare, PWM modules
Capture is 16-bit, max. resolution is 12.5 ns
Compare is 16-bit, max. resolution is 200 ns
PWM max. resolution is 10-bit
10-bit multi-channel Analog-to-Digital converter
Synchronous Serial Port (SSP) with SPI (Master Mode) and I2C (Master/Slave)
Universal Synchronous Asynchronous ReceiverTransmitter (USART/SCI)
Parallel Slave Port (PSP) 8-bits wide, with external RD/, WR/ and CS/ controls
Brown-out detection circuitry for Brown-out Reset (BOR)

CpE 112 : Klinkhachorn

PIC16F877

PIC16F87X Key Features

CpE 112 : Klinkhachorn

Program Memory (PIC16X/17X)

Reset vector
0x000
Interrupt vector
0x004
Memory Top

0x3ff (1K)
0x7ff (2K)
0xfff (4K)
0x1fff (8k)

Program Counter
13 bits

Memory Top

Main Program
And
ISR

0x0ff

Tables
Jump to ISR

0x004

Jump to Main

0x000

CpE 112 : Klinkhachorn

Program Counter
Accessing Program Memory
12

10

Program
Counter

PIC
2K Program

Memory

Ignored bits

12

10

2K (11-bit address range)

Program
Counter
Ignored bits

PIC
4K Program

Memory
4K (12-bit address range)

CpE 112 : Klinkhachorn

Program Counter
Accessing Program Memory: Call/Goto Instruction
Call/Goto
Instruction

13

10

0xfff
Call

PCLATH, 3=1

11-bit address range

12
Program
Counter

Program Memory

10

4K
Parts
0x800
0x7ff

PCLATH 0
4 3

PCLATH, 3=0

PCLATH Program Counter Latch

2K
Parts
0x000

CpE 112 : Klinkhachorn

Data Memory (Register File)

An instruction can access data (register file)

via an address
Two type of register file
General purpose register file
RAM (8 bit data bus)

Special-purpose register file

Input/Output ports
Control/Status registers
A/D, Timer, etc.

CpE 112 : Klinkhachorn

Data Memory Organization

Partitioned into multiple banks
Each bank extends up to 0x7f (128 bytes)
Bits RP1 and RP0 (status register bit 6:5) are
the bank select bits
6 5

RP1 RP0

Status Register (0x03, 0x83, 0x103, 0x183)

= 00 ! Bank 0
= 00 ! Bank 1
= 00 ! Bank 2
= 00 ! Bank 3
CpE 112 : Klinkhachorn

Register File Structure (16F87X)

0x00

0x1f
0x20

Bank 0

Bank 1

Bank 2(3)

(128 bytes)

(128 bytes)

(128 bytes)

Special purpose
registers
(32 bytes)

0x80

0x9f
0xa0

RAM
(96 bytes)

0x7f

Special purpose
registers
(32 bytes)

0x100(180)
0x10f(18f)
0x110(190)
0x11f(19f)
0x120(1a0)

RAM
(80 bytes)

0xef
0xf0
0xff

Accesses
70h-7fh

Special purpose
registers
(16 bytes)

RAM
(16 bytes)

RAM
(80 bytes)

0x16f(1ef)
0x170(1f0)
0x17f(1ff)

Accesses
70h-7fh

CpE 112 : Klinkhachorn

PIC16F87X Special File Registers

Bank 0
(128 bytes)

0x00

0x1f
0x20

Special purpose
registers
(32 bytes)

RAM
(96 bytes)

0x7f
CpE 112 : Klinkhachorn

PIC16F87X Special File Registers

CpE 112 : Klinkhachorn

PIC16XXX Instruction Set

CpE 112 : Klinkhachorn

PIC16XXX Instruction Set

CpE 112 : Klinkhachorn

PIC16XXX Instruction Set

CpE 112 : Klinkhachorn

PIC General Format for Instruction

Byte-Oriented file register operations
13

OPCODE

f(File #)

Examples:
movf Temp,W; W=Temp

d = 0 for desination W
addwf Temp,f ;Temp=Temp+W
d = 1 for destination f
f = 7-bit file register address

Bit-Oriented file register operations

13

OPCODE

10 9

7 6

b(Bit#)

f(File #)

b = 3-bit address
f = 7-bit file register address

Examples:
bcf PORTB,2 ; clear bit 2 of PORTB
btfsc Temp,0; skip if bit 0=0

CpE 112 : Klinkhachorn

PIC General Format for Instruction

Literal and Control Operation
13

8 7

OPCODE

k(literal)
k = 8-bit immediate value

Examples:
movlw

5; Load 5 to W

addlw

10; Add 10 to W

CALL and GOTO Instructions

13

11 10

OPCODE

k(literal)

k = 11-bit immediate value (address)

Examples:
goto Taks1; jump to Task1
call

Sub1; call sub1

CpE 112 : Klinkhachorn

Direct Addressing Mode

Byte/Bit oriented instruction
13

0x000

Op code
7 bit address
RP1 RP0

Data Memory

9 bit effective address

0x1ff
CpE 112 : Klinkhachorn

Indirect Addressing Mode

Indirect access memory location via FSR

(File Select Register) through INDF register

FSR register
Status Reg. <7>

IRP

Example: Clear RAM using

Bank Select
0x00

0x80

0x100

0x180

0x7f

0xff

0x17f

0x1ff

Bank 0

Bank 1

Bank 2

indirect addressing
movlw 0x20
movwf FSR
Next clrf INDF
incf FSR
btfss FSR,4
goto Next
Continue
:

;Init ptr
;to RAM
;clear RAM
;inc. ptr
;all done?
;No, clear next
; Yes, continue

Bank 3
CpE 112 : Klinkhachorn

CPU Registers

W (Working Register)
Serves a function similar to Accumulator

FSR (File Select Register)

Address 0x04,0x84,0x104,0x184
Indirect data memory address pointer

INDF (Address 0x00, 0x80, 0x100, 0x180)

Addressing this location uses contents of FSR to address data
memory (not a physical register)

PCL (Address 0x02, 0x82, 0x102, 0x182)

Program Counters(PC) Least Significant Byte

PCLATH (Address 0x0a, 0x8a, 0x10a, 0x18a)

13 bit PC

Write Buffer for the upper 5 bits of the PC

CpE 112 : Klinkhachorn

CPU Registers (Cont.)

STATUS (address 0x03,0x83,0x103,0x183)
7

IRP: Register bank select bit (Indirect addressing)

1 = Bank 2,3 (0x100 0x1ff)
0 = Bank 0,1 (0x00 0xff)

RP1, RP0:Register bank select bits (direct addressing)

11 = Bank 3 (0x180-0x1ff)
10 = Bank 2 (0x100-0x17f)
01 = Bank 1 (0x80-0xff)
00 = Bank 0 (0x00-0x7f)

TO:Time-out bit
PD:Power-down bit
Z:Zero bit
DC:Digit carry/borrow bit (from 4th low order bit)
C:Carry/borrow bit

CpE 112 : Klinkhachorn

PIC16F87X STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW

Stack Level 1
Stack Level 2
.
.
.
Stack Level 8
CpE 112 : Klinkhachorn