Verilog Basic Experiments

INDEX
S.No.
1
2
3
4
5
6
7
8
9
10
11
12
Name of Experiment
Design and simulation of two input LOGIC GATES using
VERILOG, and synthesis on FPGA.
Design and simulation of D Flip Flop, and synthesis on FPGA.
Design and simulation of FULL ADDER using VERILOG, and
synthesis on FPGA.
Design and simulation of 4 bit Adder Using VERILOG, and
synthesis on FPGA.
Design and simulation of [8:1] MUX using VERILOG, and
synthesis on FPGA.
Design and simulation of [1:8] DEMUX using VERILOG, and
synthesis on FPGA.
Design and simulation of CLOCK DIVIDER of 1 Hz using
VERILOG, and synthesis on FPGA.
Design and simulation of 4 bit UP COUNTER & DOWN
COUNTER using VERILOG, and synthesis on FPGA.
Design and simulation of 8-bit SERIAL IN PARALLEL OUT type
register using VERILOG, and synthesis on FPGA.
Design and simulation of 8-bit PARALLEL IN SERIAL OUT type
register using VERILOG, and synthesis on FPGA.
Design and simulation of SEVEN SEGMENT DISPLAY DECODER
using VERILOG, and synthesis on FPGA.
Design and simulation of 4 bit Multiplier using VERILOG, and
synthesis on FPGA.
Date of
Experiment
Sign. /
Remarks
EXPERIMENT-1
Objective:
Design and simulation of two input LOGIC GATES using VERILOG, and synthesis on
FPGA.
Hardware and Software Requirements:
Xilinx ISE Design Suite 14.7 (Software Tool).
Xilinx Spartan-3E FPGA Starter Kit Digilent Inc.
USB Cable & Power Adapter/Cord.
Overview:
In this lab, we are going to design AND, OR, NAND, NOR, XOR, XNOR GATE using
Verilog HDL. The Diagram for which is given below:
Diagram for AND GATE :
Truth Table for AND GATE :

IN 1
low
high
low
high
Diagram for OR GATE :
IN 2
low
low
high
high
Out AND
low
low
low
high
Truth Table for OR GATE:

IN 1
low
high
IN 2
low
low
OUT OR
low
high
low
high
high
high
high
high
Diagram for NAND GATE :
Truth Table for NAND GATE :
IN 1
low
high
low
high
Diagram for NOR GATE :
IN 2
low
low
high
high
OUT NAND
high
high
high
low
Truth Table for NOR GATE:

IN 1
low
high
low
high
IN 2
low
low
high
high
OUT NOR
high
low
low
low
IN 2
low
low
high
high
OUT XOR
low
high
high
Diagram for XOR GATE :
Truth Table for XOR GATE:
IN 1
low
high
low
high
Diagram for NXOR GATE :
low
Truth Table for XNOR GATE:

IN 1
low
high
low
high
IN 2
low
low
high
high
OUT XNOR
high
low
low
high
Verilog HDL Code:

module logic_gate(input in1,in2,
output
out_and,out_or,out_nand,out_nor,out_xor,out_xnor
);
assign out_and=in1&in2;
assign out_or=in1|in2;
assign out_nand=~(in1&in2);
assign out_nor=~(in1|in2);
assign out_xor=in1^in2;
assign out_xnor=in1^~in2;
endmodule
User Constraints File (UCF):

# ==== Slide Switches (SW) ====
NET "in1" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "in2" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
# ==== Discrete LEDs (LED) ====
NET "out_and" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "out_or" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "out_nand" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8
;
NET "out_nor" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8
;
NET "out_xor" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8
;
NET "out_xnor" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8
;
RTL View of the Design:
Simulation Waveforms:
Demonstration of Experiment:
We have used Xilinx Spartan-3E FPGA Starter Kit developed by Digilent to demonstrate our
experiment. The Spartan-3E FPGA Starter Kit board has four slide switches. The slide
switches are labeled SW3 through SW0 as shown in this figure. Switch SW3 is the left-most
switch, and SW0 is the right-most switch. When in the UP or ON position, a switch connects
the FPGA pin to 3.3V, a logic High. When DOWN or in the OFF position, the switch connects
the FPGA pin to ground, a logic Low.
The board also has eight individual surface-mount LEDs located above the slide switches as
shown in this figure. The LEDs are labeled LED7 through LED0. LED7 is the left-most LED,
LED0 the right-most LED.
We have used two slide switches & six LEDs. The Inputs of LOGIC GATES IN1, IN2 are
assigned to Slide Switches SW0, SW1 respectively. The output of LOGIC GATES are
assigned to LEDs:
OUTPUTS
and
or
nand
nor
xor
xnor
LED
LED7
LED6
LED5
LED4
LED3
LED2
Result:
We have successfully demonstrate AND GATE using Verilog HDL on Spartan-3E FPGA
Starter Kit Board.
Date of Experiment:
Signature of Student
Signature of Class Teacher
EXPERIMENT- 2
Objective:
Design and simulation of D Flip Flop, and synthesis on FPGA Hardware and Software
Requirements:
Overview:
In this lab, we are going to design a D Flip Flop using Verilog HDL. The Diagram for which
is given below:
Fig: D Flip Flop.

Design Specifications:
The D ip-op is widely used. It is also known as a "data" or "delay" flip-flop.The D flipflop captures the value of the D-input at a definite portion of the clock cycle (such as the
rising edge of the clock). That captured value becomes the Q output. At other times, the
output Q does not change. The D flip-flop can be viewed as a memory cell, a zero-order
hold, or a delay line.
Truth table:
Clock
Rising Edge
Rising Edge
No Rising Edge
Verilog HDL Code:
module dff(
D
0
1
x
Q
0
1
Q
input d,
output reg q,
output reg qn,
input clk,
input rst
);
always @(posedge clk or negedge rst)
begin
if(rst==1'b0)
begin
q <=0;
qn <=1;
end
else
begin
q <= d;
qn <= ~d;
end
end
endmodule

#####################################################
### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE
#####################################################
# ==== Slide Switches
NET "d" LOC = "L13" |
NET "rst" LOC = "L14"
NET "clk" LOC = "H18"
(SW) ====
IOSTANDARD = LVTTL | PULLUP ;
| IOSTANDARD = LVTTL | PULLUP ;

NET "q" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "qn" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
Figure : D FlipFlop
switches are labeled SW3 through SW0 as shown in Figure 4. Switch SW3 is the left-most
the FPGA pin to 3.3V, a logic High. When DOWN or in the OFF position, the switch
connects the FPGA pin to ground, a logic Low.
shown in Figure 4. The LEDs are labeled LED7 through LED0. LED7 is the left-most LED,
We have used three slide switches & two LEDs. The Input of D Flip Flop D, RST, & CLK
are assigned to Slide Switches SW0, SW1 & SW2 respectively. The outputs of D Flip Flop Q
& Qn are assigned to LED0 & LED1 respectively.
Figure 4: Slide Switches & Discrete LEDs

Result:
All the outputs of the D Flip Flop are verified with the help of truth table on Xilinx Spartan3E FPGA Starter Kit.
Date of Experiment:
EXPERIMENT- 3
Objective:
Design and simulation of FULL ADDER using VERILOG, and synthesis on FPGA.
(by using HALF ADDER)
Overview:
In this lab, we are going to design a simple Full Adder using Verilog HDL. The Diagram for
which is given below:
Figure 1: Full Adder using Gates

The function of the full adder is quite simple add two, one-bit numbers. The full adder is a
common circuit used in many designs both small and large (including processors). The full
adder is designed to be cascaded to compute addition on (arbitrarily) larger numbers.
Full Adder has three inputs, A, B, and Cin. It has two outputs, Sum and Cout. The inputs A
and B are two, 1-bit numbers that the addition will be performed on. The output is located at
the output labeled Sum. There are also two other I/O pins, Cin and Cout. These are called
Carry In and Carry Out, respectively. They are used for cascading adders together.
Figure 2: A Block Diagram of the circuit
Truth Table:
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
Cin
0
1
0
1
0
1
0
1
Sum
0
0
0
1
0
1
1
1
Table 1: Truth Table of Full Adder

Verilog HDL Code:
Full Adder
module fadd(a,b,cin,sum,cout);
input a;
input b;
input cin;
output sum;
output cout;
wire wa,wb,wc;
hadd hadd1(a,b,wa,wb);
hadd hadd2(wa,cin,sum,wc);
assign cout=wb|wc;
endmodule
Cout
0
1
1
0
1
0
0
1
Half Adder
module hadd(a,b,sum,cout);
input a;
input b;
output out;
output cout;
assign sum=a^b;
assign cout=a&b;
endmodule
Test Bench:
module fadder;
// Inputs
reg a;
reg b;
reg cin;
// Outputs
wire sum;
wire cout;
// Instantiate the Unit Under Test (UUT)
fadd uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
// Initialize Inputs
a = 0;b = 0;cin = 0;#100;
a = 0;b = 0;cin = 1;#100;
a = 0;b = 1;cin = 0;#100;
a = 0;b = 1;cin = 1;#100;
a = 1;b = 0;cin = 0;#100;
a = 1;b = 0;cin = 1;#100;
a = 1;b = 1;cin = 0;#100;
a = 1;b = 1;cin = 1;#100;
// Wait 100 ns for global reset to finis
endmodule

#####################################################
NET "a" LOC = "L13" |
NET "b" LOC = "L14" |
NET "cin" LOC = "H18"
(SW) ====

NET "sum" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "cout" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
Figure 3: RTL View of Full Adder
We have used three slide switches & two LEDs. The Input of Full Adder A, B, & Cin are
assigned to Slide Switches SW0, SW1 & SW2 respectively. The outputs of Full adder Sum &
Carry are assigned to LED0 & LED1 respectively.

Result:
All the outputs of the Full Adder are verified with the help of truth table on Xilinx Spartan-3E
FPGA Starter Kit.
Date of Experiment:
EXPERIMENT 4
Objective:
Design and simulation of 4 bit Adder Using VERILOG, and synthesis on FPGA.
(By using FULL ADDER)
Overview:
In this lab, we are going to design a 4-bit Adder using Verilog HDL. The Diagram for which
is given below:
Figure 1: 4-bit Full Adder using Gates
Full Adder has three inputs, A, B, and Cin. It has two outputs, Sum and Cout. The inputs A
and B are two, 1-bit numbers that the addition will be performed on. The output is located at
the output labeled Sum. There are also two other I/O pins, Cin and Cout. These are called
Carry In and Carry Out, respectively.
Figure 2: A Block Diagram of the circuit
Truth Table:
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
SUM
0
1
1
0
1
0
0
1
COUT
0
0
0
1
0
1
1
1
Table 1: Truth Table of Full Adder
Verilog HDL Code:

module faddonebit(a,b,cin,s,cout);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
wire [2:0] cy;
fadd fadd0(a[0],b[0],cin,s[0],cy[0]);
fadd fadd1(a[1],b[1],cy[0],s[1],cy[1]);
fadd fadd2(a[2],b[2],cy[1],s[2],cy[2]);
fadd fadd3(a[3],b[3],cy[2],s[3],cout);
endmodule
module fadd(a,b,cin,sum,cout);
input a;
input b;
input cin;
output sum;
output cout;
wire wa,wb,wc;
hadd hadd1(a,b,wa,wb);
hadd hadd2(wa,cin,sum,wc);
assign cout=wb|wc;
endmodule
module hadd(a,b,sum,cout);
input a;
input b;
output out;
output cout;
assign sum=a^b;
assign cout=a&b;
endmodule

#####################################################
#####################################################
NET "sum" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "cout" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "a" LOC = "L13" |
NET "b" LOC = "L14" |
NET "cin" LOC = "H18"
(SW) ====
Figure 3: RTL View of Full Adder
We have used three slide switches & two LEDs. The Input of Full Adder A, B, & Cin are
assigned to Slide Switches SW0, SW1 & SW2 respectively. The outputs of Full adder Sum
& Carry are assigned to LED0 & LED1 respectively.
Result:
All the outputs of the 4-bit Full Adder are verified with the help of truth table on Xilinx
Spartan-3E FPGA Starter Kit.
Date of Experiment:
EXPERIMENT 5
Objective:
Design and simulation of [8:1] MUX using VERILOG, and synthesis on FPGA.
(By using [4:1] & [2:1] MUX)
Overview:
In this lab, we are going to design a [1:8] MUX by using Verilog HDL. The Diagram for which
is given
below
Fig: 8X1 mux using 4X1 & 2X1mux
In electronics, a multiplexer (or mux) is a device that selects one of
several analog or digital input signals and forwards the selected input into a single line. A
multiplexer of 2n inputs has n select lines, which are used to select which input line to send to
the output.
Truth Table:
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Verilog HDL Code

module mux8x1(a,s ,out);
input[7:0]a;
input [2:0]s;
output out;
wire [1:0]w;
mux4x1 M1(a[0],a[1],a[2],a[3],s[2],s[1],w[0]);
mux4x1 M2(a[4],a[5],a[6],a[7],s[2],s[1],w[1]);
mux2x1 M3(w[0],w[1],s[0],out)
endmodule
module mux4x1(a,b,c,d,s1,s0,out);
input a;
input b;
input c;
input d;
input s1;
input s0;
output out;
assign out=s1?(s0?d:c):(s0?b:a);
endmodule
Output
D0
D1
D2
D3
D4
D5
D6
D7
module mux2x1(a,b,s0,out);
input a;
input b;
input s0;
output out;
assign out=s0?b:a;
endmodule
Figure : 8X1 mux using 4X1 & 2X1mux
We have used three slide switches & two LEDs. The Input of MUX is
A[1],A[2],A[3],A[4],A[5],A[6],A[7] are assigned to Slide Switches respectively. The outputs
of Full of MUX OUT is assigned to LED0 respectively.
Result:
We have successfully demonstrate [8:1] MUX using Verilog HDL on Spartan-3E FPGA
Starter Kit Board.
Date of Experiment:
EXPERIMENT- 6
Objective:
Design and simulation of 1x8DEMUX using VERILOG, and synthesis on FPGA.
Overview:
In this lab, we are going to design a 1x8DEMUXusing Verilog HDL.The data distributor,
known more commonly as a Demultiplexer or Demux for short, is the exact opposite of
the Multiplexer we saw in the previous tutorial. The demultiplexer takes one single input data
line and then switches it to any one of a number of individual output lines one at a time.
The demultiplexer converts a serial data signal at the input to a parallel data at its output lines
as shown below.
1-to-4 Channel De-multiplexer
Output Select
b
a
0
0
1
1
0
1
0
1
Data Output
Selected
A
B
C
D
The Boolean expression for this 1-to-4 Demultiplexer above with outputs A to D and data
select lines a, b is given as:
F = abA + abB + abC + abD
The function of the Demultiplexer is to switch one common data input line to any one of the
4 output data lines A to D in our example above. As with the multiplexer the individual solid
state switches are selected by the binary input address code on the output select pins a and
b as shown.
Demultiplexer Output Line Selection
As with the previous multiplexer circuit, adding more address line inputs it is possible to
switch more outputs giving a 1-to-2n data line outputs.
Figure 1: [1:8] DEMUX
Truth Table:
Clock Input Control Signal
Output
Cycle
I
S2 S1
S0 Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
1
1
1
2
1
0
1
0
0
0
1
1
1
1
1
1
3
1
0
1
1
0
0
0
1
1
1
1
1
4
1
1
0
0
0
0
0
0
1
1
1
1
5
1
1
0
1
0
0
0
0
0
1
1
1
6
1
1
1
0
0
0
0
0
0
0
1
1
7
1
1
1
1
0
0
0
0
0
0
0
1
Table 1: Truth Table of [1:8] DEMUX
Verilog HDL Code:

``timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//////////
// Company:
// Engineer:
//
// Create Date:
19:43:02 09/02/2014
// Design Name:
// Module Name:
demux1x8using1x4n1x2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
//////////
module demux1x8using1x4n1x2(input I,s0,s1,s2,
output [7:0] out);
wire w1,w2;
demux1x2 d1(I,s2,w1,w2);
demux1x4 d2(w1,s0,s1,out[0],out[1],out[2],out[3]);
demux1x4 d3(w2,s0,s1,out[4],out[5],out[6],out[7]);
endmodule
module demux1x2( input I,s, output o1,o2 );
assign o1=I&~s;
assign o2=I&s;
endmodule
module demux1x4( input I,s0,s1, output out0,out1,out2,out3 );
assign out0=I&~s1&~s0;
assign out1=I&~s1&s0;
assign out2=I&s1&~s0;
assign out3=I&s1&s0;
endmodule

#####################################################
#####################################################
NET "out[0]" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "out[1]" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "out[4]" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "out[5]" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
# ==== Slide Switches (SW) ====
NET "I" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "s0" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "s1" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "s2" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
Figure 3: RTL View of [1:8] DEMUX

We have used four slide switches & eight LEDs. The Input of I s0,s1& s2 are assigned
to Slide Switches L13, L14, H18, & N17 respectively. The SEVEN outputs of
1x8DEMUXout[7:0] aer assigned to LED7 to LED0 respectively.

Result:
All the outputs of the [1:8] DEMUX are verified with the help of truth table on Xilinx
Date of Experiment:
EXPERIMENT-7
Objective:
Design and simulation of CLOCK DIVIDER of 1 Hz using VERILOG, and synthesis on
FPGA.
Overview:
In this lab, we are going to design CLOCK DIVIDER of 1 Hz using Verilog HDL. The
Diagram for which is given below:
Diagram for CLOCK DIVIDER of 1 Hz :
The Digilab FPGA board has a built-in clock of frequency 50 MHz.

This clock is too fast for visual observations.
In this lab, we will be reducing the clock to 1 Hz by designing a clock
division circuitry. To use this clock circuit in future.
Verilog HDL Code:

module clk1hz(input clk,output reg clk1hz=0
);
reg [0:25]count;
initial count=0;
always@(negedge clk)
begin
count= count+1;
if(count==25000000)
begin
clk1hz=~clk1hz;
count=0;
end
else
clk1hz=clk1hz;
end
endmodule

#===Clock source======
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
#===Discrete LEDs=====
NET "clk1hz" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8
;
We have used one clock signal & one LED. The Inputs of CLOCK DIVIDER of 1hz is OnBoard 50 MHz Oscillator CLK_50MHz: (The clock is assign by FPGA PIN C9). The output
of CLOCK DIVIDER is assigned to LED0 (F12) .
Result:
We have successfully demonstrate CLOCK DIVIDER of 1 Hz using Verilog HDL on
Spartan-3E FPGA Starter Kit Board.
Date of Experiment:
EXPERIMENT- 8
Objective:
Design and simulation of 4 bit UP COUNTER & DOWN COUNTER using VERILOG, and
synthesis on FPGA.
Overview:
In this lab, we are going to design an Up down counter using Verilog HDL. The Diagram for
which is given below.
Figure 1: Up down counter using Gates

Generally most bidirectional counters can be made to change their count direction either up or
down at any point within their counting sequence. This is achieved by using an additional input
pin which determines the direction of the count, either Up or Down.
Figure 2: Block diagram of Up down counter

In our design When LOAD=1 counter will act as upcounter and when LOAD=0 counter will
act as a down counter but CLR input should be zero.if CLR=1,counter will become zero.
Verilog HDL Code:
module udcounter(ld ,clk,mode, d_in,clr,count
input mode,clk,clr,ld;
input [0:3]d_in;
output [0:3]count;
reg [0:3]count;
always @ (posedge clk)
if(ld)
count<=d_in;
else if (clr)
count<=0;
else
if (mode)
count<=count +1;
else
count<=count-1;
);
endmodule

# ==== Slide Switches (SW) ====Inputs
NET "ld" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
NET "clk" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "clr" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "mode" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
# ==== Push buttons ====Inputs

NET "d_in[3]" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "d_in[2]" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "d_in[1]" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "d_in[0]" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
# ==== Discrete LEDs
NET " count [3]" LOC
= 8 ;
= 8 ;
= 8 ;
8 ;
(LED) ====Outputs
= "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE
= "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE
= "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE
= "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
Figure 3: RTL View of Up down counter
Figure 4: Simulated waveform of Up down counter
We have used four slide switches ,four push buttons & seven LEDs. The inputs of 4-bit
up/down counter ld,mode,clr ,clk are assigned to Slide Switches SW0,SW, SW2, SW3,SW4
and d_in[0:3] assigned to push buttons respectively. The outputs of Seven segment display
decoder are assigned to Count[3], Count[2], Count[1], Count[0] are assigned to LED3, LED2,
LED1, LED0.

Result:
All the outputs of the Up down counter are verified with the help of truth table on Xilinx
Date of Experiment:
EXPERIMENT-9
Objective:
Design and simulation of 8 bit Serial In Parallel Out circuit using VERILOG, and synthesis on
FPGA.
Overview:
The Shift Register is another type of sequential logic circuit that can be used for the storage or
the transfer of data in the form of binary numbers. This sequential device loads the data present
on its inputs and then moves or shifts it to its output once every clock cycle, hence the name
shift register
In this lab, we are going to design Serial In Parallel Out using Verilog HDL. The Diagram
for which is given below:
Figure 1 Four Bit SIPO

As shown in figure, SIPO is having 4 D flip-flops connected serially. The serial input data is
entering from MSB and when the 1st data bit reaches to the last flip flop output, then it can be
taken parallel from QA, QB, QC, QD .
The above figure shows the working of the 4 bit SIPO.
Verilog HDL Code:

module SIPO8bit(input sin,clk, rst, ctrlin,
output [7:0] outb
);
reg clkin;
wire [7:0] out;
reg oen;
integer a;
initial a=0;
//reg [3:0] a=4'd15;
DFF
DFF
DFF
DFF
f1(sin, rst, clkin,out[0]);

f2(out[0], rst, clkin, out[1]);
DFF f5(out[3], rst, clkin, out[4]);

DFF f9(out[0], rst, oen,outb[0]);

always@(clk)
begin
if(ctrlin & a<16)
begin
oen=0;
a=a+1;
clkin=clk;
end
else
begin
if(a==16) begin
clkin=0;
oen=1;
a=0;
end
end
end
endmodule
module DFF(
input din,
input rst,
input clk,
output reg dout
);
always@(posedge clk or posedge rst)
begin
if(rst)
dout=0;
else
dout=din;
end
endmodule

#####################################################
#####################################################
NET "sin LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "clk LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "ctrlin LOC = "L17" | IOSTANDARD = LVTTL | PULLUP ;
NET "rst LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
# ==== Discrete LEDs
NET outb[7]" LOC =
;
NET outb[6]" LOC =
;
NET outb[5]" LOC =
8 ;
NET outb[4]" LOC =
8 ;
NET outb[3]" LOC =
8 ;
NET outb[2]" LOC =
8 ;
NET outb[1]" LOC =
8 ;
NET outb[0]" LOC =
;
(LED) ====Outputs
"F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8
"E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8
"D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
"C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
"F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
"E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
"E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
"F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8
We have used four slide switches & seven LEDs. The inputs of Seven segment display decoder
clkin, rst, sin, ctrlin are assigned to Slide Switches SW0,SW1,SW2 & SW3 respectively. The
outputs of Seven segment display decoder are assigned to outb[7], out [6], outb[5], out [4],
out [3], out [2], outb [1], outb[0] are assigned to LED7, LED6, LED5, LED4, LED3, LED2,
LED1, LED0.
Result:
We have successfully demonstrate 8 bit SIPO using Verilog HDL on Spartan-3E FPGA
Starter Kit Board.
Date of Experiment:
EXPERIMENT-10
Objective:
Design and simulation of 8 bit Parallel In Serial Out circuit using VERILOG, and synthesis on
FPGA.
Overview:
The Shift Register is another type of sequential logic circuit that can be used for the storage or
the transfer of data in the form of binary numbers. This sequential device loads the data present
on its inputs and then moves or shifts it to its output once every clock cycle, hence the name
shift register
In this lab, we are going to design Parallel In Serial Out using Verilog HDL. The Diagram
for which is given below:
Figure 1 Four Bit PISO

As shown in figure, PISO is having 4 D flip-flops connected serially. The parallel input data
is entering from the 2x1MUX and when the data is entered in parallel, then the output from
the Q can be taken at the next four clock pulses.
Figure 2
The above figure shows the working of the 8 bit PISO.
Verilog HDL Code:

module parallel_in_serial_out ( din ,clk ,reset ,load ,dout );
output dout ;
reg dout ;
reg [7:0] din ;
wire [7:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;
reg [7:0]temp;
always @ (posedge (clk))
begin
if (reset)
temp <= 1;
else if (load)
temp <= din;
else begin
dout <= temp[7];

temp <= {temp[6:0],1'b0};
end
end

#####################################################
#####################################################
NET "din LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "clk LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "load LOC = "L17" | IOSTANDARD = LVTTL | PULLUP ;
NET "rst LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
# ==== Discrete LEDs (LED) ====Outputs
NET dout LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
din, clk,load, rst are assigned to Slide Switches SW0,SW1,SW2 & SW3 respectively. The
outputs of Seven segment display decoder are assigned to dout is assigned to LED0.
Result:
We have successfully demonstrate 8 bit PISO using Verilog HDL on Spartan-3E FPGA
Starter Kit Board.
Date of Experiment:
EXPERIMENT-11
Objective:
Design and simulation of SEVEN SEGMENT DISPLAY DECODER using VERILOG and
synthesis on FPGA.
Overview:
In this lab, we are going to design a Seven segment display using Verilog HDL. The Diagram
for which is given below.
Figure 1: Seven segment display

A seven-segment display (SSD), or seven-segment indicator, is a form of electronic display
device for displaying decimal numerals that is an alternative to the more complex dot
matrix displays.Seven-segment displays are widely used in digital clocks, electronic meters,
basic calculators, and other electronic devices that display numerical information.
Figure 2: Seven segment display showing decimal values

In our design, we intially stored values for decimals in a 8 bit register and according to the
input given corresponding data stored in the specific address will be write into seven segement
display decoder
Verilog HDL Code:
module seven_seg(display,in );
output [6:0]display;
input[3:0]in;
reg [6:0]display;
always@(in)
begin
case(in)
4'b0000: display
4'b0001: display
4'b0010: display
4'b0011: display
4'b0100: display
4'b0101: display
4'b0110: display
4'b0111: display
4'b1000: display
4'b1001: display
default: display
endcase
end
endmodule
=
=
=
=
=
=
=
=
=
=
=
7'b1111110;
7'b0110000;
7'b1101101;
7'b1111001;
7'b0110011;
7'b1011011;
7'b1011111;
7'b1110000;
7'b1111111;
7'b1111011;
7'b0000000;

#####################################################
#####################################################
NET "in[3]" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP
NET "in[0]" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP
;
;
;
;

NET " display [7]" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE
= 8 ;
NET " display [6]" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE
= 8 ;
NET " display [5]" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW |
DRIVE = 8 ;
NET " display [4]" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW |
DRIVE = 8 ;
NET " display [3]" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW |
DRIVE = 8 ;
NET " display [2]" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW |
DRIVE = 8 ;
NET " display [1]" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW |
DRIVE = 8 ;
NET " display [0]" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE
= 8 ;
Figure 3: RTL View of Seven segment
Figure 4: Simulated waveform of Seven segment

in[3],in[2],in[1],in[0] are assigned to Slide Switches SW0,SW1,SW2 & SW3 respectively. The
outputs of Seven segment display decoder are assigned toout[8], display [7], display [6],
display[5], display [4], display [3], display [2], display [1], display [0] are assigned to LED7,
LED6, LED5, LED4, LED3, LED2, LED1, LED0.

Result:
All the outputs of the Seven segment display decoder are verified with the help of truth table
on Xilinx Spartan-3E FPGA Starter Kit.
Date of Experiment:
EXPERIMENT-12
Objective:
Design and simulation of 4 bit Multiplier using VERILOG, and synthesis on FPGA.
Overview:
In this lab, we are going to design a 4 bit multiplier using Verilog HDL. The Diagram for
which is given below.
Figure 1: 4 bit Multiplier

A binary multiplier is an electronic circuit used in digital electronics, such as a computer,
to multiply two binary numbers. It is built using binary adders. A variety of computer
arithmetic techniques can be used to implement a digital multiplier. Most techniques involve
computing a set of partial products, and then summing the partial products together.
A binary computer does exactly the same, but with binary numbers. In binary encoding each
long number is multiplied by one digit (either 0 or 1), and that is much easier than in decimal,
as the product by 0 or 1 is just 0 or the same number. Therefore, the multiplication of two
binary numbers comes down to calculating partial products (which are 0 or the first number),
shifting them left, and then adding them together
1011 (this is 11 in decimal)
x 1110 (this is 14 in decimal)
======
0000 (this is 1011 x 0)
1011 (this is 1011 x 1, shifted one position to the left)
1011 (this is 1011 x 1, shifted two positions to the left)
+ 1011 (this is 1011 x 1, shifted three positions to the left)
=========
10011010 (this is 154 in decimal)
Verilog HDL Code:

module multiplier(input[3:0]a,input [3:0]b,output reg [7:0]out);
wire [3:0]p;
wire [3:0]q;
wire [3:0]r;
wire [3:0]s;
reg [7:0]w;
reg [7:0]x;
reg [7:0]y;
reg[7:0]z;
assign p=b[0]?a:0;
assign q=b[1]?a:0;
assign r=b[2]?a:0;
assign s=b[3]?a:0;
always@(a[0],a[1],a[2],a[3],b[0],b[1],b[2],b[3])
begin
w={0000,p};
x={0000,q};
x=x<<1;
y={0000,r};
y=y<<2;
z={0000,s};
z=z<<3;
out=(w+x+y+z);
end
endmodule

#####################################################
#####################################################
NET "a[3]" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
NET "a[2]" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "a[1]" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "a[0]" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
# ==== Push buttons ====Inputs
NET "b[3]" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "b[2]" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "[1]" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "[0]" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
NET " out [6]" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8
;
NET " out [5]" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
8 ;
NET " out [4]" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
8 ;
NET " out [3]" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
8 ;
NET " out [2]" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
8 ;
NET " out [1]" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE =
8 ;
NET " out [0]" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8
;
Figure 3: RTL View of 4 bit Multiplier
Figure 4: Simulated waveform of 4 bit Multiplier

We have used four slide switches,four push buttons and seven LEDs. The inputs of Seven
segment display decoder a[3],a[2],a[1],a[0] and b[3],b[2],b[1],b[0] are assigned to Slide
Switches SW0,SW1,SW2 & SW4 and b[3],b[2],b[1],b[0] are assigned to push buttons
respectively. The outputs of 4-bit multiplier are assigned to out [7], out [6], out [5], out [4],
out [3], out [2], out [1], out[0] are assigned to LED7, LED6, LED5, LED4, LED3, LED2,
LED1, LED0.

Result:
All the outputs of the 4 bit Multiplier are verified with the help of truth table on Xilinx Spartan3E FPGA Starter Kit.
Date of Experiment:

Verilog Basic Experiments

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INDEX

Truth Table for AND GATE :

Diagram for OR GATE :

Truth Table for OR GATE:

Diagram for NAND GATE :

Truth Table for NAND GATE :

Diagram for NOR GATE :

Truth Table for NOR GATE:

Diagram for XOR GATE :

Truth Table for XOR GATE:

Truth Table for XNOR GATE:

Verilog HDL Code:

User Constraints File (UCF):

RTL View of the Design:

Signature of Class Teacher

Fig: D Flip Flop.

User Constraints File (UCF):

# ==== Discrete LEDs (LED) ====

RTL View of the Design:

Figure 4: Slide Switches & Discrete LEDs

Signature of Class Teacher

Figure 1: Full Adder using Gates

Figure 2: A Block Diagram of the circuit

Table 1: Truth Table of Full Adder

User Constraints File (UCF):

# ==== Discrete LEDs (LED) ====

RTL View of the Design:

Figure 3: RTL View of Full Adder

Figure 4: Slide Switches & Discrete LEDs

Signature of Class Teacher

Figure 1: 4-bit Full Adder using Gates

Figure 2: A Block Diagram of the circuit

Table 1: Truth Table of Full Adder

Verilog HDL Code:

User Constraints File (UCF):

RTL View of the Design:

Figure 3: RTL View of Full Adder

Signature of Class Teacher

Fig: 8X1 mux using 4X1 & 2X1mux

Verilog HDL Code

RTL View of the Design:

Figure : 8X1 mux using 4X1 & 2X1mux

Figure 4: Slide Switches & Discrete LEDs

Signature of Class Teacher

Figure 1: [1:8] DEMUX

Verilog HDL Code:

User Constraints File (UCF):

RTL View of the Design:

Figure 3: RTL View of [1:8] DEMUX

Figure 4: Slide Switches & Discrete LEDs

Signature of Class Teacher

Diagram for CLOCK DIVIDER of 1 Hz :

The Digilab FPGA board has a built-in clock of frequency 50 MHz.

Verilog HDL Code:

User Constraints File (UCF):

RTL View of the Design:

Signature of Class Teacher

Figure 1: Up down counter using Gates

Figure 2: Block diagram of Up down counter

User Constraints File (UCF):

# ==== Push buttons ====Inputs

RTL View of the Design:

Figure 3: RTL View of Up down counter

Figure 4: Simulated waveform of Up down counter