GATE + ISRO 2015

( Quick Reference )
Computer Science & Information Technology
( Digital Logic + Computer Organization )
( First Edition )

REJIN R

ARAVIND PRASAD A G

MTech CSE,

MTech CSE,

College of Engineering, Trivandrum

College of Engineering, Trivandrum

BTech IT,

BTech CSE,

Govt. Engineering College, Idukki

College of Engineering, Chengannur

 There is nothing new under the sun . It has all been done before.
[A Study in Scarlet] Sir Arthur Conan Doyle

Preface
Dear Reader,
Please hang on a minute and just read through before proceeding further.
If you want to know the answer of any Computer Organization or Digital Logic previous years
GATE / ISRO question, dont go and search the Google!, just search through this book.
This book is dedicated to all those preparing for GATE, ISRO and other competitive examinations. It is organized
into two parts covering subjects Digital logic & Computer organization. First part on Digital logic and second part
on Computer organization.
Each part is futher divided into sections. Each section includes the required theory part in brief as well as the
previous years GATE and ISRO questions with explanations. We tried to include GATE questions from 1992 till
2014 and ISRO questions from 2007 till 2014. Each and every question is answered in simple and lucid manner.
Pattern based question ordering is used in this book. Questions having similar structure are grouped in a manner
that the answers can be linked. We believe, Pattern based question ordering will help you to improve your skills
in problem solving in those areas described in the book.
The theory parts in brief will help you as a Quick reference to revise the concepts and formulas. We hope, this
book will give you a clear insight into the solutions and the way of solving problems.
Constructive suggestion and criticism always go a long way in enhancing any endeavor. We request you to respond
with your valuable comment / views / feedback for the betterment of this book at:
https://www.facebook.com/gateplusisro
Wish you all the best.

REJIN R

ARAVIND PRASAD A G

Part I

D I G I TA L L O G I C

1
SEQUENTIAL CIRCUITS

A sequential circuit is a digital logic circuit, whose output value depends on present and past inputs. It includes
a combinational circuit and memory element.

1.1

flip-flops

A flip-flop circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit) until
directed by an input signal to switch states.
1.1.1

Basic Flip-flop circuits

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1.1.2

Note:

Duty cycle : It is the percentage of one period in which signal is active. Duty cycle of 60% means the
signal is ON for 60% of time and OFF for 40% of time.
Propagation delay : It is the time a flip-flop takes to change its output after the clock edge.
Race around condition : In JK flip flop, when J=1 and K=1 a toggling occurs. Since clock pulse
is more than propagation delay, within on clock pulse the output keep on toggling again and again and
output become indeterminate. This situation is known as race around condition.

Master Slave Flip flops : This is a cascade of flip flop arrangement, in which first one (master) responds
with clock high and second (slave) responds with clock low. Thus the final output changes only when
clock is low. Thus race around condition is get eliminated.

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1.1.3 Flip-flops - [GATE Questions]

1. In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result
in

(a) Q = 0, Q' = 1

(b) Q = 1, Q' = 0

(c) Q = 1, Q' = 1

(d) indeterminate state

[GATE-2004 CS] [1 mark] [ISRO-2007]

2. Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may
lead to an oscillation?

(a) 11, 00

(b) 01, 10

(c) 10, 01

(d) 00, 11
[GATE-2007 IT] [1 mark]

3. In the sequential circuit shown below, if the initial value of the output Q1 Q0 is 00, what are the next four
values of Q1 Q0 ?

(a) 11, 10, 01, 00

(b) 10, 11, 01, 00

(c) 10, 00, 01, 11

(d) 11, 10, 00, 01

[GATE-2010 CS&IT] [2 mark] [ISRO-2014]

4. The following arrangement of master-slave flip flops

has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),

(a) 1, 0

(b) 1, 1

(c) 0, 0

(d) 0, 1
[GATE-2000 CS] [2 mark]

15

5. The following synchronous sequential circuit built using JK flip-flops is initialized with Q2 Q1 Q0 = 000.

The state sequence for this circuit for the next 3 clock cycles is

(a) 001, 010, 011

(b) 111, 110, 101

(c) 100, 110, 111

(d) 100, 011, 001

[GATE-2014 SET-3] [2 mark]

6. Consider the circuit in the diagram. The operator represents Ex-OR. The D flip-flops are initialized to
zeroes (cleared)

The following data: 100110000 is supplied to the "data" terminal in nine clock cycles. After that the values
of q2 q1 q0 are :

(a) 000

(b) 001

(c) 010

(d) 101
[GATE-2006 CS] [2 mark]

7. Consider the following state diagram and its realization by a JK flip-flop.

The combinational circuit generates J and K in terms of x,y and Q. The Boolean expression for J and K are:

(a) x y and x y
(c) x y and x y

(b) x y and x y
(d) x y and x y
[GATE-2008 IT] [2 mark]

16

8. You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only
at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay
the phase of f by 180 ?
(a)

(b)

(c)

(d)

[GATE-2006 CS] [1 mark]

9. Consider the following circuit.

The flip-flops are positive edge triggered D flip-flops. Each state is designated as a two bit string Q0 Q1 . Let
the initial state be 00. The state transition sequence is:

(a)

(b)

(c)

(d)

[GATE-2005 CS] [2 mark]

17

10. Consider the following circuit with initial state Q0 =Q1 =0. The D Flip-flops are positive edge triggered and
have set up times 20 ns and hold times 0.

Consider the following timing diagrams of X and C; the clock period of C40 ns.
Which one is the correct plot of Y?

[GATE-2001 CS] [2 mark]

11. Consider the following circuit involving a positive edge triggered D flip-flop.

Consider the following timing diagram. Let Ai represent the logic level on the line A in ith clock period.

Let A represent the complement of A. The correct output sequence on Y over the clock period 1 through 5
is

(a) A0 A1 A1 'A3 A4

(b) A0 A1 A2 'A3 A4

(c) A1 A2 A2 'A3 A4

(d) A1 A2 'A3 A4 A5 '

[GATE-2005 CS] [2 mark]

18

1.1.4 Flip-flops - [ISRO Questions]

1. In an RS flip-flop, if the S line(Set line) is set high(1) and the R line(Reset line) is set low(0), then the state
of the flip flop is

(a) Set to 1

(b) Set to 0

(c) No change in state

(d) Forbidden
[ISRO - 2011 CS]

2. The characteristic equation of an SR flip flop is given by

(a) Qn+1 =S+RQn

(b) Qn+1 =RQn +S Qn

(c) Qn+1 =S +RQn

(d) Qn+1 =S+RQn

[ISRO - 2007 CS]

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1.2

registers & counters

1.2.1

Registers

Registers are memory devices that can be used to store more than one bit of information.

Shift Registers
A register that provide the ability to shift its contents is known as shift registers.

Linear Feedback Shift Registers

A Linear Feedback Shift Register is a shift register whose input bits is a linear function of previous
state.

In the above example input bit at A3 is determined by XORed combination of bits A0 and A2 , with every
operation a bit is shifted right.
1.2.2

Counters

Counters are sequential circuits which goes through a sequence of states upon application of input
pulses. Modulus of a counter is the number of unique state a counter may have.
Two types of counters:
Ripple counter (Asynchronous)
Synchronous counter

Ripple counter
In a Ripple counter, the flip flop output transition serves as a source for triggering other flip flops.

20

Synchronous counters
In synchronous sequential circuits, all the flip flops clock input are applied to the same clock signal,
so that all flip flop output changes at the same time.

Ring counter
A Ring counter is composed of a circular shift register, where the output of last shift register is fed
back to input of first register. This counter circulates a single 1 around the ring.

A ring counter can also be represented using a combination of up counter and n to 2n decoder circuit.

In a ring counter, count is read by noting which flip flop is in state 1. The output pulse of one stage
is delayed by a time T from a pulse in the preceding stage. Thus a ring counter is analogous to Stepping
switch where each triggering pulse causes an advance of switch by one step.
Pattern produced by Ring counter : 1000, 0100, 0010, 0001, 1000, ....

NOTE :
Ring counter is the costliest synchronous
counter.
With n flip flops maximum modulus = N

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Johnson counter (Twisted Ring counter)

Johnson counter is a variation of Ring counter obtained by taking feedback output from Q (instead
of Q in Ring counter), to the first stage.

Pattern in Johnson counter : 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000, ....

Note :
Johnson counter performs gray counting
Maximum modulus = 2n

1.2.3 Counters - [GATE Questions]

1. What is the final value stored in the linear feedback shift register if the input is 101101?

(a) 0110

(b) 1011

(c) 1101

(d) 1111
[GATE-2007 IT] [2 mark]

2. The minimum number of D flip-flops needed to design a mod-258 counter is

(a) 9

(b) 8

(c) 512

(d) 258
[GATE-2011 CS&IT] [1 mark]

3. How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111
(rightmost bit is the LSB)?

(a) 134

(b) 133

(c) 124

(d) 123
[GATE-2005 IT] [1 mark]

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4. Let k = 2n . A circuit is built by giving the output of an n-bit binary counter as input to an bit decoder. This
circuit is equivalent to a

(a) k-bit binary up counter

(b) k-bit binary down counter

(c) k-bit ring counter

(d) k-bit Johnson counter

[GATE-2014 SET-2] [1 mark]

5. For the initial state of 000, the function performed by the arrangement of the J-K flip flops in figure is :

(a) Shift Register

(b) Mod-3 counter

(c) Mod-6 counter

(d) Mod-2 counter

[GATE-1993 CS] [2 mark]

Common Data Questions[6-7]

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

6. If all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) represented
by PQR generated by the counter?

(a) 3

(b) 4

(c) 5

(d) 6
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7. If at some instance prior to the occurance of the clock edge, P, Q and R have a value 0, 1 and 0 respectively,
what shall be the value of PQR after the clock edge?

(a) 000

(b) 001

(c) 010

(d) 011
[GATE-2011 CS&IT] [2 mark]

8. The control signal function of a 4-bit binary counter are given below( where X is "dont care"):

The counter is connected as follows: Assume that the counter and gate delays are negligible. If the counter

starts at 0, then it cycles through the following sequence.

(a) 0, 3, 4
(c) 0, 1, 2, 3, 4

(b) 0, 3, 4, 5
(d) 0, 1, 2, 3, 4, 5
[GATE-2007 CS] [2 mark]

9. Consider the circuit given below with initial state Q0 = 1, Q1 = Q2 = 0. The state of the circuit is given by
the value 4Q2 + 2Q1 + Q0

Which one of the following is correct state sequence of the circuit?

(a) 1,3,4,6,7,5,2

(b) 1,2,5,3,7,6,4

(c) 1,2,7,3,5,6,4

(d) 1,6,5,7,2,3,4
[GATE-2001 CS] [2 mark]

24

10. Consider the partial implementation of a 2-bit counter using T flip-flops following the sequence 0-2-3-1-0,
as shown below.

To complete the circuit, the input X should be

(a) Q2 '

(b) Q2 +Q1

(c) (Q1 Q2 )'

(d) Q1 Q2
[GATE-2004 CS] [2 mark]

1.2.4 Counters - [ISRO Questions]

1. Ring counter is analogous to

(a) Toggle Switch

(c) Stepping Switch

(b) Latch
(d) SR ip op
[ISRO - 2007 CS]

2. In a three stage counter, using RS flip flops what will be the value of the counter after giving 9 pulses to
input? Assume that the value of counter before giving any pulses is 1.

(a) 1

(b) 2

(c) 9

(d) 10
[ISRO - 2013 CS]

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1.3

Sequential Circuits Answers

1.3.1 Flip-flops - [GATE]

(1) d

(2) a

(3) a

(4) a

(8) c

(9) d

(10) a

(11) a

(5) c

(6) c

(7) d

(5) c

(6) b

(7) d

1.3.2 Flip-flops - [ISRO]

(1) a

(2) d

1.3.3 Registers & Counters - [GATE]

(1) a

(2) a

(3) d

(8) c

(9) b

(10) d

1.3.4 Registers & Counters - [ISRO]

(1) c

26

(2) b

(4) c

1.4

Answers with Explanations

1.4.1 Flip-flops - [GATE]

1. Ans: (d) indeterminate state
2. Ans: (a) 11, 00
In a cross coupled R-S flip-flop realized using NAND gate, for input 11 the output will be the previous output.
Input 00 leads to oscillation.
3. Ans: (a) 11, 10, 01, 00

Initial values of Q1 Q0 = 00

Next state of Q0 = Q0( prev)

[ with input 1 output of T ip-op toggles.]

Q0 is given as clock input of second T ip op.

Next state of Q1 = Q1( prev)

[ If Q0 changes from 0 to 1.]

Next state of Q1 = Q1( prev)

[ If Q0 changes from 1 to 0.]

4. Ans: (a) 1, 0

In the above configuration input of D flip flop is the output P of JK flip flop. Since, 1 is constantly given as
input to JK flip flop, each time the output toggles.

27

5. Ans: (c) 100, 110, 111

Initial values are Q2 Q1 Q0 = 0 0 0

The state sequence for next 3 clock cycles is given by :

6. Ans: (c) 010

28

7. Ans: (d) x y and x y

From the above table:

P
P
J(X,Y,Q) = (2,4) + (1,3,5,7)

J = XY+XY = XY

K(X,Y,Q) =

P
P
(3,5) + (0,2,4,6)

K = XY+XY = XY

29

8. Ans: (c)

9. Ans: (d)

State transition sequence of Q0 Q1 is :

30

10. Ans: (a)

11. Ans: (a) A0 A1 A1 A3 A4

From the given figure: Ai X + Q.X

Answer is (a) A0 A1 A1 A3 A4
1.4.2 Flip-flops - [ISRO]
1. Ans: (a) Set to 1
2. Ans: (d) Qn+1 =S+RQn

31

1.4.3 Counters - [GATE]

1. Ans: (a) 0110

2. Ans: (a) 9
A mod -258 counter counts from 0 to 257.
Number of bits required = d log2 257 e = 9
Number of D flip flops required = 9
3. Ans: (d) 123
(10101100)2 = (172)10
(00100111)2 = (39)10
Since this is an 8 bit counter it counts from 0 to 255.
The counter counts from 172 to 255
(83 pulses)
Then from 0 to 39
(40 pulses)
Total number of pulses = 40+83 = 123
4. Ans: (c) k-bit ring counter
5. Ans: (c) Mod-6 counter
The given counter is Johnson counter.
Number of flip flops, n = 3
With n flip flops maximum mod = 2n = 6
6. Ans: (b) 4
From the figure,
PNextstate = R
QNextstate = P + R
RNextstate = QR
Given that, all the flip flops were reset to 0 on power on.

Number of states = 4.
7. Ans: (d) 011
From the above answer it is clear that, if current state is 010 then next state will be 011
32

8. Ans: (c) 0, 1, 2, 3, 4
Here count starts from 0. Counter counts next until clear = 1. From the above configuration, clear =1 when
A3 and A1 becomes 1. i.e., 0101 (5).
The given counter is a mod-5 counter which counts from 0 to 4.
The sequence is (c) 0, 1, 2, 3, 4
9. Ans: (b) 1, 2, 5, 3, 7, 6, 4

10. Ans: (d) Q1 Q2

1.4.4 Counters - [ISRO]

1. Ans: (c) Stepping Switch
2. Ans: (b) 2
Since the given counter is three stage counter, it can count from 0 to 7 ( 23 = 8).
Initially the value is 1. By applying first 6 pulse it will count upto 7. For the next 3 pulses it will count: 0, 1
and 2.
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