Addressing Modes

ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

Operation

Add with Carry

A (A) + (M) + (C)

Add without Carry

A (A) + (M)

Object Code

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

A9
B9
C9
D9
E9
F9
9E D9
9E E9

ii
dd
hh ll
ee ff
ff

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

AB
BB
CB
DB
EB
FB
9E DB
9E EB

ii
dd
hh ll
ee ff
ff

ee ff
ff

ee ff
ff

Cycles

Source
Form

Address
Mode

Table 4-10. Instruction Set Summary (Sheet 1 of 8)

Affect on CCR
Cyc-by-Cyc
Details
V11H INZC

2
3
4
4
3
2
5
4

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

1 1

2
3
4
4
3
2
5
4

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

1 1

AIS #opr8i

Add Immediate Value (Signed) to

Stack Pointer
SP (SP) + (M)

IMM

A7 ii

pp

1 1

AIX #opr8i

Add Immediate Value (Signed) to

Index Register (H:X)
H:X (H:X) + (M)

IMM

AF ii

pp

1 1

Logical AND
A (A) & (M)

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

A4
B4
C4
D4
E4
F4
9E D4
9E E4

2
3
4
4
3
2
5
4

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

0 1 1

DIR
INH
INH
IX1
IX
SP1

38 dd
48
58
68 ff
78
9E 68 ff

4
1
1
4
3
5

prwp
p
p
pprw
prw
ppprw

1 1

DIR
INH
INH
IX1
IX
SP1

37 dd
47
57
67 ff
77
9E 67 ff

4
1
1
4
3
5

prwp
p
p
pprw
prw
ppprw

1 1

Branch if Carry Bit Clear

(if C = 0)

REL

24 rr

pdp

1 1

Clear Bit n in Memory

(Mn 0)

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

11
13
15
17
19
1B
1D
1F

4
4
4
4
4
4
4
4

prwp
prwp
prwp
prwp
prwp
prwp
prwp
prwp

1 1

AND
AND
AND
AND
AND
AND
AND
AND

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
BCC rel

BCLR n,opr8a

Arithmetic Shift Left

C

0
b7

b0

(Same as LSL)
Arithmetic Shift Right
C
b7

b0

ii
dd
hh ll
ee ff
ff
ee ff
ff

dd
dd
dd
dd
dd
dd
dd
dd

CPU08 Central Processor Unit Reference Manual, Rev. 4

50

Freescale Semiconductor

Instruction Set Summary

Operation

Object Code

Cycles

Source
Form

Address
Mode

Table 4-10. Instruction Set Summary (Sheet 2 of 8)

Affect on CCR
Cyc-by-Cyc
Details
V11H INZC

Branch if Carry Bit Set (if C = 1)

(Same as BLO)

REL

25 rr

pdp

1 1

BEQ rel

Branch if Equal (if Z = 1)

REL

27 rr

pdp

1 1

BGE rel

Branch if Greater Than or Equal To

(if N V = 0) (Signed)

REL

90 rr

pdp

1 1

BGT rel

Branch if Greater Than (if Z | (N V) = 0)

(Signed)

REL

92 rr

pdp

1 1

BCS rel

BHCC rel

Branch if Half Carry Bit Clear (if H = 0)

REL

28 rr

pdp

1 1

BHCS rel

Branch if Half Carry Bit Set (if H = 1)

REL

29 rr

pdp

1 1

BHI rel

Branch if Higher (if C | Z = 0)

REL

22 rr

pdp

1 1

BHS rel

Branch if Higher or Same (if C = 0)

(Same as BCC)

REL

24 rr

pdp

1 1

BIH rel

Branch if IRQ Pin High (if IRQ pin = 1)

REL

2F rr

pdp

1 1

BIL rel

Branch if IRQ Pin Low (if IRQ pin = 0)

REL

2E rr

pdp

1 1

Bit Test
(A) & (M)
(CCR Updated but Operands Not Changed)

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

2
3
4
4
3
2
5
4

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

0 1 1

pdp

1 1

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

BLE rel

Branch if Less Than or Equal To

(if Z | (N V) = 1) (Signed)

REL

A5
B5
C5
D5
E5
F5
9E D5
9E E5

ii
dd
hh ll
ee ff
ff
ee ff
ff

93 rr

BLO rel

Branch if Lower (if C = 1) (Same as BCS)

REL

25 rr

pdp

1 1

BLS rel

Branch if Lower or Same (if C | Z = 1)

REL

23 rr

pdp

1 1

BLT rel

Branch if Less Than (if N V = 1) (Signed)

REL

91 rr

pdp

1 1

BMC rel

Branch if Interrupt Mask Clear (if I = 0)

REL

2C rr

pdp

1 1

BMI rel

Branch if Minus (if N = 1)

REL

2B rr

pdp

1 1

BMS rel

Branch if Interrupt Mask Set (if I = 1)

REL

2D rr

pdp

1 1

BNE rel

Branch if Not Equal (if Z = 0)

REL

26 rr

pdp

1 1

BPL rel

Branch if Plus (if N = 0)

REL

2A rr

pdp

1 1

BRA rel

Branch Always (if I = 1)

REL

20 rr

pdp

1 1

BRCLR n,opr8a,rel

Branch if Bit n in Memory Clear (if (Mn) = 0)

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

01
03
05
07
09
0B
0D
0F

5
5
5
5
5
5
5
5

prpdp
prpdp
prpdp
prpdp
prpdp
prpdp
prpdp
prpdp

1 1

BRN rel

Branch Never (if I = 0)

REL

21 rr

pdp

1 1

dd
dd
dd
dd
dd
dd
dd
dd

rr
rr
rr
rr
rr
rr
rr
rr

CPU08 Central Processor Unit Reference Manual, Rev. 4

Freescale Semiconductor

51

Addressing Modes

Operation

Object Code

5
5
5
5
5
5
5
5

prpdp
prpdp
prpdp
prpdp
prpdp
prpdp
prpdp
prpdp

1 1

dd
dd
dd
dd
dd
dd
dd
dd

4
4
4
4
4
4
4
4

prwp
prwp
prwp
prwp
prwp
prwp
prwp
prwp

1 1

AD rr

pssp

1 1

5
4
4
5
4
6

pprdp
ppdp
ppdp
pprdp
prdp
ppprdp

1 1

1 1 0

Branch if Bit n in Memory Set (if (Mn) = 1)

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

00
02
04
06
08
0A
0C
0E

dd
dd
dd
dd
dd
dd
dd
dd

BSET n,opr8a

Set Bit n in Memory (Mn 1)

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

10
12
14
16
18
1A
1C
1E

BSR rel

Branch to Subroutine
PC (PC) + $0002
push (PCL); SP (SP) $0001
push (PCH); SP (SP) $0001
PC (PC) + rel

REL

BRSET n,opr8a,rel

CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel

Compare and...

Branch if (A) = (M)

Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)

CLC

Clear Carry Bit (C 0)

CLI

Clear Interrupt Mask Bit (I 0)

CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP

Clear

CMP
CMP
CMP
CMP
CMP
CMP
CMP
CMP

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

M $00
A $00
X $00
H $00
M $00
M $00
M $00

Compare Accumulator with Memory

AM
(CCR Updated But Operands Not Changed)

DIR
IMM
IMM
IX1+
IX+
SP1
INH

Affect on CCR
Cyc-by-Cyc
Details
V11H INZC

Cycles

Source
Form

Address
Mode

Table 4-10. Instruction Set Summary (Sheet 3 of 8)

31
41
51
61
71
9E 61

dd
ii
ii
ff
rr
ff

rr
rr
rr
rr
rr
rr
rr
rr

rr
rr
rr
rr
rr

98

INH

9A

pd

1 1 0

DIR
INH
INH
INH
IX1
IX
SP1

3F dd
4F
5F
8C
6F ff
7F
9E 6F ff

3
1
1
1
3
2
4

pwp
p
p
p
ppw
pw
pppw

0 1 1 0 1

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

A1
B1
C1
D1
E1
F1
9E D1
9E E1

2
3
4
4
3
2
5
4

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

1 1

33 dd
43
53
63 ff
73
9E 63 ff

4
1
1
4
3
5

prwp
p
p
pprw
prw
ppprw

0 1 1

3
4

ppp
prrp

COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP

Complement
M (M)= $FF (M)
(Ones Complement) A (A) = $FF (A)
X (X) = $FF (X)
M (M) = $FF (M)
M (M) = $FF (M)
M (M) = $FF (M)

DIR
INH
INH
IX1
IX
SP1

CPHX #opr
CPHX opr

Compare Index Register (H:X) with Memory

(H:X) (M:M + $0001)
(CCR Updated But Operands Not Changed)

IMM
DIR

ii
dd
hh ll
ee ff
ff
ee ff
ff

65 ii jj
75 dd

1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4

52

Freescale Semiconductor

Instruction Set Summary

CPX
CPX
CPX
CPX
CPX
CPX
CPX
CPX

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

Operation

IMM
DIR
EXT
Compare X (Index Register Low) with Memory
IX2
XM
IX1
(CCR Updated But Operands Not Changed)
IX
SP2
SP1

Object Code
A3
B3
C3
D3
E3
F3
9E D3
9E E3

DAA

Decimal Adjust Accumulator

After ADD or ADC of BCD Values

INH

72

DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ oprx8,SP,rel

DIR
INH
Decrement A, X, or M and Branch if Not Zero
INH
(if (result) 0)
IX1
DBNZX Affects X Not H
IX
SP1

3B
4B
5B
6B
7B
9E 6B

DEC opr8a
DECA
DECX
DEC oprx8,X
DEC ,X
DEC oprx8,SP

Decrement

Divide
A (H:A)(X); H Remainder

DIV
EOR
EOR
EOR
EOR
EOR
EOR
EOR
EOR

M (M) $01
A (A) $01
X (X) $01
M (M) $01
M (M) $01
M (M) $01

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP

Exclusive OR Memory with Accumulator

A (A M)

Increment

M (M) + $01
A (A) + $01
X (X) + $01
M (M) + $01
M (M) + $01
M (M) + $01

ii
dd
hh ll
ee ff
ff
ee ff
ff

dd rr
rr
rr
ff rr
rr
ff rr

Cycles

Source
Form

Address
Mode

Table 4-10. Instruction Set Summary (Sheet 4 of 8)

Affect on CCR
Cyc-by-Cyc
Details
V11H INZC

2
3
4
4
3
2
5
4

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

pp

U 1 1

5
3
3
5
4
6

pprwp
pdp
pdp
pprwp
prwp
ppprwp

1 1

1 1

DIR
INH
INH
IX1
IX
SP1

3A dd
4A
5A
6A ff
7A
9E 6A ff

4
1
1
4
3
5

prwp
p
p
pprw
prw
ppprw

INH

52

pdpdddd

1 1

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

A8
B8
C8
D8
E8
F8
9E D8
9E E8

2
3
4
4
3
2
5
4

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

0 1 1

DIR
INH
INH
IX1
IX
SP1

3C dd
4C
5C
6C ff
7C
9E 6C ff

4
1
1
4
3
5

prwp
p
p
pprw
prw
ppprw

1 1

BC
CC
DC
EC
FC

dd
hh ll
ee ff
ff

2
3
4
3
2

pp
ppp
ppdp
pdp
pp

1 1

BD
CD
DD
ED
FD

dd
hh ll
ee ff
ff

4
5
6
5
4

pssp
ppssp
ppssdp
pssdp
pssp

1 1

JMP
JMP
JMP
JMP
JMP

opr8a
opr16a
oprx16,X
oprx8,X
,X

Jump
PC Jump Address

DIR
EXT
IX2
IX1
IX

JSR
JSR
JSR
JSR
JSR

opr8a
opr16a
oprx16,X
oprx8,X
,X

Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3)
Push (PCL); SP (SP) $0001
Push (PCH); SP (SP) $0001
PC Unconditional Address

DIR
EXT
IX2
IX1
IX

ii
dd
hh ll
ee ff
ff
ee ff
ff

1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4

Freescale Semiconductor

53

Addressing Modes

LDA
LDA
LDA
LDA
LDA
LDA
LDA
LDA

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

LDHX #opr
LDHX opr
LDX
LDX
LDX
LDX
LDX
LDX
LDX
LDX

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP

Operation

Load Accumulator from Memory

A (M)

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

Object Code

Affect on CCR
Cyc-by-Cyc
Details
V11H INZC

Cycles

Source
Form

Address
Mode

Table 4-10. Instruction Set Summary (Sheet 5 of 8)

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

0 1 1

ee ff
ff

2
3
4
4
3
2
5
4

45 ii jj
55 dd

3
4

ppp
prrp

0 1 1

ii
dd
hh ll
ee ff
ff

2
3
4
4
3
2
5
4

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

0 1 1

A6
B6
C6
D6
E6
F6
9E D6
9E E6

ii
dd
hh ll
ee ff
ff

Load Index Register (H:X)

H:X (M:M + $0001)

IMM
DIR

Load X (Index Register Low) from Memory

X (M)

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

AE
BE
CE
DE
EE
FE
9E DE
9E EE

DIR
INH
INH
IX1
IX
SP1

38 dd
48
58
68 ff
78
9E 68 ff

4
1
1
4
3
5

prwp
p
p
pprw
prw
ppprw

1 1

DIR
INH
INH
IX1
IX
SP1

34 dd
44
54
64 ff
74
9E 64 ff

4
1
1
4
3
5

prwp
p
p
pprw
prw
ppprw

1 1 0

5
4
4
4

prpwp
prwp
ppwp
prwp

0 1 1

1 1 0 0

Logical Shift Left

C

0
b7

b0

(Same as ASL)
Logical Shift Right
0

C
b7

b0

ee ff
ff

MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a

Move
(M)destination (M)source
In IX+/DIR and DIR/IX+ Modes,
H:X (H:X) + $0001

DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR

4E
5E
6E
7E

MUL

Unsigned multiply
X:A (X) (A)

INH

42

ppddd

NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP

Negate
M (M) = $00 (M)
(Twos Complement) A (A) = $00 (A)
X (X) = $00 (X)
M (M) = $00 (M)
M (M) = $00 (M)
M (M) = $00 (M)

DIR
INH
INH
IX1
IX
SP1

30 dd
40
50
60 ff
70
9E 60 ff

4
1
1
4
3
5

prwp
p
p
pprw
prw
ppprw

NOP

No Operation Uses 1 Bus Cycle

INH

9D

1 1

NSA

Nibble Swap Accumulator

A (A[3:0]:A[7:4])

INH

62

ppd

1 1

Inclusive OR Accumulator and Memory

A (A) | (M)

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

AA
BA
CA
DA
EA
FA
9E DA
9E EA

2
3
4
4
3
2
5
4

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

0 1 1

ORA
ORA
ORA
ORA
ORA
ORA
ORA
ORA

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

dd dd
dd
ii dd
dd

ii
dd
hh ll
ee ff
ff
ee ff
ff

1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4

54

Freescale Semiconductor

Instruction Set Summary

Operation

Object Code

Affect on CCR
Cyc-by-Cyc
Details
V11H INZC

Cycles

Source
Form

Address
Mode

Table 4-10. Instruction Set Summary (Sheet 6 of 8)

PSHA

Push Accumulator onto Stack

Push (A); SP (SP) $0001

INH

87

ps

1 1

PSHH

Push H (Index Register High) onto Stack

Push (H); SP (SP) $0001

INH

8B

ps

1 1

PSHX

Push X (Index Register Low) onto Stack

Push (X); SP (SP) $0001

INH

89

ps

1 1

PULA

Pull Accumulator from Stack

SP (SP + $0001); Pull (A)

INH

86

pu

1 1

PULH

Pull H (Index Register High) from Stack

SP (SP + $0001); Pull (H)

INH

8A

pu

1 1

PULX

Pull X (Index Register Low) from Stack

SP (SP + $0001); Pull (X)

INH

88

pu

1 1

DIR
INH
INH
IX1
IX
SP1

39 dd
49
59
69 ff
79
9E 69 ff

4
1
1
4
3
5

prwp
p
p
pprw
prw
ppprw

1 1

DIR
INH
INH
IX1
IX
SP1

36 dd
46
56
66 ff
76
9E 66 ff

4
1
1
4
3
5

prwp
p
p
pprw
prw
ppprw

1 1

ROL opr8a
ROLA
ROLX
ROL oprx8,X
ROL ,X
ROL oprx8,SP

Rotate Left through Carry

ROR opr8a
RORA
RORX
ROR oprx8,X
ROR ,X
ROR oprx8,SP

Rotate Right through Carry

C
b7

b0

C
b7

b0

RSP

Reset Stack Pointer (Low Byte)

SPL $FF
(High Byte Not Affected)

INH

9C

RTI

Return from Interrupt

SP (SP) + $0001;
SP (SP) + $0001;
SP (SP) + $0001;
SP (SP) + $0001;
SP (SP) + $0001;

INH

80

puuuuup

RTS

Return from Subroutine

SP SP + $0001; Pull (PCH)
SP SP + $0001; Pull (PCL)

INH

81

puup

Subtract with Carry

A (A) (M) (C)

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

A2
B2
C2
D2
E2
F2
9E D2
9E E2

2
3
4
4
3
2
5
4

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

Pull (CCR)
Pull (A)
Pull (X)
Pull (PCH)
Pull (PCL)

ii
dd
hh ll
ee ff
ff
ee ff
ff

1 1

1 1

1 1

1 1

SEC

Set Carry Bit

(C 1)

INH

99

1 1 1

SEI

Set Interrupt Mask Bit

(I 1)

INH

9B

pd

1 1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4

Freescale Semiconductor

55

Addressing Modes

STA
STA
STA
STA
STA
STA
STA

opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

Operation

DIR
EXT
IX2
IX1
IX
SP2
SP1

Store Accumulator in Memory

M (A)

Object Code
B7
C7
D7
E7
F7
9E D7
9E E7

dd
hh ll
ee ff
ff
ee ff
ff

Affect on CCR
Cyc-by-Cyc
Details
V11H INZC

Cycles

Source
Form

Address
Mode

Table 4-10. Instruction Set Summary (Sheet 7 of 8)

3
4
4
3
2
5
4

pwp
ppwp
pppw
ppw
pw
ppppw
pppw

0 1 1

STHX opr

Store H:X (Index Reg.)

(M:M + $0001) (H:X)

DIR

35 dd

pwwp

0 1 1

STOP

Enable Interrupts: Stop Processing

Refer to MCU Documentation
I bit 0; Stop Processing

INH

8E

1 1 0

Store X (Low 8 Bits of Index Register)

in Memory
M (X)

DIR
EXT
IX2
IX1
IX
SP2
SP1

BF
CF
DF
EF
FF
9E DF
9E EF

dd
hh ll
ee ff
ff

3
4
4
3
2
5
4

pwp
ppwp
pppw
ppw
pw
ppppw
pppw

0 1 1

IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1

A0
B0
C0
D0
E0
F0
9E D0
9E E0

ii
dd
hh ll
ee ff
ff

2
3
4
4
3
2
5
4

pp
prp
pprp
pppr
ppr
pr
ppppr
pppr

1 1

SWI

Software Interrupt
PC (PC) + $0001
Push (PCL); SP (SP) $0001
Push (PCH); SP (SP) $0001
Push (X); SP (SP) $0001
Push (A); SP (SP) $0001
Push (CCR); SP (SP) $0001
I 1;
PCH Interrupt Vector High Byte
PCL Interrupt Vector Low Byte

INH

83

psssssvvp

TAP

Transfer Accumulator to CCR

CCR (A)

INH

84

pd

TAX

Transfer Accumulator to X (Index Register

Low)
X (A)

INH

97

1 1

TPA

Transfer CCR to Accumulator

A (CCR)

INH

85

1 1

DIR
INH
INH
IX1
IX
SP1

3D dd
4D
5D
6D ff
7D
9E 6D ff

3
1
1
3
2
4

prp
p
p
ppr
pr
pppr

0 1 1

INH

95

pp

1 1

STX
STX
STX
STX
STX
STX
STX

opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB

#opr8i
opr8a
opr16a
oprx16,X
oprx8,X
,X
oprx16,SP
oprx8,SP

TST opr8a
TSTA
TSTX
TST oprx8,X
TST ,X
TST oprx8,SP
TSX

Subtract
A (A) (M)

Test for Negative or Zero

Transfer SP to Index Reg.

H:X (SP) + $0001

(M) $00
(A) $00
(X) $00
(M) $00
(M) $00
(M) $00

ee ff
ff

ee ff
ff

1 1 1

1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4

56

Freescale Semiconductor

Opcode Map

Operation

Object Code

Affect on CCR
Cyc-by-Cyc
Details
V11H INZC

Cycles

Source
Form

Address
Mode

Table 4-10. Instruction Set Summary (Sheet 8 of 8)

TXA

Transfer X (Index Reg. Low) to Accumulator

A (X)

INH

9F

1 1

TXS

Transfer Index Reg. to SP

SP (H:X) $0001

INH

94

pp

1 1

WAIT

Enable Interrupts; Wait for Interrupt

I bit 0; Halt CPU

INH

8F

1 1 0

Object Code:
dd
Direct address of operand
ee ff High and low bytes of offset in indexed, 16-bit offset
addressing
ff
Offset byte in indexed, 8-bit offset addressing
hh ll High and low bytes of operand address in extended
addressing
ii
Immediate operand byte
ii jj 16-bit immediate operand for H:X
rr
Relative program counter offset byte
Addressing Modes:
DIR
Direct addressing mode
EXT Extended addressing mode
IMM Immediate addressing mode
INH
Inherent addressing mode
IX
Indexed, no offset addressing mode
IX1
Indexed, 8-bit offset addressing mode
IX2
Indexed, 16-bit offset addressing mode
IX+
Indexed, no offset, post increment addressing mode
IX1+ Indexed, 8-bit offset, post increment addressing mode
REL Relative addressing mode
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode

Operation Symbols:
A
Accumulator
CCR Condition code register
H
Index register high byte
M
Memory location
n
Any bit
opr
Operand (one or two bytes)
PC
Program counter
PCH Program counter high byte
PCL Program counter low byte
rel
Relative program counter offset byte
SP
Stack pointer
SPH Most significant byte of stack pointer
SPL Least significant byte of stack pointer
X
Index register low byte
&
Logical AND
|
Logical OR

Logical EXCLUSIVE OR
()
Contents of
( )
Negation (twos complement)
#
Immediate value

Sign extend

Loaded with
?
If
:
Concatenated with
Cycle-by-Cycle Codes:
d
Dummy duplicate of the previous p, r, or s cycle.
d is always a read cycle so sd is a stack write
followed by a read of the address pointed to by the
updated stack pointer
p
Program fetch; read from next consecutive
location in program memory
r
Read 8-bit operand
s
Push (write) eight bits onto stack
u
Pop (read) eight bits from stack
v
Read vector from $FFxx (high byte first)
w
Write 8-bit operand

CCR Bits, Effects:

V
Overflow bit
H
Half-carry bit
I
Interrupt mask
N
Negative bit
Z
Zero bit
C
Carry/borrow bit
Set or cleared

Not affected
U
Undefined

4.4 Opcode Map

The opcode map is provided in Table 4-11.

CPU08 Central Processor Unit Reference Manual, Rev. 4

Freescale Semiconductor

57

Branch
REL

DIR

INH

Read-Modify-Write
INH
IX1

Control
SP1

IX

INH

INH

IMM

DIR

EXT

9E6

Register/Memory
IX2
SP2

IX1

SP1

IX

9EE

HIGH

9ED

LOW
5

BRSET0
3

1
2

CPU08 Central Processor Unit Reference Manual, Rev. 4

DIR 2
4

DIR
5

DIR 2
4

BSET1
2

DIR 2
4

BRCLR1 BCLR1
3

DIR
5

BRSET2
3

DIR
5

DIR 2
4

BSET2
2

DIR 2
4

BRCLR2 BCLR2
3

DIR
5

BRSET3
3

DIR
5

DIR 2
4

BSET3
2

DIR 2
4

BRCLR3 BCLR3
3

DIR
5

BRSET4
3

DIR
5

DIR 2
4

BSET4
2

DIR 2
4

BRCLR4 BCLR4
3

A
B

DIR
5

BRSET6
3

DIR
5

DIR 2
4

BSET5
2

DIR 2
4

BRCLR5 BCLR5
3

DIR
5

BRSET5
3

DIR
5

DIR 2
4

BSET6
2

DIR 2
4

BRCLR6 BCLR6
3

DIR
5

BRSET7
3

DIR
5

DIR 2
4

BSET7
2

DIR 2
4

Freescale Semiconductor

BRCLR7 BCLR7
3

INH
IMM
DIR
EXT
DD
IX+D

DIR
5

BRSET1
3

BSET0
2

BRCLR0 BCLR0
3

DIR
5

DIR

DIR 2

BRA
REL 2
3

BRN
REL 3
3

NEG
CBEQ

BCC
REL 2
3

BCS
REL 2
3

BNE
REL 2
3

BEQ
REL 2
3

BHCC
REL 2
3

BHCS
REL 2
3

BPL
REL 2
3

BMI
REL 3
3

BMC
REL 2
3

BMS
REL 2
3

1
4

COM
LSR
STHX
ROR
ASR
LSL
ROL
DIR 1
4

DBNZ
INC
TST

3
3

CLR
DIR 1

Inherent
REL
Relative
Immediate
IX
Indexed, No Offset
Direct
IX1
Indexed, 8-Bit Offset
Extended
IX2
Indexed, 16-Bit Offset
DIR/DIR
IMD
IMM/DIR
IX+/DIR
DIX+ DIR/IX+
*Pre-byte for stack pointer indexed instructions

INH 2
1

TSTX

INH 1
5

INH 2
4

MOV

DD 2
1

CLRA

DIX+ 3
1

CLRX

INH 1

IX1+

INH 3
1

INCX

INH 1
1

SP1
SP2
IX+

INH 2
3

DBNZX

INH 2
1

MOV

REL
3
REL 2

INH 1
3

TSTA

DIR 1

INH 2
1

DECX

INCA

DIR 1
3

INH 2
1

ROLX

INH 1
1

DBNZA

DIR 2
4

INH 2
1

LSLX

INH 1
1

DECA

DIR 1
5

INH 2
1

ASRX

INH 1
1

ROLA

DEC

DIR 3
1

RORX

INH 1
1

LSLA

DIR 1
4

BIL
BIH

IMM 2
1

ASRA

DIR 1
4

INH 2
4

LDHX

RORA

DIR 1
4

INH 2
1

LSRX

INH 1
3

LDHX

DIR 3
4

INH 1
1

COMX

INH 1
1

LSRA

DIR 1
4

IMM 3
7

DIV

INH 1
1

COMA

DIR 1
4

INH 2
4

CBEQX

IMM 3
5

MUL

REL
3
REL 2
3

NEGX

INH 1
4

CBEQA

DIR 3

BHI
BLS

NEGA

DIR 1
5

INH 2

NEG

CBEQ

NEG

IX1 3
5

CBEQ

IX1+ 4
3

1
5

COM

IX1 3
4

COM

LSR

LSR

SP1 1

CPHX
2
5

ROR

IX1 3
4

LSL

LSL

SP1 1
5

DBNZ

IX1 4
4

INC

DBNZ

INC

INC

TST

IX1 3
4

MOV
CLR

2
4

CLR

IX1 3

Stack Pointer, 8-Bit Offset

Stack Pointer, 16-Bit Offset
Indexed, No Offset with
Post Increment
Indexed, 1-Byte Offset with
Post Increment

SP1 1

INH
1

WAIT

IX 1

ADD

IMM 2

JMP
BSR

INH 2

LDX
2
1

TXA

INH 1

INH 2

JSR

AIX

LDX
STX

IX2 4
4

SBC
IX2 4
4

CPX
IX2 4
4

AND
IX2 4
4
IX2 4
4
IX2 4
4
IX2 4
4

EOR
IX2 4
4

ADC
IX2 4
4

ORA
IX2 4
4

ADD
IX2 4
4

SUB

SUB

SP2 2
5

CMP
SBC

EXT 3
4

CPX
AND

IX2 4

IX1 3
3

AND

SP2 2
5

BIT

IX1 3
3

BIT

SP2 2
5

LDA

IX1 3
3

LDA

SP2 2
5

STA

IX1 3
3

STA

SP2 2
5

EOR

IX1 3
3

EOR

SP2 2
5

ADC

IX1 3
3

ADC

SP2 2
5

ORA

IX1 3
3

ORA

SP2 2
5

ADD

IX1 3
3

ADD

SP2 2

IX1 3
3

CMP

LDX

CMP

SBC

SP2 2
5

STX
SP2 2

IX1 3
3

STX
IX1 3

IX
2

SBC

SP1 1
4

CPX

IX
2

CPX

SP1 1
4

AND

IX
2

AND

SP1 1
4

BIT

IX
2

BIT

SP1 1
4

LDA

IX
2

LDA

SP1 1
4

STA

IX
2

STA

SP1 1
4

EOR

IX
2

EOR

SP1 1
4

ADC

IX
2

ADC

SP1 1
4

ORA

IX
2

ORA

SP1 1
4

ADD

IX
2

ADD

SP1 1

IX
2

JMP
1

IX
4

JSR

IX1
3

LDX

IX
2

SP1 1
4

JSR
2

2 HC08 Cycles
Opcode Mnemonic
IX Number of Bytes / Addressing Mode

SUB
1

SUB

SP1 1
4

IX1
5

SUB

JMP
2

IX2
4

STX

EXT 3

IX1 3
3

CPX

SP2 2
5

IX2
6

IX2 4
4

IX1 3
3

SBC

SP2 2
5

JMP

LDX

IX1 3
3

CMP

SP2 2
5

JSR

EXT 3
4

STX

DIR 3

High Byte of Opcode in Hexadecimal

Low Byte of Opcode in Hexadecimal

EXT 3
5

LDX

DIR 3
3

IMM 2

EXT 3
3

JSR

DIR 3
3

IMM 2
2

EXT 3
4

JMP

DIR 3
4

REL 2
2

EXT 3
4

ADD

DIR 3
2

EXT 3
4

ORA

DIR 3
3

CLR

IMM 2
2

INH
1

NOP
STOP

DIR 3
3

CMP

STA

EXT 3
4

ADC

ORA

RSP

IX+D 1
2

IMM 2
2

IX2 4
4

LDA

EXT 3
4

EOR

DIR 3
3

ADC

ADD

INH 2
1

INH 1

IX
4

MOV

IMD
3

SEI

TST

SP1 1

EOR

ORA

INH 2
2

INH 1
1

CLRH
IX 1
2

INH 2
2

EXT 3
4

STA

DIR 3
3

IMM 2
2

ADC

CLI

INH 1
2

STA

SUB

BIT

LDA

DIR 3
3

IMM 2
2

EOR

INH 2
1

SEC

PSHH

IX 1
3

SP1 1
4

CLC

INH 1
2

LDA

AIS

INH 2
1

INH 1
2

PULH

IX 1
4

SP1 2
5

IX1 3
3

TST

IX 1
3

SP1 1
6

TAX

INH 1
2

EXT 3
4

BIT

DIR 3
3

IMM 2
2

EXT 3
4

AND

DIR 3
3

BIT

LDA
2
1

PSHX

DEC

AND

IMM 2
2

EXT 3
4

CPX

DIR 3
3

IMM 2
2

EXT 3
4

SBC

DIR 3
3

CPX

BIT

INH 2

INH
2

PULX
IX 1
3

ROL

DEC

IX1 3
5

DBNZ

LSL

ROL

TSX

PSHA

IX 1
3

SP1 1
5

IX1 3
4

DEC

ASR

SBC

IMM 2
2

EXT 3
4

CMP

DIR 3
3

IMM 2
2

AND

INH 2
2

PULA

IX 1
3

SP1 1
5

IX1 3
4

ROL

ROR

ASR

IX1 3
4

TXS

INH 1
2

CMP

CPX

REL 2
2

INH 1
1

TPA

DIR 1
3

SP1 1
5

BLE

INH 2
2

TAP
IX 1
4

CPHX

IMM
4

ASR

SWI

IX 1
3

SUB

DIR 3
3

IMM 2
2

SBC

REL 2
3

SUB

IMM 2
2

CMP

REL 2
3

BGT
2
9

SUB

REL 2
3

BLT

INH 2

INH
3

SP1 1
5

IX1 3
3

ROR

RTS

IX+ 1
2

BGE

INH 2
4

DAA

INH
4

LSR

RTI

IX 1
4

CBEQ

SP1 2

NSA
COM

NEG

SP1 1
6

IX
2

LDX

LDX

SP1 1
4

STX
SP1 1

IX
2

STX
IX

Addressing Modes

58

Table 4-11. Opcode Map

Bit-Manipulation
DIR
DIR

Chapter 5
Instruction Set
5.1 Introduction
This section contains detailed information for all HC08 Family instructions. The instructions are
arranged in alphabetical order with the instruction mnemonic set in larger type for easy reference.

5.2 Nomenclature
This nomenclature is used in the instruction descriptions throughout this section.

Operators
()

&
|

:
+

=
=
=
=
=
=
=
=
=
=
=

Contents of register or memory location shown inside parentheses

Is loaded with (read: gets)
Boolean AND
Boolean OR
Boolean exclusive-OR
Multiply
Divide
Concatenate
Add
Negate (twos complement)
Sign extend

CPU registers
A
CCR
H
X
PC
PCH
PCL
SP

=
=
=
=
=
=
=
=

Accumulator
Condition code register
Index register, higher order (most significant) eight bits
Index register, lower order (least significant) eight bits
Program counter
Program counter, higher order (most significant) eight bits
Program counter, lower order (least significant) eight bits
Stack pointer

CPU08 Central Processor Unit Reference Manual, Rev. 4

Freescale Semiconductor

59

Instruction Set

Memory and addressing

M =
M:M + $0001 =

rel

A memory location or absolute data, depending on addressing mode

A 16-bit value in two consecutive memory locations. The higher-order (most
significant) eight bits are located at the address of M, and the lower-order (least
significant) eight bits are located at the next higher sequential address.
The relative offset, which is the twos complement number stored in the last byte of
machine code corresponding to a branch instruction

Condition code register (CCR) bits

V
H
I
N
Z
C

=
=
=
=
=
=

Twos complement overflow indicator, bit 7

Half carry, bit 4
Interrupt mask, bit 3
Negative indicator, bit 2
Zero indicator, bit 1
Carry/borrow, bit 0 (carry out of bit 7)

Bit status BEFORE execution of an instruction (n = 7, 6, 5, ... 0)

For 2-byte operations such as LDHX, STHX, and CPHX, n = 15 refers to bit 15 of the 2-byte word or
bit 7 of the most significant (first) byte.
Mn = Bit n of memory location used in operation
An = Bit n of accumulator
Hn = Bit n of index register H
Xn = Bit n of index register X
bn = Bit n of the source operand (M, A, or X)

Bit status AFTER execution of an instruction

For 2-byte operations such as LDHX, STHX, and CPHX, n = 15 refers to bit 15 of the 2-byte word or
bit 7 of the most significant (first) byte.
Rn = Bit n of the result of an operation (n = 7, 6, 5, 0)

CCR activity figure notation

0
1
U

=
=
=
=
=

Bit not affected

Bit forced to 0
Bit forced to 1
Bit set or cleared according to results of operation
Undefined after the operation

CPU08 Central Processor Unit Reference Manual, Rev. 4

60

Freescale Semiconductor

Nomenclature

Machine coding notation

dd
ee
ff
ii
jj
kk
hh
ll
rr

=
=
=
=
=
=
=
=
=

Low-order eight bits of a direct address $0000$00FF (high byte assumed to be $00)
Upper eight bits of 16-bit offset
Lower eight bits of 16-bit offset or 8-bit offset
One byte of immediate data
High-order byte of a 16-bit immediate data value
Low-order byte of a 16-bit immediate data value
High-order byte of 16-bit extended address
Low-order byte of 16-bit extended address
Relative offset

Source forms
The instruction detail pages provide only essential information about assembler source forms.
Assemblers generally support a number of assembler directives, allow definition of program
labels, and have special conventions for comments. For complete information about writing
source files for a particular assembler, refer to the documentation provided by the assembler
vendor.
Typically, assemblers are flexible about the use of spaces and tabs. Often, any number of spaces
or tabs can be used where a single space is shown on the glossary pages. Spaces and tabs are
also normally allowed before and after commas. When program labels are used, there must also
be at least one tab or space before all instruction mnemonics. This required space is not apparent
in the source forms.
Everything in the source forms columns, except expressions in italic characters, is literal
information which must appear in the assembly source file exactly as shown. The initial 3- to
5-letter mnemonic is always a literal expression. All commas, pound signs (#), parentheses, and
plus signs (+) are literal characters.
The definition of a legal label or expression varies from assembler to assembler. Assemblers also
vary in the way CPU registers are specified. Refer to assembler documentation for detailed
information. Recommended register designators are a, A, h, H, x, X, sp, and SP.
n Any label or expression that evaluates to a single integer in the range 07
opr8i Any label or expression that evaluates to an 8-bit immediate value
opr16i Any label or expression that evaluates to a 16-bit immediate value
opr8a Any label or expression that evaluates to an 8-bit value. The instruction treats this
8-bit value as the low order eight bits of an address in the direct page of the 64-Kbyte
address space ($00xx).
opr16a Any label or expression that evaluates to a 16-bit value. The instruction treats this
value as an address in the 64-Kbyte address space.
oprx8 Any label or expression that evaluates to an unsigned 8-bit value; used for indexed
addressing
oprx16 Any label or expression that evaluates to a 16-bit value. Since the MC68HC08S has a
16-bit address bus, this can be either a signed or an unsigned value.

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Instruction Set

rel

Any label or expression that refers to an address that is within 128 to +127 locations
from the next address after the last byte of object code for the current instruction. The
assembler will calculate the 8-bit signed offset and include it in the object code for this
instruction.

Address modes
INH
IMM
DIR
EXT
IX
IX+
IX1
IX1+
IX2
REL
SP1
SP2

=
=
=
=
=
=
=
=
=
=
=
=

Inherent (no operands)

8-bit or 16-bit immediate
8-bit direct
16-bit extended
16-bit indexed no offset
16-bit indexed no offset, post increment (CBEQ and MOV only)
16-bit indexed with 8-bit offset from H:X
16-bit indexed with 8-bit offset, post increment (CBEQ only)
16-bit indexed with 16-bit offset from H:X
8-bit relative offset
Stack pointer relative with 8-bit offset
Stack pointer relative with 16-bit offset

5.3 Convention Definitions

Set refers specifically to establishing logic level 1 on a bit or bits.
Cleared refers specifically to establishing logic level 0 on a bit or bits.
A specific bit is referred to by mnemonic and bit number. A7 is bit 7 of accumulator A.
A range of bits is referred to by mnemonic and the bit numbers that define the range. A [7:4] are
bits 7 to 4 of the accumulator.
Parentheses indicate the contents of a register or memory location, rather than the register or
memory location itself. (A) is the contents of the accumulator. In Boolean expressions,
parentheses have the traditional mathematical meaning.

5.4 Instruction Set

The following pages summarize each instruction, including operation and description, condition
codes and Boolean formulae, and a table with source forms, addressing modes, machine code,
and cycles.

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Memory
$0000

$003F

I/O REGISTERS
64 BYTES

$0040

$007F

RESERVED(1)
64 BYTES

$0080

$00FF

RAM
128 BYTES

$0100

$27FF

UNIMPLEMENTED(1)
9984 BYTES

$2800

$2DFF

AUXILIARY ROM
1536 BYTES

$2E00

$EDFF

UNIMPLEMENTED(1)
49152 BYTES

$EE00

$FDFF

FLASH MEMORY
MC68HC908QT4 AND MC68HC908QY4
4096 BYTES

Note 1.
Attempts to execute code from addresses in this
range will generate an illegal address reset.

$2E00
UNIMPLEMENTED
51712 BYTES

$F7FF

$FE00

BREAK STATUS REGISTER (BSR)

$FE01

RESET STATUS REGISTER (SRSR)

$FE02

BREAK AUXILIARY REGISTER (BRKAR)

$FE03

BREAK FLAG CONTROL REGISTER (BFCR)

$FE04

INTERRUPT STATUS REGISTER 1 (INT1)

$FE05

INTERRUPT STATUS REGISTER 2 (INT2)

$FE06

INTERRUPT STATUS REGISTER 3 (INT3)

$FE07

RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR)

$FE08

FLASH CONTROL REGISTER (FLCR)

$FE09

BREAK ADDRESS HIGH REGISTER (BRKH)

$FE0A

BREAK ADDRESS LOW REGISTER (BRKL)

$FE0B

BREAK STATUS AND CONTROL REGISTER (BRKSCR)

$FE0C

LVISR

$FE0D

$FE0F

RESERVED FOR FLASH TEST

3 BYTES

$FE10

$FFAF

MONITOR ROM 416 BYTES

$FFB0

$FFBD

FLASH
14 BYTES

$FFBE

FLASH BLOCK PROTECT REGISTER (FLBPR)

$FFBF

RESERVED FLASH

$FFC0

INTERNAL OSCILLATOR TRIM VALUE

$FFC1

RESERVED FLASH

$FFC2

$FFCF

FLASH
14 BYTES

$FFD0

$FFFF

USER VECTORS
48 BYTES

FLASH MEMORY
1536 BYTES

$F800

$FDFF

MC68HC908QT1, MC68HC908QT2,
MC68HC908QY1, and MC68HC908QY2
Memory Map

Figure 2-1. Memory Map

MC68HC908QY/QT Family Data Sheet, Rev. 5

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