MEMORY AND STORAGE

Stanley L. Aquino

Outline
.Basics of Semiconductor Memory
.Random-Access Memories (RAMs)

Objectives
.Define the basic memory characteristics
.Explain what a RAM is and how it works
.Explain the difference between static RAMs
(SRAMs) and dynamic RAMs (DRAMs)

Memory Units
.Memoriesstoredatainunitsfromonetoeightbits.Themostcommonunitisthebyte,whichbyde
finitionis8bits.
.Bitis the smallest unit of binary data.
.Byte is a unit for group of 8 bits.
.Data can be stored in 9-bit groups which consist of a byte
plus a parity bit.
.Nibble is a group of 4 bits
.One byte can be split into two nibbles.

Memory Units
.Computermemoriesareorganizedintomultiplesofbytescalledwords.Generally,awordisde
finedasthenumberofbitshandledasoneentitybyacomputer.Bythisdefinition,awordisequa
ltotheinternalregistersize(usually16,32,or64bits).
.Forhistoricalreasons,assemblylanguagedefinesawordasexactlytwobytes.Inassemblyla
nguage,a32bitentityiscalledadouble-wordand64bitsisdefinedasaquad-word.

Memory Units
.Each storage element in a
memory can retain either a
1 or a 0 and is called a cell.
.Memories are made up of
arrays of cells.
.Each block in the memory
array represents one
storage cell, and its
location can be identified
by specifying a row and a
column.
8x8 ARRAY
16x4 ARRAY
64x1 ARRAY
A64-cell memory array organized in
three different ways.

Memory Units
.Amemoryisidentifiedbythenumberofwordsitcanstoretimesthewordsize.
.Example:
16kx8memory
Numberofwords=16,000words
Wordsize=8bits
.16kx8memorycanactuallystore16,384wordsofeightbitseach.
.Theactualnumberofwordsisalwaysapowerof2.

214=16,384

Memory Units
.Thelocationofaunitofdatainamemoryarrayiscalleditsaddress.Itdependsonhowthememor
yisorganizedintounitsofdata.
The address of the blue
bit is row 5, column 4
The address of the
blue byte is row 3
Memory address in 2-dimensional array

Memory Address and Capacity

.A3-dimensionalarrayisarrangedasrowsandcolumns.Eachbytehasauniquerowandcolumnadd
ress.
a)How many bytes are
shown?
b)What is the location of the
blue byte?
b) Row 5, column 8
a) 64 B

Memory Address and Capacity

.The capacityof a memory is the total number of
data units that can be stored.
.Computer memories typically have 256 MB (MB
is megabyte) or more of internal memory.
The capacity is 64 bits
The capacity is
8 bytes = 64 bits
The capacity is 64 bytes

Basic Memory Operations

.Thewriteoperationputsdataintoaspecifiedaddressinthememory.
.Thereadoperationcopiesdataoutofaspecifiedaddressinthememory.
.Theaddressingoperationselectsthespecifiedmemoryaddressandispartofboththewritean
dthereadoperations.

Basic Memory Operations

.Inordertoreadorwritetoaspecificmemorylocation,abinarycodeisplacedontheaddressbu
s.Internaldecodersdecodetheaddresstodeterminethespecificlocation.Dataisthenmoved
toorfromthedatabus.
RowaddressdecoderAddress busData busWriteMemory arrayReadColumn address decoder
The address bus is a group of
conductors with a common
function. Its size determines
the number of locations that
can be accessed. A 32 bit
address bus can access 232locations, which is
approximately 4G.

Basic Memory Operations

.Inadditiontotheaddressbusanddatabus,
semiconductormemorieshavereadandwritecontrolsignalsandchipselectsignals.Dependin
gonthetypeofmemory,othersignalsmayberequired.
Chip Select(CS) or Chip Enable(CE) is used as part of address
decoding. All other inputs are ignored if the Chip Select is not
active.
ReadEnable(RE) and WriteEnable(WE) signals are sent from
the CPU to memory to control data transfer to or from memory.
Output Enable(OE) is active during a read operation,
otherwise it is inactive. It connects the memory to the data
bus.

1.The address is placed

on the address bus.
2.Data is placed on the
data bus.
3.A write command is
issued.
Basic Memory Operations
.Asimplifiedwriteoperationisshowninwhichnewdataoverwritestheoriginaldata.Datamov
estothememory.
1
2
3

1.The address is placed

on the address bus.
2.A read command is
issued.
3.A copy of the data is
placed in the data bus
and shifted into the
data register.
Basic Memory Operations
.Thereadoperationisactuallya copy operation,astheoriginaldataisnotchanged.
1
2
3
0
0
1

Semiconductor Memories
.Semiconductormemoriesaredevicesforstoringdigitalinformationthatisfabricatedbyus
ingintegratedcircuittechnology.
.Theyareclassifiedaccordingtothetypeofdatastorageandthetypeofdataaccessmechanism
.RAM-random-accessmemory
.ROM-read-onlymemory

Semiconductor Memories: RAM

.RAM(random-accessmemory)isatypeofmemoryinwhichalladdressesareaccessibleinanequa
lamountoftimeandcanbeselectedinanyorderforareadorwriteoperation.
.AllRAMshavebothreadandwritecapability.
.Volatilememoriesarememoriesthatlosestoreddatawhenthepoweristurnedoff.
.RAMisavolatilememory.

Semiconductor Memories: ROM

.ROM (read-only memory) is a type of memory in
which data are stored permanently or semi
permanently.
.Data can be read from a ROM, but there is no
write operation as in the RAM.
.Nonvolatile memories are memories that retain
stored data even if power is turned off.
.ROM is a nonvolatile memory.

Random Access Memories (RAMs)

.RAMs are read/write memories in which data can be written
into or read from any selected address in any sequence.
.When a data unit is written into a given address in the RAM,
the data unit previously stored at that address is replaced by
the new data unit.
.When a data unit is read from a given address in the RAM, the
data unit remains stored and is not erased by the read
operation.
.A RAM is typically used for short-term data storage because it
cannot retain stored data when power is turned off.

The RAM Family

.The two categories of RAM
.Static RAM (SRAM)
.Dynamic RAM (DRAM)
.Static RAMs generally use latchesas storage elements
and can therefore store data indefinitely as long as dc
power is applied.
.Dynamic RAMs use capacitorsas storage elements and
cannot retain data very long without the capacitors
being recharged. This process of charging the capacitor
is called refreshing.

The RAM Family

.Comparison between SRAMs and DRAMs.
.Both SRAMs and DRAMs will lose stored data when dc
power is removed and, therefore, are classified as
volatile memories.
.Data can be read much faster from SRAMs than from
DRAMs.
.DRAMs can store much more data than SRAMs for a
given physical size and cost because the DRAM cell is
much simpler, and more cells can be crammed into a
given chip area than in the SRAM.

The RAM Family

StaticRAM(SRAM)
DynamicRAM(DRAM)
AsynchronousSRAM(ASRAM)
SynchronousSRAM withburst feature(SB SRAM)
ExtendedData OutDRAM(EDO DRAM)
BurstEDO DRAM(BEDODRAM)
Fast PageModeDRAM(FPM DRAM)
SynchronousDRAM(SDRAM)
RandomAccessMemory(RAM)Bits stored in a
semiconductor
latch or flip-flop
Bits stored as
charge on a
capacitor

Static RAMs (SRAMs)

.All static RAMs are characterized bylatch memory cells.
.As long as dc power is applied to a static memory cell, it
can retain a 1 or 0 state indefinitely. If power is removed,
the stored data bit is lost.
A typical SRAM
latch memory cell.

Basic Static Memory Cell Array

.The memory cells in an
SRAM are organized in
rows and columns.
.All the cells in a row share
the same Row Select line.
.Data in and data out lines
are connected to a single
data line that serves as
either an input and output
line through buffers and
control.
Basic SRAM array
(n x 4 array)

Basic Asynchronous SRAM Organization

.An asynchronous
SRAM is one in
which the operation
is not synchronized
with a system clock.
Logic diagram
for an
asynchronous
32k x 8 SRAM

Basic Asynchronous SRAM Organization: Tristate

Outputs and Buses
.Tristate buffer allows two logic states (LOW -0 or HIGH 1) as input but produces three different types of output
signals (LOW -o, HIGH -1 or HIGH IMPEDANCE Z).
.It has two inputs: a data inputand a control input.
.The control input acts like a valve.
.When the control input is active, the
output is the input.
.It allows the data lines to act as either
input or output lines and connect the
memory to the data bus in a computer.
.Tristate outputs are indicated on logic
symbols by a small inverted triangle.
Tristate buffer

Basic Asynchronous SRAM Organization: Memory

Array
.SRAM chips can be organized in single bits, nibbles (4
bits), bytes (8 bits), or multiple bytes (16, 24, 32 bits, etc.).
.The memory cell array is arranged in 256 rows and 128
columns, each with 8 bits. The actual addresses are 215=
32,768. Each address contains 8 bits. The capacity is
32,768 bytes (typically expressed as 32 kB).
The organization of
a typical 32k x 8
SRAM

Basic Asynchronous SRAM Organization:

Operation
.For the memory to
operate, chip select
(CS ) must be LOW.
.Fifteen address lines,
eight of which are
decoded by the row
and seven by the
column decoder.
.Eight data
Input/output lines
Memory block diagram

Basic Asynchronous SRAM Organization: Read

.Read cycle sequence:
.A valid address is put on the
address bus
.Chip select is LOW
.Write enable is HIGH
.Output enable is LOW
.Data is obtained from the data
bus
.The input tristatebuffers are
disabled by gate G1, and the
column output tristatebuffers are
enabled by gate G2.
Memory control
signals
Connected to the eight
tristateinput buffers
control input
Connected to the eight
tristateoutput buffers
control input
0
1
0
1
(Enable)
0
(Disable)

Basic Asynchronous SRAM Organization: Write

.Write cycle sequence:
.A valid address is put on the
address bus
.Chip select is LOW
.Write enable is LOW
.Output enable is a Don t Care
.Data is placed on the data bus
.The input buffers are enabled by
gate G1, and the output buffers
are disabled by gate G2.
Memory control
signals
Connected to the eight
tristateinput buffers
control input
Connected to the eight
tristateoutput buffers
control input
0
0
X
0
(Disable)
1
(Enable)

Basic Asynchronous SRAM Organization: Read

Cycle
.A valid address code is applied to the address lines for a
specified time interval.
.The chip select and the output enable inputs go LOW.
.After a specified time delay, valid data will appear on the data
lines
A typical timing diagrams for a memory read cycle for SRAM

Basic Asynchronous SRAM Organization: Write

Cycle
.A valid address code is applied to the address lines for a specified
time interval called the write cycle time, tWE.
.The chip select and the write enable inputs go LOW.
.A valid data is supplied after a specified time interval after the
deassertionof Write enable signal.
A typical timing diagrams for a memory write cycle for SRAM

Basic Synchronous SRAM

.A synchronous SRAM is synchronized with the
system clock and uses clocked registers.
.The address, the read/write input, the chip
enable, and the input data are all latched into
their respective registers on an active clock
pulse edge.
.Once this information is latched, the memory
operation is in sync with the clock.

Basic Synchronous SRAM: Read and Write

Read Cycles of Synchronous SRAM
Write Cycles of Synchronous SRAM

Basic Synchronous SRAM with Burst Feature

A basic block diagram of a 32k x 8 synchronous SRAM with burst feature

Basic Synchronous SRAM with Burst Feature

.A set of parallel lines can be indicated by a single heavy
line with a slash and the number of separate lines in the set.
.Two basic types of synchronous SRAM are theflow-through
and the pipelined.
.The flow-throughsynchronous SRAM does not have a
Data output register, so the output data flow
asynchronously to the data I/O lines through the output
buffers.
.The pipelined synchronous SRAM has a Data output
register so the output data are synchronously placed on
the data I/O lines.

Basic Synchronous SRAM:The Burst

Feature
.Burst feature allows the memory to read or write
at up to four locations using a single address by
adding 00, 01, 10, and 11 to the two lowest order address bits on successive clock pulses.

Basic Synchronous SRAM:Read Burst

Feature
Timing diagram of Read cycles of Synchronous SRAM with burst feature

Basic Synchronous SRAM:Write Burst

Feature
Timing diagram of Write cycles of Synchronous SRAM with burst feature

SRAM Application: Cache Memory

.Cache memory is a relatively small, high-speed memory
that stores the most recently used instructions or data
from the larger but slower main memory.
.Cache memory is basically a cost-effective method of
improving system performance without having to resort
to the expense of making all of the memory faster.
SRAM used as cache memory in computers
CACHE
CACHE

SRAM Application: L1 and L2 Caches

.A first-level cache (L1 cache) is usually integrated into the processor
chip and has a very limited storage capacity.
.L1 cache is also known as primary cache.
.A second-level cache (L2 cache) is a separate memory chip or set
of chips external to the processor and usually has a larger storage
capacity than an L1 cache.
.L2 cache is also known as secondary cache.

Block diagram showing L1 and L2 cache memories in a computer system

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