BASIC CHARACTERISTICS OF

ELECTRONIC CIRCUITS

MOSFET Fabrication
- Silicon is an electrical semiconductor.
- A transistor is fabricated by creating areas in the silicon substrate
that have an excess of either positive or negative electrical charge.
- The gate terminal is made of polysilicon which is preferable to metal
as it can be fabricated with extremely small dimensions.
- The gate is electrically isolated from the rest of transistor by a layer
of SiO2.
- Transistors operation is governed by electrical fields caused by
voltages applied to its terminal

NMOS off
V

= 0V
SiO 2

= 0V
V

++++++ ++++
++++++
++++++
+++++++++
++++++
++++++
++++++
++++++
++++++
+++++++++++
++++++
+++++++++++
+++++++++ Substrate (type p) +++++++++

Source (type n)

Drain (type n)

(a) WhenV GS = 0 V, the transistor is off

NMOS transistor when turned off: back-to-back diodes represent

very high resistance (1012 ohm) between drain & source

NMOS on

VDD
VG = 5 V

SiO2

VS = 0 V

VD = 0 V
++++++ ++++
+++ ++++++
++++++
++++++
+++++++++++ +++++++++++++++++
+++++++++ ++ +++++++ ++++++++++

Channel (type n)
(b) When VGS = 5 V, the transistor is on

NMOS transistor when turned on: If the gate-to-source voltage

VGS is greater than a certain minimum positive voltage, called
VT (typically 0,2 VDD), then the switch is closed.

Channel size
-The positive voltage on the gate attracts free electrons existing in
the type-n source and drain terminals & other areas of the transistor
towards the gate. Because of SiO2 layer, electrons gather in region
of the substrate between source & drain terminals, which results
into channel connecting source & drain.

+
W1

+
L

L
(a) Small transistor

(b) Larger transistor

- The size of channel is determined by length L & width W

W2

ID

Current-Voltage Curve
Triode

V GS V T

- Triode region:
- Saturation region:

Saturation

VDS

ID

Triode

Saturation

V GS V T
VDS

MOSFET On-Resistance
VDD

VDD

R
Vf
Vx

(a) NMOS NOT gate

I stat

- Ideal switches have infinite resistance

when turned off and zero resistance
when turned on
- The actual resistance is VDS/ID

V f = V OL
RDS

(b) Vx = 5 V

Example 3.4

Example 3.5

Voltage Transfer Characteristic

Vf

VDD

V OH = V DD

Slope = 1

T1
Vx

Vf
T2

(a) Circuit

V OL = 0 V
VT

- VIL: maximum input voltage

- VIH: minimum input voltage

V IL

V IH
V DD

( V DD V T ) V DD

Vx

N1

Noise Margin

N2

(a) A NOT gate driving another NOT gate

Consider 2 NOT gates connected in Fig. a. When N1 produces its

low voltage level VOL, the presence of noise may alter the voltage
level, but as long as it remains less than VIL, it will be interpreted
correctly by N2
The ability to tolerate noise without affecting the correct
operation of the circuit is known as NOISE MARGIN
For low output voltage, low noise margin: NML = VIL VOL
For high output voltage, high noise margin: NMH = VOH VIH

Example 3.6
N1

N2

x
(a) A NOT gate driving another NOT gate

VDD

VDD

Dynamic
Operation

VA
Vx

Vf
C

(b) The capacitive load at node A

- Because of the way transistors are constructed in silicon, capacitors

may be effectively created. This capacitance is called parasitic/stray
which results as an un-designed side effect of transistor fabrication.
- One significant capacitance exists between input of N2 and Ground:
Its value depends on the sizes of the transistors in N2. Each tran.
contributes a gate capacitance Cg= W x L x COX (oxide capacitance)
- Additional capacitance is caused by tra. N1 & by metal wiring that is
attached to node A

VDD

VDD

VA
Vx

Vf
C

(b) The capacitive load at node A

- Thus, it is possible to represent all parasitic capacitance by an

equivalent C
- C has a negative effect on the operation speed of the logic gate:
Voltage across a capacitor cannot change instantaneously
- Time needed for charging & discharging depends on size of C and
current through the C
- In detailed: when N1 PMOS ON ? Then when N1 NMOS ON ?

Propagation Delay
VDD
Vx

50%

50%

Gnd
Propagation delay

Propagation delay

VDD
90%
VA

90%

50%
Gnd

50%

10%
tr

10%
tf

(3.1)

(3.2)

+
W1

+
L

L
(a) Small transistor

(b) Larger transistor

W2

VDD

Power Dissipation

Vf
Vx

(c) NMOS NOT gate

VDD

Power Dissipation
Vx
Vf

Vf

Vx

(a) Current flow when input Vx

changes from 0 V to 5 V

(b) Current flow when input Vx

changes from 5 V to 0 V

Short Circuit Current

VDD

Vf
VOH = VDD

Slope= 1

T1
Vx

Vf
T2
VOL = 0 V
VT

(a) Circuit

VIL

VIH
VDD

(VDD VT) VDD

Vx

CMOS - Power Dissipation

V DD

Vf
Vx

Vx

Vx

Vx

High fan-in NMOS NAND gate.

VDD

Vf
Vx1

Vx2

Vxk

High fan-in NMOS NOR gate.

N1
x

Vf

To inputs of
x
n other inverters

To inputs of
n other inverters
Cn

(a) Inverter that drives n other inverters

(b) Equivalent circuit for timing purposes

V f for n =1
VDD

V f for n = 4
Gnd
0

Time

(c) Propagation times for different values of n