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Classic designs are being migrated to SDR-based implementation, and requirements for recongurability, space and size reduction
are becoming crucial. SDR offers the most benet in multichannel
scenarios where high-speed signal-processing modules can process
multiple channels without duplication of expensive processing modules. FPGAs are also playing a signicant role for baseband processing and offer recongurability and space saving that is crucial for a
variety of applications. This multichannel receiver can be used as, for
example, a sonobuoy receiver, a tactical communication receiver or a
next-generation wireless communication receiver. The FPGA-based
implementation allows the user to recongure the same hardware into
System description
ADC 1
ADC 4
DDC 1
DDC 16
PMC: ICS-554
FPGA
8-ch FM
demod
8-ch FM
demod
PCI interface
Market needs
Data format
igh-speed analog to digital converters (ADC) and large eldprogrammable gate arrays (FPGA) have allowed designers to
design compact solutions that were unthinkable a few years ago.
This article discusses how a 16-channel frequency modulation (FM)
demodulator operating in the intermediate frequency (IF) region may
be implemented in a single slot, and builds on two articles previously
published in RF Design[1,2]. The system implemented here is capable
of digitally tuning to 16 separate FM bands, downconverting the signal
to produce complex baseband outputs and performing a multichannel
FM demodulation in a FPGA core.
This article describes an example implementation that can handle an
FM bandwidth of 300 kHz. This supports an FM with 40 kHz message
bandwidth and 105 kHz FM deviation. The implementation presented
here easily handles a wide range of applications including sonobuoy
and tactical communication applications. The 16-channel demodulator
is implemented in a modular fashion as two eight-channel demodulator
blocks. The eight-channel FM demodulator uses less than than 4700
slices, seven 18 x 18 multipliers and 16 18 kbit random access memory
(RAM) blocks found in a Xilinx FPGA[3].
Data format
PMC: ICS-1580
To host
46
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April 2006
I*dQ - Q*dI
I
16
16
I +Q
2
2 n (I*dQ - Q*dI)
32
32
Automatic scaling
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 6
Ch 7
Ch 8
32
32
2 (-m) * (I 2 + Q 2 )
16
Decimate by 16,
361-tap MAC
FIR (8-ch)
1.5625
Msps/ch
97.65 ksps/ch
x 8 channels
16
To PCI interface
Figure 3. An eight-channel FM demodulator module implemented in FPGA.
100 MHz
64
17%
DDC RF Bandwidth
265 kHz
1.5625 Msamples/s
(complex)
97.65 ksamples/s
(real) per channel
Hardware modules
The ICS-554 and the ICS-1580 PMC modules that enable the build
up of the system are described here.
ICS-554. A four-input high-speed ADC card capable of
sampling at rates up to 105 MHz. Up to 16 onboard narrowband
digital tuners enable users to implement a compact multichannel
receiver solution. The maximum bandwidth per channel is 2.5 MHz
for the 16 narrowband channels. Multiple channels may be combined
to provide up to four channels at 10 MHz each. The onboard DDCs
allow the user to digitally downconvert the signal and reduce the
effective data rate for each channel. Digital tuning is achieved by
writing a tuning word for the numerically controlled oscillator
(NCO). Digital retuning is thus an extremely fast process and enables
the receiver to serve as a very fast frequency-hopped system. More
information regarding the ICS-554 is available from[4].
ICS-1580. A PMC module with a Virtex-II Pro device
(XC2VP70). The FPGA is directly connected to 64 Mbytes of
synchronous dynamic random access memory (SDRAM) arranged
as four independent banks and 16 Mbytes of QDR-II SRAM arranged
as four independent banks. Four multi-Gigabit Tx/Rx links from
the FPGA are available on the front panel and enable high-speed
data movement in a multiboard scenario. This would allow multiple
ICS-1580s to be interconnected to increase effective FPGA resources.
The 64 user I/O lines of the PMC module are also connected to
the FPGA and are used to transfer data from the ICS-554 to this module.
More information regarding the ICS-554 is available from[5].
48
Baseband lter
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April 2006
Used in 8-ch
FM demod
Percent Used
33,088
4700
14.2%
18 x 18 Multiplier
328
2.1%
328
16
4.9%
Multichannel IF receiver
Signal generator
-10
-20
-30
-40
-50
-60
PCI
FM at 21.4 MHz
105 kHz deviation
8 kHz message
Amplitude (dB)
Slices
Total Available
-70
-80
0
Demod data
analysis (off-line)
10
15
20 25 30 35
Frequency (kHz)
40
45
50
Distortion reduction
Performance characterization
-10
-20
Amplitude (dB)
-30
-40
-50
-60
-70
-80
0
10
15
20 25 30 35
Frequency (kHz)
40
45
50
Conclusion
References
50
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