Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog 21 September 2007.

2007 by Elsevier Inc. Reproduced with permission from the publisher.

77

solutions for chapter 5

exercise 5.14

A possible datapath is:

p_cnt_ce
cnt_rst

ab_cnt_ce

counter
7-bit
ce
Q

ab_cnt_tc

reset TC
clk
counter
7-bit
ce
Q

SSRAM
A

a_data
ab_rd

D_in D_out

reset

en

clk

wr

SSRAM

clk

D_in D_out
en

SSRAM
A

b_data

D_in D_out
en
wr
clk

p_wr
clk

The two SSRAMs on the left store the elements of the vectors a and b, and
the SSRAM on the right stores the elements of the vector p. This datapath
is simplified from a complete version, since it does not include provision
for writing the vector values into the a and b memories or reading the values from the p memory. We will return to that shortly.
The addresses for the memories are generated by the two counters, each
of which starts from 0 and increments cycle-by-cycle up to 127 as corresponding elements from a and b are read, multiplied, and the product
stored. Given that the computation takes a cycle, the address for the p
memory must lag one behind the address for the a and b memories. That
is why we use separate counters with separate count-enable control inputs. The timing for computation of a complete vector product, starting

wr
clk

p_data

Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog 21 September 2007.
2007 by Elsevier Inc. Reproduced with permission from the publisher.

78

solutions for chapter 5

with the go input being activated and finishing with the done output being
activated, is:
state

idle

idle cmp0 comp comp

comp comp last result idle

clk
go
cnt_rst
ab_cnt_ce
a/b address

126 127

ab_rd
0

a/b SSRAM output

125 126 127

p_cnt_ce
p address

125 126 127

ab_cnt_tc
p_wr
done

We have also shown the control steps on this diagram. They will be implemented by the control section. The counters are held reset when the circuit is idle. When the go input is activated, the counter reset signal is
deactiviated, but only the a and b address counter is enabled. The a and b
memories are enabled to read. In the next cycle, the elements at address 0
appear at the SSRAM outputs and are multiplied together. The p memory
address counter is enabled (one cycle behind the a and b memory address
counter, hence it lags by 1), and the p memory is enabled to write. On subsequent cycles, the operations repeat, until the a and b address counter
reaches its terminal count. There is then one last cycle to compute and
write the final product to the p memory. After that, the done output is activated for a cycle and the counters are reset.
The control section can be implemented as a finite-state machine. The
transition and output functions are shown in the following table:
state

go

ab_cnt_tc

idle

0
1

idle
cmp0
comp

next
state

cnt_rst

ab_cnt_ce
ab_rd

p_cnt_ce
p_wr

done

idle

1
0
0
0

0
1
1
1

0
0
1
1

0
0
0
0

cmp0
comp
comp

Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog 21 September 2007.
2007 by Elsevier Inc. Reproduced with permission from the publisher.

79

solutions for chapter 5

state

go

ab_cnt_tc

next
state

cnt_rst

ab_cnt_ce
ab_rd

p_cnt_ce
p_wr

done

comp

last

0
0
1

1
0
0

1
1
0

0
0
1

last
result

result
idle

What is missing from the simplified datapath is provision for an external

circuit to provide address and control signal inputs to write to the a and b
memories and to read the p memory. We can provide for these operations
by augmenting the datapath as follows:
addr_sel
p_addr
p_cnt_ce
cnt_rst

ab_cnt_ce

counter
7-bit
ce
Q

ab_cnt_tc

reset TC
clk

a_addr

1
0

counter
7-bit
ce
Q

SSRAM
A

a_data
ab_rd

D_in D_out

clk

wr

SSRAM

clk

SSRAM

b_data

D_in D_out
en

b_wr_en

D_in D_out
en

b_addr

reset

en

a_wr_en

wr
clk

p_rd_en
p_wr
clk

The control signal addr_sel is 0 in the idle state and 1 in all other states.
e x e r c i s e 5 . 1 5 We will assume the a and b vector elements are
16-bit signed values and the p vector elements are 32-bit signed values. For
other types or sizes, the types in the model can be changed accordingly.
The module definition is:
module vector_product_pipelined
( input
clk, reset, go,
input
[6:0] a_addr, b_addr,

wr
clk

p_data

Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog 21 September 2007.
2007 by Elsevier Inc. Reproduced with permission from the publisher.
solutions for chapter 5

e x e r c i s e 5 . 1 8 We can specify the order of concurrent read and

write operations by combining the model code for the two ports into one
always block.
a) The revised model ensuring the read occurs first is:
// In this module, if a read and write to the same
// address occur concurrently, the value read is the
// original value before the write.
module dual_port_SSRAM_synth_a
( output reg [15:0] d_out1,
input
[15:0] d_in1,
input
[11:0] a1,
input
en1, wr1,
output reg [15:0] d_out2,
input
[11:0] a2,
input
[11:0] en2,
input
clk );
reg [15:0] data_RAM [0:4095];
always @(posedge clk) begin // dual port
if (en2) d_out2 <= data_RAM[a2];
if (en1)
if (wr1) begin
data_RAM[a1] <= d_in1; d_out1 <= d_in1;
end
else
d_out1 <= data_RAM[a1];
end
endmodule

b) The revised model ensuring the write occurs first is:

// In this module, if a read and write to the same
// address occur concurrently, the value read is the
// original value before the write.
module dual_port_SSRAM_synth_b
( output reg [15:0] d_out1,
input
[15:0] d_in1,
input
[11:0] a1,
input
en1, wr1,
output reg [15:0] d_out2,
input
[11:0] a2,
input
[11:0] en2,
input
clk );

87

Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog 21 September 2007.
2007 by Elsevier Inc. Reproduced with permission from the publisher.

88

solutions for chapter 5

reg [15:0] data_RAM [0:4095];

always @(posedge clk) begin // dual port
if (en1)
if (wr1) begin
data_RAM[a1] <= d_in1; d_out1 <= d_in1;
end
else
d_out1 <= data_RAM[a1];
if (en2)
if (wr1 && a1 == a2) d_out2 <= d_in1;
else
d_out2 <= data_RAM[a2];
end
endmodule

The code representing the read port explicitly tests whether the read/write
port is performing a write to the same address, and if so, uses the written
data. The reason for including this explicit test is that the update to the
memory array does not take place until after the alway block has completed executing. Had we not included the test and action in this way, the read
port would read the old value from the array.
exercise 5.19

The revised model is:

module dual_read_write_SSRAM
( output reg [15:0] d_out1,
input
[15:0] d_in1,
input
[11:0] a1,
input
en1, wr1,
output reg [15:0] d_out2,
input
[15:0] d_in2,
input
[11:0] a2,
input
[11:0] en2, wr2,
input
clk );
reg [15:0] data_RAM [0:4095];
always @(posedge clk) // port1
if (en1)
if (wr1) begin
data_RAM[a1] <= d_in1; d_out1 <= d_in1;
end
else
d_out1 <= data_RAM[a1];
always @(posedge clk)

// port2

Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog 21 September 2007.
2007 by Elsevier Inc. Reproduced with permission from the publisher.
solutions for chapter 5

For the data word 01101001:

e1 = d1 d2 d4 d5 d7 = 1 0 1 0 1 = 1
e2 = d1 d3 d4 d6 d7 = 1 0 1 1 1 = 0
e4 = d2 d3 d4 d8 = 0 0 1 0= 1
e8 = d5 d6 d7 d8 = 0 1 1 0= 0
So the ECC word is 011001001101.
exercise 5.26

a) The check bits read from memory are 0110.

The check bits computed from the data bits of the ECC word are
e1 = e3 e5 e7 e9 e11 = 0 1 0 1 0 = 0
e2 = e3 e6 e7 e10 e11 = 0 1 0 0 0 = 1
e4 = e5 e6 e7 e12 = 1 1 0 1= 1
e8 = e9 e10 e11 e12 = 1 0 0 1= 0
The syndrome is 0110 0110 = 0000. Thus, there is no error in the read
ECC. The data is 10010010.
b) The check bits read from memory are 1100.
The check bits computed from the data bits of the ECC word are
e1 = e3 e5 e7 e9 e11 = 0 1 0 1 0 = 0
e2 = e3 e6 e7 e10 e11 = 0 1 0 0 0 = 1
e4 = e5 e6 e7 e12 = 1 1 0 0= 0
e8 = e9 e10 e11 e12 = 1 0 0 0= 1
The syndrome is 1010 1100 = 0110. Thus, there is an error in bit e6 of
the read ECC. That bit should be flipped back from 0 to 1, giving the corrected ECC word 000110011000. The data is 00010010.
c) The check bits read from memory are 1101.
The check bits computed from the data bits of the ECC word are
e1 = e3 e5 e7 e9 e11 = 1 1 1 0 1 = 0

93

Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog 21 September 2007.
2007 by Elsevier Inc. Reproduced with permission from the publisher.

94

solutions for chapter 5

e2 = e3 e6 e7 e10 e11 = 1 0 1 1 1 = 0
e4 = e5 e6 e7 e12 = 1 0 1 1= 1
e8 = e9 e10 e11 e12 = 0 1 1 1= 1
The syndrome is 1100 1101 = 0001. Thus, there is an error in bit e1 of
the read ECC. That bit should be flipped back from 0 to 1, giving the corrected ECC word 111011011100. The data is 11101011.
exercise 5.27
check word bits is:
d16 d15 d14 d13 d12 d11 d10 d9

d8

The correspondence between data-word bits and

d7

d6

d5

d4

d3

d2

d1

e21 e20 e19 e18 e17 e16 e15 e14 e13 e12 e11 e10

e9

e8

e7

e6

e5

e4

e3

e2

The Boolean equations for the check bits are:

e1 = e3 e5 e7 e9 e11 e13 e15 e17 e19 e21
= d1 d2 d4 d5 d7 d9 d11 d12 d14 d16
e2 = e3 e6 e7 e10 e11 e14 e15 e18 e19
= d1 d3 d4 d6 d7 d10 d11 d13 d14
e4 = e5 e6 e7 e12 e13 e14 e15 e20 e21
= d2 d3 d4 d8 d9 d10 d11 d15 d16
e8 = e9 e10 e11 e12 e13 e14 e15
= d5 d6 d7 d8 d9 d10 d11
e16 = e17 e18 e19 e20 e21
= d12 d13 d14 d15 d16

e1