Beruflich Dokumente
Kultur Dokumente
1/07)
Date of Birth
Title
Academic Session
2010/2011
CONFIDENTIAL
RESTRICTED
OPEN ACCESS
SIGNATURE
SIGNATURE OF SUPERVISOR
881212-01-6032
Date :
NOTES :
NAME OF SUPERVISOR
Date :
* If the thesis is CONFIDENTIAL or RESTRICTED, please attach with the letter from
the organisation with period and reasons for confidentiality or restriction.
MAY 2011
I hereby declare that I have read this thesis and in my opinion this thesis is
sufficient in terms of scope and quality for the award of the degree of Bachelor of
Engineering (Electrical - Microelectronics).
Signature
Supervisor
Date
ii
I declare that this thesis entitled Design and Characterization of Biaxial Strained
Silicon CMOS is the result of my own research except as cited in the references.
The thesis has not been accepted for any degree and is not concurrently submitted in
candidature of any other degree.
Signature
Name of Candidate
NUR ERSHADIAH
Date
iii
Specially dedicated to
my beloved mother, father, and sisters
and someone who inspired me all of these years.
iv
ACKNOWLEDGEMENT
Alhamdulillah, the author would like to express her utmost gratitude to the
project supervisor, Prof. Dr. Razali Bin Ismail for his ultimate dedication of supervision,
guidance, and motivation to the author to complete the project. His advices and
motivations have kept the author in the track and achieve the aim of the project.
Appreciation should also be extended to doctoral candidate, Miss Kang Eng
Siew becoming the authors mentor besides her selfless help and guidance throughout
this project. Not to forget, Mr. Yeap Kim Ho from Universiti Tuanku Abdul Rahman for
his guidance and help to the author.
Next, the gratitude should be expressed to the authors beloved parents, family
and sisters. The support and love given by them has inspired the author to finish the
project on the estimated time.
Lastly, to the authors friends, Akmal Hayati Rusli, Nurulsyahida Ishak, Sabariah
Mohamad Ali, Aimie Amalina Azman, Siti Zubaidah Tumari, Norsaradatul Akmar
Zulkifli, Nabilah Yusoff, Nadiah Abdul Razak, Nurul Nadia Ramli, Wan Haszerila Wan
Hassan, Nursyifa Zainal Abidin, Noraliah Aziziah Md.Amin, Hafiz Izzuddin Julaihi,
Muhd. Firdaus Yusof, and lots more, the author would like to thank them for their
support, love and trust besides sharing the knowledge and motivated her all of this
while. Thank you to all, very much.
ABSTRACT
vi
ABSTRAK
Bagi memenuhi permintaan yang tinggi terhadap peranti elektronik yang kecil
dan laju telah menghasilkan era penambahbaikan peranti semikoduktor konvensional.
Semakin banyak usaha telah dijalankan bagi mengatasi masalah pengskalaan, dimana ia
mematuhi Moores Law. Kebelakangan ini, pengskalaan dilihat semakin mencapai tahap
limitasi, maka, silicon tegang merupakan kaedah terkini untuk mencapai hasil yang sama
seperti pengskalaan, tanpa perlu mengubahsuai saiz peranti elektronik. Prestasi peranti
elektronik bolek diperbaiki dengan menambah lapisan silicon tegang didalam MOSFET.
Tujuan menambah lapisan nano silicon tegang didalam MOSFET adalah untuk
menambah pergerakan pembawa dan menambahbaik kelajuan peranti. Walau
bagaimanapun, penyelidik menghadapi beberapa limitasi seperti kesan saluran pendek
yang tidak dapat dielakkan. Objektif projek ini adalah untuk menjalankan kajian
terhadap dwipaksi silicon tegang CMOS. Projek ini dibantu oleh SILVACOs
International Technology Computer Aided Design (TCAD) tools. Proses telah
dibahagikan kepada dua bahagian, iaitu rekabentuk dan simulasi menggunakan perisian
SILVACOs ATHENA, dan proses terakhir adalah analisis cirri-ciri peranti, dibantu oleh
perisian SILVACOs ATLAS. Analisis terhadap hasil dapatan dalam sifat-sifat elektrik
seperti subthreshold swing, drain induced barrier lowering (DIBL) dibandingkan
dengan CMOS konvensional. Kesimpulan beserta cadangan untuk penambahbaikan turut
disertakan didalam projek ini.
vii
TABLE OF CONTENT
CHAPTER
TITLE
PAGE
DECLARATION
DEDICATION
iii
ACKNOWLEDGEMENT
iv
ABSTRACT
ABSTRAK
vi
TABLE OF CONTENT
vii
LIST OF TABLES
xii
LIST OF FIGURES
xiii
LIST OF ABBREVIATIONS
xvii
LIST OF SYMBOLS
xix
LIST OF APPENDICES
xx
INTRODUCTION
1.1 Background of Study
1.3 Objectives
1.4 Scope
viii
7
8
2.1.2 PMOSFET
12
12
13
2.1.3 CMOS
2.2 Short Channel Effect
13
15
16
17
18
19
20
20
21
22
23
23
23
24
ix
25
25
25
26
3.1 Methodology
26
3.2 Flowchart
28
30
30
31
31
32
3.3.1.1.3 MASKVIEWS
33
35
36
39
40
41
42
44
x
4.1.1.6 Deposition and Patterning of Polysilicon
44
46
48
48
50
50
52
54
62
62
64
65
68
70
72
76
CONCLUSION
77
77
79
79
79
xi
80
80
81
REFERENCES
83
APPENDICES
86
xii
LIST OF TABLES
TABLE NO.
TITLE
PAGE
1.1
2.1
22
4.1
54
5.1
72
5.2
75
5.3
76
5.4
76
6.1
78
xiii
LIST OF FIGURES
FIGURE NO.
TITLE
PAGE
2.1
2.2
NMOS structure
2.3
Induced NMOS
10
2.4
11
2.5
11
2.6
11
2.7
PMOS structure
12
2.8
CMOS structure
13
2.9
14
2.10
15
2.11
17
2.12
18
2.13
20
2.14
21
2.15
21
2.16
23
xiv
2.17
24
3.1
28
3.2
Segmentation of project
29
3.3
29
4.1
37
4.2
37
4.3
38
4.4
39
4.5
40
4.6
41
4.7
41
4.8
42
4.9
42
4.10
43
4.11
43
4.12
43
4.13
44
4.14
45
4.15
Layer of Polysilicon
45
4.16
45
4.17
Etched Polysilicon
46
4.18
46
xv
4.19
Oxidized Polysilicon
47
4.20
47
4.21
48
4.22
49
4.23
49
4.24
50
4.25
51
4.26
Reflected structure
51
4.27
52
4.28
53
4.29
53
4.30
55
4.31
56
4.32
57
4.33
58
4.34
58
4.35
59
4.36
59
4.37
60
4.38
61
5.1
63
5.2
64
5.3
66
xvi
5.4
67
5.5
68
5.6
69
5.7
70
5.8
71
5.9
71
5.10
73
5.11
74
5.12
75
6.1
80
6.2
81
6.3
82
xvii
LIST OF ABBREVIATIONS
MOSFET
CMOS
RAM
TCAD
DIBL
UTM
NMOS
PMOS
SiGe
Silicon Germanium
DOS
Density of States
GaAs
Gallium Arsenide
FYP
PBL
Problem-Based Learning
sSi
Strained Silicon
EDA
IC
Integrated Circuit
GUI
SOI
Silicon On Insulator
xviii
VLSI
STI
DC
Direct Current
AC
Alternating Current
HEMT
LED
LASER
CCD
NVM
Non-volatile Memory
xix
LIST OF SYMBOLS
ID
Drain current
VDS
Drain-to-source voltage
VGS
Gate-to-source voltage
VT
Threshold Voltage
VSB
Source-to-body voltage
VDB
Drain-to-body voltage
Leff
Subthreshold Swing
Width
Length
xx
LIST OF APPENDICES
APPENDIX
TITLE
PAGE
85
87
89
92
94
96
98
101
103
105
107
110
xxi
112
116
119
M
N
114
CHAPTER 1
INTRODUCTION
MOSFET family is divided into three most common types, NMOS, PMOS and
CMOS, which consists of both NMOS and PMOS. CMOS the abbreviation of
Complementary Metal Oxide Semiconductor Field Effect Transistor technology is
widely used in microcontrollers, microprocessors, static RAM, and also in other digital
2
logic circuits. For its variety usage, it is also been used in analog circuits, such as data
converters, image sensors, and highly integrated transceivers in the communication field.
The most important characteristics of CMOS are its high noise immunity and low static
power consumption.
Silicon is one of natures compounds that have been used widely in the
semiconductor technology for years. It is a tetravalent metalloid or semimetal chemical
element that is less reactive than its chemical analog carbon. Silicon comes in atomic
number of 14. The most natural-famous form of silicon found in nature in dusts and
sands is silicon dioxide or silicates. Because of its native oxide that is easily grown in a
furnace and it forms a better dielectric and semiconductor interface compared to the
other material, silicon remains as the most popular material used in semiconductor
technology. Strained silicon MOSFET has been known for increasing the speed,
mobility and reducing power consumption of conventional MOSFET2.
A general term for Si1-xGex is SiGe, which is widely used in the semiconductor
technology to be matched with silicon and produced strained silicon. Since the
3
fundamental scaling has its own limitation caused by the short channel effect, SiGe
extends the chance of improving the performance of MOSFETs. The 4.2% lattice
mismatch between Si and SiGe layer is used to create strained layer to enhance the
carrier transport in the MOSFETs channel4. Theoretical calculations5-9 predict electrons
and holes mobility enhancements in strained Si MOSFETs.
In this project, biaxial strained silicon CMOS has been chosen to be studied to obtain
the characteristics of biaxial strained silicon CMOS and to compare it with the
performance of the conventional CMOS. Recent studies in semiconductor technology
specialized in strained silicon has proven that the performance of strained silicon CMOS
is much better than the conventional CMOS.
1.2
Problem of Statement
4
1.3
Objectives
1.4 Scope
Biaxial strained silicon CMOS is modified from the conventional CMOS and the
characteristics of the device is studied. The design and the fabrication process of biaxial
strained silicon CMOS is done by using SILVACOs ATHENA software. The
SILVACOs ATLAS software is used to simulate and to obtain the devices
characteristics. Lastly, analysis is done to the result to investigate the electrical
properties of the biaxial strained silicon CMOS, and compared it to the conventional
one, and the project is concluded.
Some electrical characteristics that are studied in the project including the
threshold voltage, subthreshold swing, and drain induced barrier lowering (DIBL). For
every step in simulation process, caution has been taken to ensure the accurate CMOS
that has been designed is simulated.
5
1.5
Previous research held by UTM students and researchers focused on PMOS and
NMOS. In the year of 2007, some researches were done on uniaxial strained silicon
PMOS
10-11
. In 2010, Biaxial strained silicon NMOS has been designed virtually, using
12
The study focused on 45nm biaxial strained silicon MOSFET, since the technology
now has reach 32nm nano regime. Former research proved that the study is still valid
and can be done extensively. The results of the researches are summarized in Table 1.1
to compare with the result in this project.
6
Table 1.1: Summary of previous researches
Characteristics
Threshold Voltage
(Vd=0.1V)
Subthreshold Swing
(mV/dec)
DIBL (mV/V)
Mobility enhancement
at Vgs=3V (%)
0.571733(90nm)12
0.581068(150nm)12
186.153 10
112.8 12
693.564 10 / 303.411
354 12
25.65% 10
-Hole mobility enhancement
35.7% 12
-Electron mobility
enhancement
CHAPTER 2
2.1
Overview of MOSFET
8
MOSFET is divided into three main types, PMOS, NMOS and CMOS. MOSFET
operates when a voltage is applied across it. Let us review an example of a p-type
semiconductor. When a positive voltage is supplied at the gate, it creates a depletion
layer by forcing the positive charged majority carrier (in this case hole for p-type)
away from the gate insulator interface, and leave an exposed carrier-free region of
negative charged acceptor. When the voltage supplied at the gate is high enough, high
concentration of negative charge carrier will form an inversion layer a very thin layer
next to the interface between the insulator and semiconductor.
2.1.1 NMOSFET
NMOS is built with p-type material as the substrate. The plus (+) notation on n+
indicates the n-type material/region are heavily doped material. An insulator which is
made of a thin layer of silicon oxide (SiO2) is grown on the substrates surface, and
covering the area between the source and drain. Metal is deposited at four different
terminals, which are labeled as Source (S), Gate (G), Drain (D), and Body (B).
When a positive voltage is applied at the gate terminal, it causes the free holes
(positive charges) to be repelled from the region of the substrate, under the gate. Then,
these holes are push downwards into the substrate, creating a carrier depletion region.
The depletion region is made from the negative charges, due to the neutralizing holes
that have been pushed down. The gate voltage, which is positive, will attract electrons
from the n-wells, forming an n channel that connects the source and the drain. Thus,
current will flow through the induced region. The current flow from drain to source,
since the current, iD is carried by free electrons from source to drain. The current
magnitude depends on the electrons density in the channel, which depends on V GS >
VT.
If VGS > VT, the channel will increases, and the resistance across the channel is
reduced or the conductance is increased. The conductance of the channel is proportional
to the excess gate voltage, which is known as effective voltage.
10
Cutoff region When VGS < VT, there is no inversion layer present under
the surface. At VDS = 0, the source and drain depletion regions are
symmetrical. A positive VDS reverse biases the drain substrate junction,
hence the depletion region around the drain widens, and since the drain is
adjacent to the gate edge, the depletion region widens in the channel.
However, there is no current flows even for VDS > 0, since no conductive
channel is present and ID = 017.
II.
III.
11
12
2.1.2 PMOSFET
PMOS is built with n-type material as the substrate. The plus (+) notation on p+
indicates the p-type material/region are heavily doped material. An insulator which is
made of a thin layer of silicon oxide (SiO2) is grown on the substrates surface, and
covering the area between the source and drain. Metal is deposited at four different
terminals, which are labeled as Source (S), Gate (G), Drain (D), and Body (B).
13
2.1.2.2 PMOS Operation
A PMOS operates in a similar way as the NMOS, except that V GS, VDS and the
threshold voltage VT are negative values. The current flow through the channel, iD enters
the source terminal, and leaves through the drain (opposite to the NMOS)
For summary, the PMOS device operates at:
I.
Cutoff region the device is turned off when VGS > VT, and turned on
VGS < VT.
II.
III.
2.1.3
CMOS
14
The PMOS part has been designed so that the PMOS can only receive an input,
either from the source (voltage source) or from the other PMOS transistor. The NMOS
part works similarly. It can only receive an input either from the ground, or from the
other NMOS transistor.
In the PMOS part, the composition of its structure has created a low resistance
every time a low voltage is applied through it, and similarly, when a high voltage is
applied, it creates a high resistance in it. Contrary, in the NMOS part, when a low
voltage is applied, it creates a high resistance and when a high voltage is applied on it, it
creates a low resistance.
There are two cases of the operation of CMOS device, when a low voltage is
applied, and when a high voltage is applied. Both cases have a similar flow of operation.
15
a) When low voltage is inserted: At NMOS part, if the input is a low voltage
supply, the NMOS creates a high resistance, and it prevents the voltage from
leaking into the ground. At the PMOS part, if the input is low voltage, it allows
the input to go through the PMOS transistor straight to the output. The output
will be a high voltage.
b) When high voltage is inserted: When a high voltage is inserted, PMOS transistor
will produce a high resistance and it will automatically block the voltage source
from the output. At the NMOS part, it will be a low resistance, and allows the
output to move from the drain to the ground. The output will eventually register
as a low voltage.
2.2
If the channel length of a MOSFET is the same order of magnitude as the depletionlayer widths (xdD, xdS) of the source and drain junction, the MOSFET is considered as
short MOSFET. To improve the operational speed of a device and to increase the
number of components per chip, the channel length should be altered. Unfortunately, the
short channel effect will arise when the channel length, Leff is reduced. Two phenomena
are attributed by the short channel effects, which are the limitation imposed on electron
16
drift characteristic in the channel, and the modification of the threshold voltage due to
the shortening channel length3. Basically, there are five significant short channel effects
that can be observed, which are the drain induced barrier lowering (DIBL) and
Punchthrough, surface scattering, velocity saturation, impact ionization and hot
electrons.
2.2.1
. (1)
Or
. (2)
Based on the equations, when the depletion regions surrounding the drain
extends to the source, until the two depletion layer can merge (xdS + xdD = L),
punchthrough will eventually occurs. Thinner gate oxides, larger substrate doping,
shallower junctions, and obviously with longer channels can minimized the effects of
punchthrough3. Creating and sustaining the inversion layer on the surface of a MOSFET
will influence the current flows in the channel. When the gate bias voltage is not
sufficient to invert the surface (i.e. VGS<VT0), a potential barrier will block the flow of
the carriers (electrons) in the channel. By increasing the gate voltage, it will reduced the
potential barrier and, thus, allowing the carriers to flow under the influence of the
channel electric field. In small-geometry MOSFETs, the gate-to-source voltage VGS and
the drain-to-source voltage VDS are controlling the potential barrier. Once the drain
voltage is increased, the potential barrier in the channel will decreases, creating an effect
called drain induced barrier lowering (DIBL). Electrons can flow between the source
17
and drain when the potential barrier is reduced, even if the VGS is lower than VTO
(threshold voltage). The current that flows under the condition of V GS<VTO is called a
sub-threshold current.
There are several ways to reduce the punchthrough effect, but the simplest way is
to increase the overall bulk doping level. As the doping in the bulk increases, the drain
and source depletion regions will become smaller, and it will not establish a parasitic
current path. Unfortunately, this method is not the most efficient one since increasing the
bulk doping will increase the subthreshold swing at the same time. Some other method
that will not affecting subthreshold swing are delta doping, halo and pocket implants.
Figure 2.11: Several ways to reduce punchthrough effects (a) delta doping (b) halo (c)
pocket implants
2.2.2
Surface Scattering
Due to the lateral extension of the depletion layer into the channel region, the
channel length becomes smaller, the longitudinal electric field component (x) increases,
and the surface mobility becomes field-dependent. Since the carrier transport in a
MOSFET is confined within the narrow inversion layer and the surface scattering cause
reduction of the mobility, the electrons move with great difficulties, parallel to the
18
interface. This will results the average surface mobility to become about half as much as
that of the bulk mobility, even for small values of x. Surface scattering is the collisions
suffered by the electrons that are accelerated toward the interface by x3.
Figure 2.12: Inversion layer, depletion region and the surface scattering effect
2.2.3
Velocity Saturation
19
lowering the voltage bias. The maximum gain that is possible for a MOSFET, by using
VDE (sat), can be defined as
.................. (3)
2.2.4
Impact Ionization
With the presence of high longitudinal fields that generate electron-hole pairs,
impact ionization occurs when the high velocity of electrons exist. By impacting on
silicon atoms and ionizing the atoms, impact ionization occurs, especially in NMOS.
Most of the electrons are attracted by the drain, while the holes will enter the substrate to
form an art of the parasitic substrate current3.
The source region plays the role of the emitter, the drain region plays the role as
the collector, and the region between the source and the drain plays the role as the base
of an npn. When the source is collecting the holes, the corresponding hole current will
create a voltage drop, right in the substrate material. The normal reverse biased
substrate-source pn junction of 6V will conduct appreciably. Only then electrons can be
injected from the source to the substrate3, most likely to be similar as electrons that have
been injected from the emitter to the base. As the electrons travel towards the drain, it
gained enough energy to create new electron-hole pairs. If some electrons generated due
to high fields escape from the drain field to travel into the substrate, it will affect the
other devices on the chip and worsen the situation.
20
2.2.5
Hot Electrons
Hot electrons refer to high energy electrons, which enter the oxide layer and trapped,
that will affecting the oxide, to rise to oxide charging. It accumulates with time, and
degraded the performance of the device by increasing the threshold voltage, V T, affects
its conveyed conductance, and affects adversely the gates control on the drain current 3.
21
2.3.1
Figure 2.14: (Left) Pure silicon and Silicon Germanium (Right) Strained silicon after
being matched with Silicon Germanium
22
eventually stretched /strained to match the SiGe atoms as SiGe atoms molecular
structure is much wider. The strained silicon obtained after the process have less
resistance compared to the pure one, which leads to the improvement in the device
performance.
performance of the device without the need of altering them to make it smaller.
2.3.2
Strained Si (SS) MOSFETs are device structures that take advantage of straininduced enhancement of carrier transport in silicon. When a thin layer of Si is
pseudomorphically grown on a thick, relaxed SiGe layer, the lattice constant of the Si
film conforms to that of the SiGe layer, and the lattice mismatch between Si and SiGe
leads to biaxial tensile strained in the Si layer. If the SiGe layer is fully relaxed and the
Si layer fully strained, the amount of strain in Si is approximately 4.2 x x% where x is
the Ge mole fraction in the SiGe layer13. The type of stress needed for MOSFET is
sectioned in Table 2.1.
NMOS
PMOS
Tension
Compression
Tension
Tension
Compression
Tension
Out of Plane
23
2.3.3
All 90, 65, and 45nm high performance logic technologies adopted uniaxial
process induced strained silicon. Uniaxial stress could provide a low channel direction in
plane conductivity mass, large out-of-plane in confinement mass, and high in-plane
density of states (DOS) to the ground hole subband14. A tensile capping layer is formed
right on top of the Strained SiGe gate. At the area between source and drain, strained
silicon is introduced.
24
substrate15. Strained silicon is introduced at the region between the source and the drain
region, and a relaxed SiGe layer is placed at the top of the bulk, right under the strained
silicon layer. The bottom part of the device will be the silicon substrate layer.
2.4
25
2.4.1
2.4.2
Since the interatomic atoms in the strained silicon have been stretched, it allows
electrons to move faster, which means that it creates a lower resistance region.
Fortunately, the power consumption in the device will be reduced as the resistance is
lowered.
2.4.3
26
CHAPTER 3
3.1
Methodology
Several stages in the project were done to complete the project in the estimated
time. Stages were carefully planned to fit the schedule and also the submission of the
project, part by part.
Stage 1: The title, problem, objectives and scope is determined
Problem is determined, and relevant title with objectives and scopes to focus is
chosen.
Conduct literature studies on CMOS, strained silicon, biaxial and uniaxial strained
silicon.
27
Stage 3: FYP 1 Seminar
PBL Lab of SEW 4722 is reviewed to get familiar with the ATLAS and
ATHENA software.
User manual of ATHENA, ATLAS and MASKVIEWS are used extensively to help
the fabrication and characterization process.
Final thesis is written with binding hard cover and submitted to the faculty.
28
3.2
Flowchart
29
Biaxial sSi
CMOS
Conventional &
sSi PMOS
Conventional &
sSi NMOS
CMOS (Layout)
Analyze
Characteristics
Analyze
Characteristics
CMOS
Structure
SILVACO
ATLAS
SILVACO
ATHENA
SILVACO
MASKVIEWS
PRODUCT
30
3.3
TCAD Tools
Nowadays, simulation tools are very popular in the design section to aid the
designers to obtain the optimized desirable result. In electrical engineering field itself,
stages from digital design to circuit level design, are using simulation tools in every
aspect to obtain the accurate characteristics and results. In this project, ATHENA and
ATLAS have been chosen to aid the author throughout the project.
31
3.3.1.1 TCAD Software
32
Set popups that provide full language and run-time support for each simulator
Many input file creation and debug assist features, such as run, kill, pause, stop at,
and re-start
graphic features such as pan, zoom, views, labels and multiple plot support. TONYPLOT
also provides many TCAD specific visualization functions, 1D cut lines from 2D
structures, animation of markers to show vector flow, integration of log or 1D data files
and fully customizable TCAD specific colors and styles.
Some of the key features of TONYPLOT are:
Plotting engine supports all common 1D and 2D data views including: 1D x-y
data, 2D contour data, 2D meshed data, smith charts and polar charts
Exports data in many common formats for use in reports or by third party tools.
Supported formats include; jpg, png, bmp, Spice Raw File and CSV
33
Integrated suite of probes, rulers, and other measurement tools allows detailed
analysis of 1D and 2D structures
Function and Macro editor allows complex functions and macros to be defined
that can be visualized as normal 1D quantity. This feature allows calculation of
M-Plots for OLED devices
Fully customizable including; colors, materials, legends, toolbars and shortcuts 20.
3.3.1.1.3 MASKVIEWS
34
Any part of the layout can be simulated the most interesting process, and
without the hassle of structuring the codes in ATHENA; you can obtain the accurate
design based on the layout that has been accurately designed. MASKVIEWS also provides
features to allow layout experimentation such as misalignment, polygon over sizing or
under sizing, global rescales and region definition depending on combinations of
present mask elements21.
35
CHAPTER 4
4.1
Design of MOSFET
In this chapter, we will be discussing the important part of this project, which is
designing MOSFETs PMOS, NMOS and CMOS. Basically, the design of NMOS and
PMOS are the same, except the source/drain doping and the VTH adjustment for NMOS.
That means the material is either Arsenic or Phosphorus. The substrate for NMOS is a
p+ material, so it will be Boron. As for PMOS - the doping at the source and drain, and
also the threshold voltage adjustment is p+ material; which means it is Boron.
Next, the distinct difference between the conventional MOSFET and the strained
silicon MOSFET is minor that is the strained silicon will have two additional layers
Silicon Germanium layer on top of the substrate and Silicon layer on top of the Silicon
Germanium layer. The author would like to declare that only strained silicon NMOS will
be discussed as the flow of conventional and biaxial strained silicon is quite similar
except that conventional MOSFET does not have a silicon and SiGe layers. A bulk
CMOS design will be discussed in the subsequent subtopic.
36
37
Define mesh,
initialize
substrate
Metallization
and Contact
Patterning
Reflect
Structure
Electrode
labeling
Add epitaxial
layer
Source Drain
Annealing
Tonyplot
Gate Oxidation
formation
Polysilicon
Oxidation
Concentration
view and
Measurement
Threshold
Voltage
Adjustment
Polysilicon
patterning
Source Drain
Annealing
Metallization
and Contact
Patterning
Add epitaxial
layer
Polysilicon
Oxidation
Reflect
Structure
Electrode
labeling
Deposition of
Silicon and SiGe
layer
Polysilicon
patterning
Tonyplot
Gate Oxidation
formation
Threshold
Voltage
Adjustment
Concentration
view and
Measurement
38
Note that the only difference between the conventional MOSFET and the biaxial
strained silicon MOSFET is only the deposition of Silicon and Silicon Germanium
layers. This is a simplified version of designing a MOSFET and of course, a much more
detail process do exists. Lets discuss each part of the process starting from the first one,
thoroughly.
The very basic step is to know how to use DECKBUILD of SILVACO TCAD
Tools. DECKBUILD can only be ran in UNIX prompt which means that the next
important thing is to have a computer with UNIX and a SILVACO licensed software.
Open terminal and create a folder to specify the location of the design that will be
created. Since DECKBUILD is a very convenient and user-friendly tool, it is easy to
familiarize with it.
39
4.1.1.1 Mesh Definition and Substrate Initialization
At the horizontal or x-line, the line has been set up to be denser at the right of the
structure with the space of 0.025 microns. This region will be the critical region of the
device, where the flow of current and channel formation will occur here. At the vertical
or y-line, almost an even mesh is created. The dimension of the device structured is
0.5 microns x 0.3 microns. Note here that the dimension specified here is only the
dimension that will be generated straight away from the codes. After reflecting it, the
dimension will be 1 microns x 0.3 microns.
40
The structure then is initialized by defining the wafer or the substrate of the
device. This is the step where the dopants of the device is determined whether it is a
PMOS or NMOS device. In this case, since it is a NMOS device, the dopant is Boron
which is a p+ material. The concentration is set to be 2 x 1018 cm-3, and a <100>
orientation with two-dimensional substrate is chosen.
Note that this is the code for generating a NMOS structure. For a PMOS
structure, the substrate should be doped with an n+ material, which is either Phosphorus
or Arsenic.
Adding epitaxial layer is a process of depositing a thin single layer crystal over a
single crystal substrate. This process is mandatory to minimize the latch-up occurrence
in VLSI (Very Large Scale Integrated Circuit) design, thus allowing a better
controllability in doping concentration and improves the device performance. Normally
the material used in epitaxial layer is the same material with used in its substrate, which
means that, for NMOS, the substrate is Silicon doped with Boron, and for PMOS is
Silicon doped with Phosphorus.
41
Epitaxial layer
Substrate
Figure 4.7: View of Epitaxial Layer and Substrate with Grid Definition
42
first, and then SiGe with germanium mole fraction of 0.35, and on top of it is a thin
single layer of Silicon.
To obtain the gate oxide layer, an oxide layer is diffused after the deposition of
Silicon and SiGe layers. Since a very thin oxide layer needed, diffuse time is minimized
and Dry O2 process is preferred since oxide tends to grown faster in Wet O2 condition.
43
Here, a thin layer of gate oxide of thickness less than 6nm is desired. The temperature
used normally is higher than 800c since Silicon can only be oxidized in temperature
higher than 800c.
# Gate Oxidation
diffus time=7 temp=900 dryo2 press=1.00 hcl.pc=3
Figure 4.10: Codes for diffusing gate oxide
Oxide Layer
To obtain the accurate thickness, the thickness of gate oxide is the extracted to a
log file that can be open via Microsoft Excel.
44
4.1.1.5 Threshold Voltage Adjustment
The next step is to implant material for threshold voltage adjustment. This
process is needed to determine the threshold voltage. The lower the concentration of the
dopant, the lower the threshold voltage will be. The material used should be the same as
the material used in the MOSFET device. For NMOS, Boron is used, and for PMOS,
Phosphorus is used. Moderate energy is used as it does not need big junction. The
determination of threshold voltage concentration is highly related to the formation of
gate oxide. Reducing the thickness of gate oxide requires a reduction in threshold
voltage. In other words, thin gate oxide needs a small voltage to turn it on.
Figure 4.13: Codes for implanting the doping for threshold adjustment
45
the length of etched Polysilicon in this process is needed to obtain the accurate desirable
result.
Polysilicon
Layer
# Etch Poly
etch polysilicon left p1.x=0.408093
Figure 4.16: Codes for patterning polysilicon
46
Etched
Polysilicon
Layer
The Polysilicon is then oxidized to create the effect of insulation on top of the
Polysilicon. In this project Polysilicon is diffused in a temperature of 900c since Silicon
can only be oxidized in a temperature above 800c. Wet O2 is preferred so that the oxide
layer can be grown faster.
# Poly Oxidation
method Fermi
diffus time=3 temp=900 weto2 press=1.00
47
The next crucial step is the Polysilicon doping. This step is needed to alter the
junction of source drain and to ensure the conductibility of the Polysilicon gate. For
NMOS, Polysilicon is doped with an n+ material; while for PMOS, Ploysilicon is doped
with a p+ material. Since TCAD tools has its own limitation, which is etching the
Polysilicon might not affect the channel length when the channel length is too short, you
may found out that altering the doping concentration of Polysilicon is somehow useful to
obtain the accurate desirable channel length. In this process, Polysilicon is implanted
with 5x1014cm-3 Phosphorus with a small amount of energy.
# Poly Doping
implant phosphor dose=5.0e14 energy=13 crystal
48
4.1.1.8 Spacer Oxide
To prevent ions from being implanted to the gate, a layer of spacer oxide with
thickness of 0.12microns is deposited and then etched. Normally the thickness of the
spacer oxide is only about 10% of the Polysilicon thickness. Since the thickness of
Polysilicon is 0.2 microns, the thickness of spacer oxide can be 0.02 microns. However,
this condition is not mandatory.
Right after spacer oxide process, the source and drain formation is done. The
device is implanted with a dopant of 1 x 1016 cm-3. For NMOS, the dopant is an n+
material such as Phosphorus or Arsenic, and for PMOS, the dopant is a p+ material,
which is Boron. This process is also called ion implantation, where a chemical species
directly bombarded into a substrate with a high energy ions of the chemical for
deposition.
49
Thermal diffusion process has been replaced by ion implantation process for
doping a material in wafer fabrication since it the control of the process of depositing
dopants atoms into the substrate, is much more precise as compared to the thermal
diffusion process. However, the damage caused by atomic collisions during ion
implantation changes the electrical characteristics of the target. Many target atoms are
displaced, creating deep electron and hole traps which capture mobile carriers and
increase resistivity. To repair the lattice damage and inserting the dopant in
substitutional sites where they can be electrically active again, annealing is therefore
needed in this process 11.
Source/Drain region
50
After the formation of body, gate, source and drain, the structure is the ready for
the next step, which is depositing and patterning the contact. When contact is deposited,
the layer of metal is electrically interconnected the device fabricated on the silicon
substrate. The material used for the contact is Aluminium, since it has a very low
resistivity (high conductivity) and its adhesion compatibility with SiO2. In this step, a
very thin layer of metal which in this case is Aluminium, is deposited, and a portion of
it is etched away, leaving a contact right on top of the source and drain region.
# Aluminium Deposition
deposit aluminum thick=0.03 divisions=2
# Etch Aluminium
etch aluminium right p1.x=0.18
Figure 4.24: Codes for depositing and patterning Aluminium
Since the structure obtained all the way through these processes is only half of
the device structure, the second final process of structuring a device using ATHENA is
to mirror the structure (if it happens the structure is symmetrical). The process eased the
burden of creating the same step over and over again, thus, minimized the risk of errors
occur in the process of structuring a device.
51
# Mirror structure
struct mirror right
Figure 4.25: Codes for reflecting structure
Finally, the device is then labeled for the ease of analysis and the output file is
created. Labels included source, drain, gate, and backside.
52
# Label structure
electrode name=source left
electrode name=gate x=0.5
electrode name=drain right
electrode name=backside backside
# Struct Outfile
struct outfile=ssin.str
Figure 4.27: Codes for labeling structure and creating output file
The out file of a biaxial strained Silicon NMOS is now obtained. The next step is
to view the structure and measure the channel length of the device and to ensure that the
channel length is the desirable length. By using another advance feature of TONYPLOT
by SILVACO, the effective channel length can be measured by simply viewing the
concentration view and displaying the junction, and zooming right beneath the gate.
Note that the length measured is in microns.
The out file obtained later is exported into ATLAS right after invoking ATLAS
with the command of go atlas. As mentioned earlier, the process of structuring a
conventional NMOS and PMOS is similar to the process of creating biaxial strained
Silicon NMOS and PMOS.
53
# Tonyplot structure
tonyplot ssin.str
54
Table 4.1: Specification of simulated devices
Specification
Effective
Channel
Length (nm)
Gate Oxide
thickness (nm)
Vth at vd=0.1v
Germanium
fraction
NMOS
45
sSi NMOS
45
PMOS
45
sSi PMOS
45
5.7
5.7
5.7
5.7
1.50
-
0.2625
0.35
-1.30
-
-0.80
0.35
MASKVIEWS by SILVACO provided a very handy help which can ease the
burden of creating a complicated device. As you may find typing or even generating the
codes with GUI (Graphical User Interface) is somehow a tedious process for a
complicated device such as Complementary MOSFET, MASKVIEWS is the sole, easiest
solution to this problem.
Some researchers and student tried to construct a CMOS and any other
complicated device using solely ATHENA and ATLAS, including the author. Basically,
55
the structure obtained will have the resemblance of a Complementary MOSFET, and the
STI (Shallow Trench Isolation to isolate between NMOS and PMOS) is simply the
etched Silicon that has been oxidized. But the significance problem arose is that how to
get the accurate effective channel length desired? ATHENA can design and using
TONYPLOT the cross-section of the simulated device can be observed. By using,
MASKVIEWS, layout is designed using top-view of the device, and the characteristics
will be exported to ATHENA to generate the cross-section view.
The only solution is to use MASKVIEWS to produce a GDS layout, and extract it
to ATHENA to produce the structure. Since MASKVIEWS license is not available, the
author could not proceed with this step to create a bulk CMOS and a bulk biaxial
strained silicon CMOS. The author will discuss MASKVIEWS processes by referring to
SILVACO MASKVIEWS manual and journal from SILVACO
21
. The recipe of
simulation should be observed and done carefully, since even with M ASKVIEWS aid, if
the simulation recipe is incorrect, the desirable result could not be obtained. Figure 4.31
56
shows the flowchart to design a CMOS and Figure 4.32 shows the recipe and steps to
design a CMOS.
57
The process recipes and fabrication flows are referred from University of
California, Berkeley Micro lab open source 21.
58
After creating the layout and converting it to GDS II format (industry format),
the parameters generated is sent to ATHENA to construct the structure of a complicated
device.
59
Figure 4.35: Top view and side view of 0.35um CMOS using MASKVIEWS
60
61
62
CHAPTER 5
The design of conventional and strained Silicon MOSFETs has been discussed
thoroughly in the last chapter. The next step conducted in this project is to characterize
the electrical properties of the devices that have been simulated previously, before
comparison and conclusion is made. In this chapter, ATLAS as a device simulator is
discussed as well as the electrical properties of the devices.
5.1
The key features of ATLAS are that ATLAS can accurately characterize physicsbased devices in 2D or 3D for electrical, optical, and thermal performance. This means
63
that ATLAS can characterize without costly split-lot experiments, solve yield and
process variation problems for optimal combination of speed, power, density,
breakdown, leakage, luminosity, or reliability. ATLAS also is fully integrated with
ATHENA process simulation software, comprehensive visualization package, extensive
database of examples, and simple device entry, that can be chosen from the largest
selection of silicon, III-V, II-VI, IV-IV, or polymer/organic technologies including
CMOS, bipolar, high voltage power device, VCSEL, TFT, optoelectronic, LASER,
LED, CCD, sensor, fuse, NVM, ferro-electric, SOI, Fin-FET, HEMT, and HBT, as well
as connect TCAD to Tape-out with direct import of ATLAS results into UTMOST for
SPICE parameter extraction. ATLAS is also worldwide support software 28.
64
5.2
The most commonly used inputs of ATLAS are text file (.txt file) and structure
file (.str file). Commands written in text file can be executed by running the coding
while the structure defined in structure file can also be exported for the device
simulation12.
Besides, ATLAS produces three outputs: run-time output, log files (.log) and
solution files.
warning or error messages if any. Log file (.log file) stores all the terminal current and
voltage values from the device simulation. These values are then extracted and used for
data analysis in Microsoft Excel. Solution file will stores two or three dimension data
that related to the values of solution variables within the device for a bias point12.
Material
model
Specification
Mesh
Region
Electrode
Doping
Structure
Specification
Material
Models
Contact
Interface
Solution
Specification
Method
Numerical
Models
Specification
Log
Solve
Load
Save
Extract
Tonyplot
Result
Analysis
65
To start the device simulation, the input file of structure specification can be read
from another existing file. The input file of ATLAS in this project is taken from the
structure file (.str file) created in ATHENA. The result analysis is done to obtain the
characterizations of biaxial strained Silicon MOSFET and conventional MOSFET in the
following sub chapters12.
5.3
As for PMOS, gate voltage has been ramped from 0V to -3V. A negative voltage
must be applied to the gate in order to make the inversion layer charge equal to zero,
whereas a positive gate voltage will induce a larger inversion1. Drain voltage is biased
with -0.1V and -1V, and the same value is supplied to the conventional PMOS.
66
NMOS
6.00E-05
sSi NMOS
4.00E-05
2.00E-05
-2.00E-05
0.00E+00
2.00E-01
4.00E-01
6.00E-01
8.00E-01
1.00E+00
1.20E+00
1.40E+00
1.60E+00
1.80E+00
2.00E+00
2.20E+00
2.40E+00
2.60E+00
2.80E+00
3.00E+00
0.00E+00
Figure 5.3: ID-VGS of NMOS and strained Silicon NMOS at VDS = 0.1V
From Figure 5.3, graph of ID-VGS of NMOS and strained Silicon NMOS at VDS
= 0.1V, it can be observed that strained silicon NMOS has a threshold voltage around
0.26V. Comparing with conventional NMOS, the same threshold adjustment results a
different threshold voltage. This is one of short channel effects that occur when the
channel length is too small.
67
0.00E+00
-2.00E-01
-4.00E-01
-6.00E-01
-8.00E-01
-1.00E+00
-1.20E+00
-1.40E+00
-1.60E+00
-1.80E+00
-2.00E+00
-2.20E+00
-2.40E+00
-2.60E+00
-2.80E+00
-3.00E+00
-0.00001
-0.000015
PMOS
sSi PMOS
-0.00002
-0.000025
-0.00003
Figure 5.4: ID-VGS of PMOS and strained Silicon PMOS at VDS = 0.1V
From Figure 5.4, graph of ID-VGS of PMOS and strained Silicon PMOS at VDS =
0.1V, it can be observed that strained Silicon PMOS has a threshold voltage around
0.80V. Comparing with conventional PMOS, the same threshold adjustment or threshold
implant concentration results a different threshold voltage. This is one of short channel
effects that occur when the channel length is too small.
68
5.4
As the drain voltage increases, the voltage drop across the oxide near the drain
terminal decreases, which means that the induced inversion charge density near the drain
also decreases. The incremental conductance of the channel at the drain decreases which
then means that, the slope of the ID versus VDS curve will decrease1.
When VDS increases to the point where the potential drop across the oxide at the
drain terminal is equal to threshold voltage, the induced inversion charge density is zero
at the drain terminal. At this point, the incremental conductance at the drain is zero,
which means that the slope o the ID versus VDS curve is zero1.
where
VDS(sat) = VGS - VT
................ (4)
69
As shown in Figure 5.5 of ID-VDS graph, the characteristics of conventional and
strained Silicon NMOS are compared. Results showed that strained Silicon NMOS
drives better drain current compared to the conventional one, for 3V, 2V and 1V gate
voltage. As for PMOS, the strained Silicon added device also proves that it is better
when compared to the conventional PMOS. Since PMOS suffers one of the short
channel effects that is hot electrons effect, the characteristics obtained is not 100%
accurate, but roughly, it compares the performance between strained and conventional
MOSFET.
70
5.5
(a)
(b)
Figure 5.7: Determining DIBL from graph (a) NMOS (b) PMOS
Comparing the DIBL values of conventional NMOS and PMOS by varying the
channel length, the shorter the channel length, the device suffers less DIBL effect, as
shown in Figure 5.4.
71
Figure 5.9: Comparison of DIBL effect between conventional and strained Silicon
MOSFETs
72
Overall, DIBL has been improved quite much by adding strained Silicon into the
MOSFETs structures. The significant improvement concludes that strained silicon is
another alternative besides scaling down the device which will reach its limit.
Table 5.1: Comparison of DIBL with different channel length
DIBL (mV/V)
Effective channel
length, Leff (nm)
5.6
sSi NMOS
NMOS
sSi PMOS
PMOS
45
218
145
695
348
90
35412
410
100
693.56410
911
Subthreshold Swing
73
Weak
inversion
Strong inversion
74
Nowadays, the technology has become so advanced that MOSFETs has been
scaled down to 32nm. It is widely known that varying channel length improves the
overall performance of conventional MOSFETs. The results are then compared to the
previous research so that the effect of scaling down strained Silicon MOSFET can be
observed.
75
The results are then summarized as stated in Table 5.2 below. By comparing the
channel length of the device, it can be seen clearly that the strained Silicon MOSFETs
are better in performance, compared to the conventional ones.
NMOS
sSi PMOS
PMOS
45
109
155
122
149
90
112.812
16412
100
186.15310
21410
76
5.7
Result Comparison
Results are then compared, between varying the channel length of conventional
MOSFETs, and varying the channel length of biaxial strained Silicon MOSFETs, and
comparing results between conventional and biaxial strained Silicon MOSFETs.
Table5.3: Comparison between conventional and biaxial strained Silicon MOSFETs
NMOS 45nm
Gate Oxide
thickness (nm)
Vth at vd=0.1v
Subthreshold
swing
DIBL
Improvement
of
subthreshold
swing
Improvement
of DIBL
PMOS 45nm
5.7
sSi NMOS
45nm
5.7
5.7
sSi PMOS
45nm
5.7
1.50
155
0.2625
109
-1.30
149
-0.80
122
218
-
145
29.68%
695
-
348
18.12%
33.49%
49.93%
Table 5.4: Comparison between different channel lengths of strained silicon MOSFETs
Gate Oxide
thickness (nm)
Vth at vd=0.1v
Subthreshold
swing
DIBL
Improvement
of
subthreshold
swing
Improvement
of DIBL
sSi NMOS
90nm
11
sSi NMOS
45nm
5.7
sSi PMOS
100nm
-
sSi PMOS
45nm
5.7
0.57153312
112.812
0.2625
109
-0.59689410
186.15310
-0.80
122
35412
145
693.56410
348
3.37%
34.46%
60.58%
49.82%
77
CHAPTER 6
CONCLUSION
6.1
Project Summary
Based on the studies conducted in this project, it can be concluded that biaxial
strained Silicon CMOS is the alternative for improving a conventional CMOS rather
than scaling down the current technology of conventional CMOS. By growing a strained
Silicon layer on top of the relaxed SiGe layer at the channel, this technology allows the
enhancement of the carrier mobility, thus delaying the need for the new gate stack
materials and improving the overall performance of the device. The strained silicon
technology allows us to have a powerful device without the need of scaling down and
minimize the short channel effects that often occur in nanoscale devices.
Biaxial strained Silicon NMOS and PMOS have been designed virtually with the
aid of SILVACO TCAD TOOLS ATHENA and ATLAS. Rather than speeding up the
fabrication process and providing an accurate and optimized result, the simulation also
gave the opportunity to save cost and to alter any design without any hassle. Any small
78
adjustment, in example changing or decreasing the channel length or decreasing the
threshold voltage can be easily done by using ATHENA.
The devices are then characterized by comparing the channel length of 45nm and
90nm. Several characteristics have been carefully observed. Significant improvement
has been noticed by comparing the conventional and biaxial strained silicon CMOS.
Overall, four devices have been simulated in this project with these specifications:
Table 6.1: Summary of device characteristics
Specification
Effective
Channel
Length (nm)
Gate Oxide
thickness (nm)
Vth at vd=0.1v
Germanium
fraction
NMOS
45
sSi NMOS
45
PMOS
45
sSi PMOS
45
5.7
5.7
5.7
5.7
1.50
-
0.2625
0.35
-1.30
-
-0.80
0.35
Subthreshold
Swing (mV/dec)
Improvement in
Subthreshold
Swing (%)
DIBL
Improvement in
DIBL (%)
155
109
149
122
29.68%
18.12%
218
-
145
33.49%
695
-
348
49.93%
79
6.2
Since the scope of the project has been narrowed down, there are several
extensions that can be made for future work. This project can be improved in several
ways and can covers wider topics of MOSFET.
Since the author has improved from 90nm technology to 45nm technology,
which is two steps above, further extension can be made my sizing down the device to
32nm. 32nm is the latest technology adopted by semiconductor companies like Intel
Corporation. Reducing the gate length needs modification in several characteristics,
including the threshold voltage, and doping concentration.
Another important scope that can be extended from this project is the
capacitance-voltage characteristics (C-V characteristics). C-V characteristics give
information about device performance under high/low frequency. Other parameters, for
instance, junction depth and parasitic resistance can be extracted if necessary12.
80
6.2.3 Strained Silicon in Silicon-on-Insulator (SOI)
81
It has been reported that the electrically induced inversion layer is a candidate for ultrashallow source/drain extensions and short-channel effect (SCE) could be suppressed by
using this approach25-27. However, the reported works showed severe decrease of current
level resulting from structural weakness. The structural weakness includes the thick
side-gate oxide, long side-gate length and gate-to-gate capacitance. A device structure
with a thin side-gate oxide is required in order to induce the inversion layer at a low
voltage 24.
Rather than having only one well in a CMOS, twin well and field oxide (FOX)
technology has been introduced. Field oxide is simply a relatively thick oxide separating
NMOS and PMOS. An extension from this project can be made using this type of
MOSFET and by adding biaxial strained silicon; biaxial strained Silicon twin well with
FOX technology can be created.
82
83
REFERENCE
84
9. Oberhuber R, Zandler G, Vogl P. Subband structure and mobility of two
dimensional holes in strained Si/SiGe MOSFETs. Physical Review B. 1998.
58(15):99419948.
10. Eunice Goh. Design and Characterization of Strained Silicon MOSFET.
Thesis Bachelor of Electrical Engineering. Universiti Teknologi Malaysia.
2007
11. Wong Y.J., Ismail Saad, Razali Ismail. Characterization of Strained Silicon
MOSFET Using Semiconductor TCAD Tools. 2006. Kuala Lumpur:
ICSE2006 Proc.
12. Lau Ngei Ong, Design and Characterization of Biaxial Strained Silicon NChannel MOSFET. Thesis Bachelor of Electrical Engineering. Universiti
Teknologi Malaysia. 2010.
13. K. Rim et al. Strained Si CMOS (SS CMOS) technology: opportunities and
challenges. Solid-State Electronics. 2003. 47. 11331139
14. Y.Sun et al. Physics of process induced uniaxially strained Si. Materials
Science and Engineering. 2006. B(135). 179183.
15. Scott E. Thompson et al. Uniaxial Process Induced Strained Si: Extending the
CMOS roadmap. IEEE Transactions On Electron Devices.2006. 53(5).
16. Scott E. Thompson, Mark Armstrong, et al. A Logic Nanotechnology
Featuring Strained Silicon. IEEE Electron Device Letters. 2004. 25(4): 191193.
17. David J. Walkey. MOSFET Operations, notes given in Physical Electronics
(Lecture 21). 2008.
18. Silvaco International, Interactive Tools: ATHENA: Process Simulation
Framework, Trade Brochure
19. Silvaco International, Interactive Tools: DeckBuild. Trade Brochure.
20. Silvaco International, TCAD Workshop Using Silvaco TCAD Tools. Manual.
21. Shaobo men. Simulation of 0.35um CMOS Process and Device Use
SILVACO TCAD TOOLS. 2008.
22. Reiche. M. et al. Strained Silicon Devices. Solid State Phenomena. 2010.
156-158.
85
23. Baker. R.J. CMOS Circuit Design, Layout, and Simulation. USA: John
Wiley & Sons Inc. 2005.
24. H. Wakabayashi, et al. 45-nm gate length CMOS technology and beyond
using steep halo. IEDM Technical Digest. 2000. 4952.
25. H. S. Wong. Gate current injection and surface impact ionization in
MOSFETs with a gate induced virtual drain. IEDM Technical Digest. 1992.
151154.
26. H. Noda et al. Threshold voltage controlled 0.1um MOSFET utilizing
inversion layer as extremely shallow source/drain. IEDM Technical Digest.
1993. 123126.
27. H. Kawaura, T. Sakamoto, et al. Transistor characteristics of 14-nm-gatelength EJ-MOSFETs. IEEETrans. Electron Devices. 2000. 47. 856860.
28. Silvaco International, Interactive Tools: ATLAS: Device Simulation
Framework. Trade Brochure.
86
APPENDIX A
ATHENA INPUT FILE: 45nm BIAXIAL STAINED SILICON NMOS
go Athena
# Establishing Initial Non-Uniform Grid
line x loc=0.00 spac=0.075
line x loc=0.30 spac=0.025
line x loc=0.40 spac=0.025
line x loc=0.50 spac=0.050
#
line y loc=-2.5 spac=0.008
line y loc=-2.4 spac=0.006
line y loc=-2.2 spac=0.005
# Initialize Substrate Material
init silicon c.boron=2.0e18 orientation=100 two.d
# Depositing epitaxial layer
epitaxy time=25 temp=800 thickness=0.02 c.boron=4.0e16
# Deposit Si & SiGe layer
deposit silicon thick=0.02 c.boron=1.0e16 divisions=10
deposit sige thick=0.015 c.boron=1.0e16 divisions=5
c.fraction=0.35
deposit silicon thick=0.009 c.boron=1.0e16 divisions=4
# Gate Oxidation
diffus time=7 temp=900 dryo2 press=1.00 hcl.pc=3
#Extract Gate Oxide
extract name="GateOxide" thickness material="SiO~2"
mat.occno=1 x.val=0.3 datafile="gateOxide.final"
# Vth Adjust Implant
implant boron dose=1.0e10 energy=30 tilt=0 rotation=0
crystal
# Deposit Poly of Gate
deposit polysilicon thick=0.2 divisions=8
# Etch Poly
etch polysilicon left p1.x=0.408093
87
# Poly Oxidation
method fermi
diffus time=3 temp=900 weto2 press=1.00
# Poly Doping
implant phosphor dose=5.0e14 energy=13 tilt=0 rotation=0
crystal
# Deposit Spacer oxide
deposit oxide thick=0.12 divisions=10
# Etch Spacer Oxide
etch oxide thick=0.12
# Source/Drain Implant
implant phosphor dose=1.0e16 energy=20 tilt=0 rotation=0
crystal
# Source/Drain Annealing
method fermi
diffus time=1 temp=900 nitro press=1.00
# Open Contact Window
etch oxide left p1.x=0.21
# Aluminium Deposition
deposit aluminum thick=0.03 divisions=2
# Etch Aluminium
etch aluminum right p1.x=0.18
#Mirror structure
struct mirror right
#Name structure
electrode name=source left
electrode name=gate x=0.5
electrode name=drain right
electrode name=backside backside
struct outfile=ssin.str
tonyplot ssin.str
quit
88
APPENDIX B
ATLAS INPUT FILE: DIBL CHARACTERISTICS OF BIAXIAL STRAINED
SILICON NMOS
go atlas
#
mesh infile=ssin.str
# material parameter, model, method and output specific
material material=Si taun0=1e-7 taup0=1e-7
material material=SiGe taun0=1.0e-8 taup0=1.0e-8
model bgn consrh auger fldmob conmob print
contact name=gate n.polysilicon
interface qf=3e10
#use newton method
method newton
# save the structure with band diagram and plot it
output con.band val.band
save outf=test.str
#tonyplot test.str
#Bias the drain with small voltage
solve vdrain=0.025 vstep=0.025 vfinal=0.3 name=drain
#Ramp the gate
log outf=dibl_1.log master
solve vgate=0 vstep=0.1 vdrain=0.3 vfinal=1.5 name=gate
# extract device parameters
extract init inf="dibl_1.log"
extract name="pvt_1"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
log off
# Start again, ramp the drain to 3 volts
solve init
89
# Bias the drain to 3 volts, 2 times, with small voltage
first
solve vdrain=0.025 vstep=0.025 vfinal=0.3 name=drain
solve vdrain=0.25 vstep=0.25 vfinal=3.5 name=drain
# Ramp the gate again with another opened logfile...
log outf=dibl_2.log master
solve vgate=0 vstep=0.1 vdrain=3.5 vfinal=1.5 name=gate
# extract the next device parameter with the drain now at 3
volts....
extract init inf="dibl_2.log"
extract name="pvt_2"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
# Calculate a DIBL parameter....in V/V
extract name="ndibl" ($"pvt_1"-$"pvt_2")/(3.0-0.1)
tonyplot -overlay
quit
dibl_1.log dibl_2.log
90
APPENDIX C
ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS OF BIAXIAL STRAINED
SILICON NMOS
go atlas
#
mesh infile=ssin.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=1
log outf=ssin1.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
#value extraction
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
91
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssin1.log
log off
solve vdrain=0.1
log outf=ssin0_1.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssin0_1.log
log off
solve vdrain=0.4
log outf=ssin0_4.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssin0_4.log
log off
solve vdrain=0.5
log outf=ssin0_5.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
92
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssin0_5.log
log off
solve vdrain=0.7
log outf=ssin0_7.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssin0_7.log
quit
93
APPENDIX D
ATLAS INPUT FILE: Id-Vds CHARACTERISTICS OF BIAXIAL STRAINED
SILICON NMOS
go atlas
#
mesh infile=ssin.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=1
log outf=ssin1.log
solve vgate=1.1 outf=solve1
solve vgate=2.2 outf=solve2
solve vgate=3.3 outf=solve3
#
load infile=solve1
log outf=ssin1_1.log
94
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
#
load infile=solve2
log outf=ssin1_2.log
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
#
load infile=solve3
log outf=ssin1_3.log
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
tonyplot -overlay ssin1_1.log ssin1_2.log ssin1_3.log
quit
95
APPENDIX E
ATHENA INPUT FILE: 45nm CONVENTIONAL NMOS
go athena
# Establishing Initial Non-Uniform Grid
line x loc=0.00 spac=0.075
line x loc=0.30 spac=0.025
line x loc=0.40 spac=0.025
line x loc=0.50 spac=0.050
#
line y loc=-2.5 spac=0.008
line y loc=-2.4 spac=0.006
line y loc=-2.2 spac=0.005
# Initialize Substrate Material
init silicon c.boron=2.0e18 orientation=100 two.d
# Gate Oxidation
diffus time=7 temp=900 dryo2 press=1.00 hcl.pc=3
#Extract Gate Oxide
extract name="GateOxide" thickness material="SiO~2"
mat.occno=1 x.val=0.3 datafile="gateOxide.final"
# Vth Adjust Implant
implant boron dose=1.0e10 energy=30 tilt=0 rotation=0
crystal
# Deposit Poly of Gate
deposit polysilicon thick=0.2 divisions=8
# Etch Poly
etch polysilicon left p1.x=0.428
# Poly Oxidation
method fermi
diffus time=3 temp=900 weto2 press=1.00
# Poly Doping
implant phosphor dose=7.5e14 energy=15 tilt=0 rotation=0
crystal
96
97
APPENDIX F
ATLAS INPUT FILE: DIBL CHARACTERISTICS OF CONVENTIONAL
NMOS
go atlas
#
mesh infile=convn.str
# material parameter, model, method and output specific
material material=Si taun0=1e-7 taup0=1e-7
material material=SiGe taun0=1.0e-8 taup0=1.0e-8
model bgn consrh auger fldmob conmob print
contact name=gate n.polysilicon
interface qf=3e10
#use newton method
method newton
# save the structure with band diagram and plot it
output con.band val.band
save outf=test.str
#tonyplot test.str
# Bias the drain with small voltage
solve vdrain=0.025 vstep=0.025 vfinal=0.3 name=drain
#Ramp the gate
log outf=dibl_1.log master
solve vgate=0 vstep=0.1 vdrain=0.3 vfinal=1.5 name=gate
# extract device parameters
extract init inf="dibl_1.log"
extract name="pvt_1"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
log off
# Start again, ramp the drain to 3 volts
98
solve init
# Bias the drain to 3 volts, 2 times, with small voltage
first
solve vdrain=0.025 vstep=0.025 vfinal=0.3 name=drain
solve vdrain=0.25 vstep=0.25 vfinal=3.5 name=drain
# Ramp the gate again with another opened logfile...
log outf=dibl_2.log master
solve vgate=0 vstep=0.1 vdrain=3.5 vfinal=1.5 name=gate
# extract the next device parameter with the drain now at 3
volts....
extract init inf="dibl_2.log"
extract name="pvt_2"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
# Calculate a DIBL parameter....in V/V
extract name="ndibl" ($"pvt_1"-$"pvt_2")/(3.0-0.1)
tonyplot -overlay
dibl_1.log dibl_2.log
99
APPENDIX G
ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS OF CONVENTIONAL
NMOS
go atlas
#
mesh infile=convn.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=1
log outf=convn1.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
#value extraction
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
100
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convn1.log
log off
solve vdrain=0.1
log outf=convn0_1.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convn0_1.log
log off
solve vdrain=0.4
log outf=convn0_4.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convn0_4.log
log off
solve vdrain=0.5
log outf=convn0_5.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
101
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convn0_5.log
log off
solve vdrain=0.7
log outf=convn0_7.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convn0_7.log
102
APPENDIX H
ATLAS INPUT FILE: Id-Vds CHARACTERISTICS OF CONVENTIONAL
NMOS
go atlas
#
mesh infile=convn.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=1
log outf=convn1.log
solve vgate=1.1 outf=solve1
solve vgate=2.2 outf=solve2
solve vgate=3.3 outf=solve3
#
load infile=solve1
log outf=convn1_1.log
103
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
#
load infile=solve2
log outf=convn1_2.log
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
#
load infile=solve3
log outf=convn1_3.log
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
tonyplot -overlay convn1_1.log convn1_2.log convn1_3.log
quit
104
APPENDIX I
ATHENA INPUT FILE: 45nm BIAXIAL STRAINED SILICON PMOS
go athena
# Establish Initial Grid
line x loc=0.00 spac=0.075
line x loc=0.30 spac=0.025
line x loc=0.40 spac=0.025
line x loc=0.50 spac=0.050
#
line y loc=-2.5 spac=0.008
line y loc=-2.4 spac=0.006
line y loc=-2.2 spac=0.005
# Initialize Substrate Material
init silicon c.arsenic=2.0e17 orientation=100 two.d
# Epitaxy
epitaxy time=25 temp=800 thickness=0.02 c.phos=4.0e16
# Deposit Si & SiGe layer
deposit silicon thick=0.02 c.arsenic=1.0e16 divisions=10
deposit sige thick=0.015 c.arsenic=1.0e16 divisions=5
c.fraction=0.35
deposit silicon thick=0.009 c.arsenic=1.0e16 divisions=4
# Gate Oxidation
diffus time=7 temp=900 dryo2 press=1.00 hcl.pc=3
#Extract Gate Oxide
extract name="GateOxide" thickness material="SiO~2"
mat.occno=1 x.val=0.3 \
datafile="gateOxide.final"
# Vth Adjust Implant
implant arsenic dose=1.0e10 energy=30 tilt=0 rotation=0
crystal
# Deposit Poly of Gate
deposit polysilicon thick=0.2 divisions=8
# Etch Poly
105
etch polysilicon left p1.x=0.408093
# Poly Oxidation
method fermi
diffus time=3 temp=900 weto2 press=1.00
# Poly Doping
implant boron dose=25.0e13 energy=5 tilt=0 rotation=0
crystal
# Deposit Spacer oxide
deposit oxide thick=0.12 divisions=10
# Etch Spacer Oxide
etch oxide thick=0.12
# Source/Drain Implant
implant boron dose=1.0e13 energy=9 tilt=0 rotation=0
crystal
# Source/Drain Annealing
method fermi
diffus time=1 temp=900 nitro press=1.00
# Open Contact Window
etch oxide left p1.x=0.21
# Aluminium Deposition
deposit aluminum thick=0.03 divisions=2
# Etch Aluminium
etch aluminum right p1.x=0.18
#Mirror structure
struct mirror right
#Name structure
electrode name=source left
electrode name=gate x=0.5
electrode name=drain right
electrode name=backside backside
struct outfile=ssip.str
tonyplot ssip.str
106
APPENDIX J
ATLAS INPUT FILE: DIBL CHARACTERISTICS OF BIAXIAL STRAINED
SILICON PMOS
go atlas
#
mesh infile=ssip.str
# material parameter, model, method and output specific
material material=Si taun0=1e-7 taup0=1e-7
material material=SiGe taun0=1.0e-8 taup0=1.0e-8
model bgn consrh auger fldmob conmob print
contact name=gate n.polysilicon
interface qf=3e10
#use newton method
method newton
# save the structure with band diagram and plot it
output con.band val.band
save outf=test.str
#tonyplot test.str
# Bias the drain with small voltage
solve vdrain=-0.025 vstep=-0.025 vfinal=-0.3 name=drain
#Ramp the gate
log outf=dibl_1.log master
solve vgate=0 vstep=-0.1 vdrain=-0.3 vfinal=-1.5 name=gate
# extract device parameters
extract init inf="dibl_1.log"
extract name="pvt_1"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
log off
# Start again, ramp the drain to 3 volts
solve init
107
# Bias the drain to 3 volts, 2 times, with small voltage
first
solve vdrain=-0.025 vstep=-0.025 vfinal=-0.3 name=drain
solve vdrain=-0.25 vstep=-0.25 vfinal=-3.5 name=drain
# Ramp the gate again with another opened logfile...
log outf=dibl_2.log master
solve vgate=0 vstep=-0.1 vdrain=-3.5 vfinal=-1.5 name=gate
# extract the next device parameter with the drain now at 3
volts....
extract init inf="dibl_2.log"
extract name="pvt_2"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
# Calculate a DIBL parameter....in V/V
extract name="pdibl" ($"pvt_1"-$"pvt_2")/(3.0-0.1)
tonyplot -overlay
dibl_1.log dibl_2.log
108
APPENDIX K
ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS OF BIAXIAL STRAINED
SILICON PMOS
go atlas
#
mesh infile=ssip.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=-1
log outf=ssip1.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
#value extraction
109
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssip1.log
log off
solve vdrain=-0.1
log outf=ssip0_1.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssip0_1.log
log off
solve vdrain=-0.4
log outf=ssip0_4.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssip0_4.log
log off
solve vdrain=-0.5
log outf=ssip0_5.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
110
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssip0_5.log
log off
solve vdrain=-0.7
log outf=ssip0_7.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssip0_7.log
111
APPENDIX L
ATLAS INPUT FILE: Id-Vds CHARACTERISTICS OF BIAXIAL STRAINED
SILICON PMOS
go atlas
#
mesh infile=ssip.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=-1
log outf=ssip1.log
solve vgate=-1.1 outf=solve1
solve vgate=-2.2 outf=solve2
solve vgate=-3.3 outf=solve3
#
load infile=solve1
log outf=ssip1_1.log
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3
112
#
load infile=solve2
log outf=ssip1_2.log
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3
#
load infile=solve3
log outf=ssip1_3.log
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3
tonyplot -overlay ssip1_1.log ssip1_2.log ssip1_3.log
quit
113
APPENDIX M
ATHENA INPUT FILE: 45nm CONVENTIONAL PMOS
go athena
# Establish Initial Grid
line x loc=0.00 spac=0.075
line x loc=0.30 spac=0.025
line x loc=0.40 spac=0.025
line x loc=0.50 spac=0.050
#
line y loc=-2.5 spac=0.008
line y loc=-2.4 spac=0.006
line y loc=-2.2 spac=0.005
# Initialize Substrate Material
init silicon c.arsenic=2.0e17 orientation=100 two.d
# Gate Oxidation
diffus time=7 temp=900 dryo2 press=1.00 hcl.pc=3
#Extract Gate Oxide
extract name="GateOxide" thickness material="SiO~2"
mat.occno=1 x.val=0.3 \
datafile="gateOxide.final"
# Vth Adjust Implant
implant arsenic dose=1.0e10 energy=30 tilt=0 rotation=0
crystal
# Deposit Poly of Gate
deposit polysilicon thick=0.2 divisions=8
# Etch Poly
etch polysilicon left p1.x=0.424
# Poly Oxidation
method fermi
diffus time=3 temp=900 weto2 press=1.00
# Poly Doping
implant boron dose=15.0e13 energy=5 tilt=0 rotation=0
crystal
114
115
APPENDIX N
ATLAS INPUT FILE: DIBL CHARACTERISTICS OF CONVENTIONAL PMOS
go atlas
#
mesh infile=convp.str
# material parameter, model, method and output specific
material material=Si taun0=1e-7 taup0=1e-7
material material=SiGe taun0=1.0e-8 taup0=1.0e-8
model bgn consrh auger fldmob conmob print
contact name=gate n.polysilicon
interface qf=3e10
#use newton method
method newton
# save the structure with band diagram and plot it
output con.band val.band
save outf=test.str
#tonyplot test.str
# Bias the drain with small voltage
solve vdrain=-0.025 vstep=-0.025 vfinal=-0.3 name=drain
#Ramp the gate
log outf=dibl_1.log master
solve vgate=0 vstep=-0.1 vdrain=-0.3 vfinal=-1.5 name=gate
# extract device parameters
extract init inf="dibl_1.log"
extract name="pvt_1"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
log off
# Start again, ramp the drain to 3 volts
solve init
# Bias the drain to 3 volts......slowly at first....
116
solve vdrain=-0.025 vstep=-0.025 vfinal=-0.3 name=drain
solve vdrain=-0.25 vstep=-0.25 vfinal=-3.5 name=drain
# Ramp the gate again with another opened logfile...
log outf=dibl_2.log master
solve vgate=0 vstep=-0.1 vdrain=-3.5 vfinal=-1.5 name=gate
# extract the next device parameter with the drain now at 3
volts....
extract init inf="dibl_2.log"
extract name="pvt_2"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
# Calculate a DIBL parameter....in V/V
extract name="pdibl" ($"pvt_1"-$"pvt_2")/(3.0-0.1)
tonyplot -overlay
dibl_1.log dibl_2.log
117
APPENDIX O
ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS OF CONVENTIONAL
PMOS
go atlas
#
mesh infile=convp.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=-1
log outf=convp1.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
#value extraction
118
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convp1.log
log off
solve vdrain=-0.1
log outf=convp0_1.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convp0_1.log
log off
solve vdrain=-0.4
log outf=convp0_4.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convp0_4.log
log off
solve vdrain=-0.5
log outf=convp0_5.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
119
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convp0_5.log
log off
solve vdrain=-0.7
log outf=convp0_7.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convp0_7.log
120
APPENDIX P
ATLAS INPUT FILE: Id-Vds CHARACTERISTICS OF CONVENTIONAL
PMOS
go atlas
#
mesh infile=convp.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=-1
log outf=convp1.log
solve vgate=-1.1 outf=solve1
solve vgate=-2.2 outf=solve2
solve vgate=-3.3 outf=solve3
#
load infile=solve1
log outf=convp1_1.log
121
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3
#
load infile=solve2
log outf=convp1_2.log
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3
#
load infile=solve3
log outf=convp1_3.log
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3
tonyplot -overlay convp1_1.log convp1_2.log convp1_3.log
quit