EEL782 PROJECT WORK (2014-16 BATCH) IIT DELHI

Multi-Stage Operational Amplifier with Frequency

Compensation and High CMRR
Shubham Gupta (2014EEN2400) Hassen Basha (2014EEN2790)
KV Kalyan Kumar (2014JVL2703)
Abstract
The Project aims to design an Low Power High Speed Operational Amplifier with frequency Compensation. This Operational Amplifier
circuit is implemented using 120nm CMOS Process Technology and the simulation results such as Open Loop Gain, Operating Points,
unity gain Frequency, Phase Margin, ICMR (Input Common Mode Range), OCMR have been computed and results are tabulated.
KeywordsFrequency Compensation,Low Voltage OP-Amp, High CMRR, Phase Margin

Introduction

he project is intended to design a Low Power High

Speed Multi Stage Operational Amplifier with CMRR
90-110 dB. We started with 5 Transistor OTA (fig.1)
(Operational Transcoductance Amplifier) as a first stage
of our Operational Amplifier and achieved differntial gain
of 40 dB and Common-Mode gain of -4 dB. So, we moved
on to Multi Stage Amplifier with cascaded CS (Common
Source) Stage as a 2nd stage of our Operational Amplifier
and hence we obtained differntial gain of 57 dB and
Common-Mode gain of +4 dB. Hence CMRR is increased
by using two stage OP-Amp but for achieving a high
CMRR we need to have another cascade stage. But as we
are increasing the number of stages, the High Impedence
Nodes will be increased and these nodes will introduce
dominant poles. To have good phase margin we have to
properly frequency compensate our circuit as shown in fig.1
We have done literature Survey by referring IEEE papers, Text Books and Online Material as mentioned in the
Referrences.

2.2

Circuit Diagram

[4]

Fig. 1 Two Stage Frequency Compensated Operational

Amplifier
2.3

Size Calculation

[3]

Cc (CompensatingCapacitor) 0.22CL

2
2.1

OP-Amp Circuit
Cc 220f F
Cc = 250f F

Design Specification
Table 1
Parameter
Targeted
DC Gain
95 dB
CMRR
100 dB
Gain-BW Product 100 MHz
Phase Margin
60 deg
Slew Rate
20 V/ us
Load Capacitance
1pF
Supply Voltage
1.2 V
ICMR(min.)
0.3 V
ICMR(max.)
1V
Power
300 uW

Current through N M 3 = SR Cc
current = 20uA
2

n Cox = 500uA/V (Calculated f rom N M OS Simulation)

p Cox = 95uA/V 2 (Calculated f rom P M OS Simulation)

EEL782 PROJECT WORK (2014-16 BATCH) IIT DELHI

Tabel 2 : Transistor Sizes

W(um) L(nm)
NM0
87
600
NM1
3
300
NM2
3
300
NM3
4.8
600
NM5
4.8
600
PM0
1.2
300
PM1
1.2
300
PM2
87
600

Size of NM1,NM2 :
gm1 = GBW Cc 2
W
gm1 2
=
L N M 1,2
n Cox 2Idn1
W
= 10
L N M 1,2
Size of PM1,PM2 :
2Idp1
W
=
L P M 1,2
p Cox (VDD ICM R+ Vtp1,max + Vtn1,min )2
Vtp1,min = 274.69mV, Vtn1,min = 319.1mV
Vtp1,max = 274.69mV, Vtn1,max = 366.6mV

2.4 Simulated Results

DC Analysis
We completed DC Analysis to ensure that Transistors are
operating in Region = 2 (Saturation Region) only for the
applied Common Mode Signal.

W
=4
L P M 1,2
Size of NM3,NM5 :
2Idn3
W
=
L N M 3,5
n Cox (VD,sat )2
s
2Idn1
VD,sat = ICM R
Vtn1,max
1
W
=8
L N M 3,5
Size of PM2 :
F or 60o P hase M argin : gm6 10gm1

Fig. 2 DC Operating Points of each Transistor

AC Analysis
Gain and Phase Plots

gm6 3141 uA/V 2

W
L P M2
W
L P M1

Id,p2
gm,p2
=
Id,p1
gm,p1

W
= 145
L P M2
Size of NM0 :
W
L NM0
W
L NM3

Id,n0
Id,n3

W
= 145
L NM0

Fig. 3 Phase and Gain Margin Plot

EEL782 PROJECT WORK (2014-16 BATCH) IIT DELHI

Table 3: Summary of Simulation Result (CL = 1pF )

Parameter
DC Gain
CMRR
Gain-BW Product
Phase Margin
Supply Voltage
ICMR(min.)
ICMR(max.)

Targeted
95 dB
100 dB
100 MHz
60 deg
1.2 V
0.3 V
1V

Achieved
57 dB
53 dB
76.7883 MHz
56.33 deg
1.2 V
0.45 V
0.95 V

3 Modified OP-Amp Circuit with High

CMRR and Bandwidth
3.1

Circuit Diagram

[4]

3.3 Final Simulation Results

3.3.1 Simulation Results with Fix Parameters
Parameter Values:
Tabel 5 : Parameter Values
Value
CL
1 pF
Cc
250 fF
Idc
40 A
Rz
400
Vcm
800 mV
Temp.
300 K
Differential Gain Plot:

Fig. 5 Differential Gain and Phase Margin Plot

Common-Mode Gain Plot:
Fig. 4 Two Stage Frequency Compensated Operational
Amplifier with CMFB
3.2

Modified Design

Transistor sizes have been modified as we have added

CMFB circuit and cascoded Tail current source for the
purpose of decreasing Common-mode Gain and increase
in Bandwidth respectively.
Tabel 4 : Transistor Aspect Ratios and Functions

NM0
NM1,NM2
NM3
NM4
NM6
PM0,PM1
PM2
PM3
PM4
Rz
Cc

W(um)/L(nm)
175/600
3/300
100/9.6um
140/9.6um
8/300
1.2/300
81.6/600
2.6/300
600nm/300
400
250fF

Function
2 Stage load
Diff. pair
tail current source
biased tail current source
Tail Isink for CMFB
diff. load
2nd Stage driver
CMFB driver
voltage ref. source
Nulling resistor
Miller Compens. Cap.

Fig. 6 Common-Mode Gain and Phase Margin Plot

Slew Rate Plot:

nd

Fig. 7 Slew Rate Plot

EEL782 PROJECT WORK (2014-16 BATCH) IIT DELHI

Input Noise Analysis Plot:

Input Common-mode Range Plot:

Fig. 11 ICMR Plot

Fig. 8 Input Noise Analysis Plot

Output Noise Analysis Plot:

Slew Rate Measurement : We have connected the

OP-Amp in unit gain feedback configuration and applied
the unit Step signal at the Positive terminal, the slope at
the O/P will give us the Slew Rate.
Improved Common Mode Gain : To decrease the
common mode gain we have used the Common Mode
Feedback (CMFB) circuit which is controlling the bias
voltage of the Tail Current Source.
Noise Analysis : We have performed the Noise analysis
of Input Transistor NM1 and Output Transistor PM2
and we plotted PSD of both Input and Output Noise as
shown in Fig. 8 and 9.
Input Thermal Noise PSD: 2.51 pV 2 /Hz
Output Thermal Noise PSD: 40.29 pV 2 /Hz
Tabel 6 : Summary Of Simulation Results

Fig. 9 Output Noise Analysis Plot

Transient Analysis Plot:

Fig. 10 Transient Analysis Plot

Parameter
Common-Mode Gain
Differential Gain
CMRR
3dB BW
Gain-BW Product
Phase Margin
Supply Voltage
Slew Rate
Power
ICMR(min.)
ICMR(max.)
Input Offset
Output Offset

Targeted
0 dB
95 dB
100 dB
100 kHz
100 MHz
60 deg
1.2 V
20 V/s
700 W
0.3 V
1V
0V
0V

Achieved
-53.0955 dB
46.1517 dB
99.2472 dB
295.92 kHz
100.968 MHz
59.5813 deg
1.2 V
21.4367 V/s
657.6 W
0.791 V
0.977 V
681.12 nV
18 V

EEL782 PROJECT WORK (2014-16 BATCH) IIT DELHI

3.3.2 Parametric Analysis

Bias Current variation (28 A to 40 A)
Power vs I Plot:

INFERENCE :
As bias current is increasing, we observed that
Differential
gain is decreasing as gain is inversely
propotional to 2 Id so
Common mode gain degrades as decrease in impedance
of the tail current source (RSS ) is dominated over increase
in gm .
Phase margin remained constant as it depends on miller
compensation capacitor and doesnt depends on bias
current.
CL variation (250fF to 5pF)
Differential Gain variation :

Fig. 12 Power Dissipation variation w.r.t bias Current

Differential Gain variation :

Fig. 16 Differential Gain variation w.r.t CL

Fig. 13 Differential Gain variation w.r.t bias current

Common-mode Gain variation:

Common-mode Gain variation:

Fig. 17 Common-mode Gain variation w.r.t CL

Fig. 14 Common-mode Gain variation w.r.t bias current

3dB BW,Phase Margin and Unity-Gain BW

variation:

3dB BW,Phase Margin and Unity-Gain BW

variation:

Fig. 18 3dB BW,Phase Margin and Unity-Gain BW

variation w.r.t CL
Fig. 15 3dB BW,Phase Margin and Unity-Gain BW
variation w.r.t bias current

EEL782 PROJECT WORK (2014-16 BATCH) IIT DELHI

INFERENCE :

INFERENCE :

As CL is increasing, we observed that

Adm and Acm is constant as they depends upon the

aspect ratios of the transistors and biasing current.
Because of the cascaded stage(CS amp) we are getting
two dominant poles. These poles are affecting the phase
margin and unity gain bandwidth product.To maintain the
system stability(PM 60 ) second pole must be alteast 2.2
times the unity gain frequency. But from the above plots
as the Cc increasing greater than 0.22CL (CL maintained
constant at 1pF) and hence phase margin increases.
But increasing the miller capacitor beyond the certain
limit(0.22CL ) will lead to decrease in the bandwidth due
to increase in both input as well as output node time
constant.

Adm and Acm is constant as they depends upon the

aspect ratios of the transistors and biasing current.
Unity gain BW is reducing due to the increase in the
Time constant i.e. increase in the time taken by the Load
capacitor to charge
Because of the cascaded stage(CS amp.) we are getting
two dominant poles. These poles are affecting the phase
margin and unity gain bandwidth product.To maintain
the system stability(PM 60 deg) second pole must be
alteast 2.2 times fugbw . But from the above plots as
the CL increasing we are not able to maintain Cc =0.22
CL (Cc maintained constant at 250fF) and hence phase
margin is decreasing.
Cc variation (210fF to 1pF)

Rz variation (0 to 1k)
Differential Gain variation :

Differential Gain variation :

Fig. 22 Differential Gain variation w.r.t Rz

Fig. 19 Differential Gain variation w.r.t Cc
Common-mode Gain variation:

Fig. 20 Common-mode Gain variation w.r.t Cc

3dB BW,Phase Margin and Unity-Gain BW
variation:

Fig. 21 3dB BW,Phase Margin and Unity-Gain BW

variation w.r.t Cc

Common-mode Gain variation:

Fig. 23 Common-mode Gain variation w.r.t Rz

3dB BW,Phase Margin and Unity-Gain BW
variation:

Fig. 24 3dB BW,Phase Margin and Unity-Gain BW

variation w.r.t Rz

EEL782 PROJECT WORK (2014-16 BATCH) IIT DELHI

INFERENCE :

INFERENCE:

Adm and Acm is constant as they depends upon the

aspect ratios of the transistors and biasing current.
As due to two stage amplifier we are getting the Right
half plane zero,which reduces the phase margin there by
reduces the system stability.So as to maintain the system stability(PM=60 deg) we should maintain minimum
Rz =1/gm2 (second stage transconductor) to cancel out the
right half plane zero.
It is observed that nulling resistor doesnt affect the
bandwidth much.

As the temperature increases the mobility of carriers in

the channel decreases there by reducing the drain current
in the channel. Hence the differential gain reduces due to
decrease in gm
Device Length variation (150nm to 600nm)
Differential Gain variation :

Temperature variation (0 to 100)

Differential Gain variation :

Fig. 28 Differential Gain variation w.r.t Device length

3dB BW,Phase Margin and Unity-Gain BW
variation:

Fig. 25 Differential Gain variation w.r.t Temperature

Common-mode Gain variation:

Fig. 29 3dB BW,Phase Margin and Unity-Gain BW

variation w.r.t Device length
* Multiplier is the Transistor length multiplication factor
INFERENCE :
Fig. 26 Common-mode Gain variation w.r.t Temperature
3dB BW,Phase Margin and Unity-Gain BW
variation:

Fig. 27 3dB BW,Phase Margin and Unity-Gain BW

variation w.r.t Temperature

As the length of device increase the time taken for

the carrier to reach from source to drain increases(gm
decreases). Hence the differential gain decreases.

EEL782 PROJECT WORK (2014-16 BATCH) IIT DELHI

Device Width variation (1.5m to 6m)

Differential Gain variation :

Table 8: Primary design trade offs for

Frequency Compensated OP-Amp
Parameters to
Improve
Differential Gain
Gain-BW Product
Phase Margin

Method to
Improve
L,W/L const
gm ,L and Ids const
Cc
Cc
Cc
Rz
CL

Trade Offs
degraded
Vdsat
Noise
UGB
UGB
3dB BW
Driven Capability

Fig. 30 Differential Gain variation w.r.t device width

3dB BW,Phase Margin and Unity-Gain BW
variation:

REFERENCES

[1] Ehsan Kargaran, Sadjad Institute for Higher

Education,"A 1.5 V High Swing Ultra-Low-Power
Two Stage CMOS OP-Amp in 0.18 um Technology" in
ICMEE 2010.
[2] Jae-Seung Lee,Jun Hyun Bae, Pohang University,"A
Design Guide of 3-stage CMOS Operational Amplifier
with Nested Gm-C Frequency Compensation" in Journal
of Semiconductor Technology and Science.

Fig. 31 3dB BW,Phase Margin and Unity-Gain BW

variation w.r.t device width

[4] Behzad Razavi,"Design of Analog CMOS Integrated

Circuits" Textbook

INFERENCE :
As the width of differential pair transistors increases,
gain and Bandwidth increased but it leads to decrease in
the system stability as the Phase margin is reduced.

CONCLUSION
Table 7: Summary
Acm
Adm
3dB BW
GBW
PM

[3] Philip E. Allen and Douglas R. Holberg,"CMOS

Analog Circuit Design" Textbook

I
decr
decr
incr
incr
incr

Cc
const
const
decr
decr
incr

CL
const
const
decr
decr
decr

Rz
const
const
decr
incr
incr

T emp.
decr
decr
incr
decr
decr

[5] Michael Angelo G. Lorenzo, University of Philippines,"Design and Implementation of CMOS Rail-to-Rail
Operational Amplifiers" in ISCIT 2007