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EXECUTE FETCH
EXECUTE FETCH
EXECUTE
time
FETCH
EXECUTE
BIU
FETCH
FETCH
EU
WAIT
EXECUTE
FETCH
FETCH
EXECUTE
time
EXECUTE
Instruction
Pipeline
EXECUTION
UNIT
EU
BUS
INTERFACE
UNIT BIU
Address Bus
Data Bus
Instr. Decode;
Bus Controller
EU
AH
AL
BH
BL
CH
CL
DH
DL
BP
DI
SI
SP
ADD
CS
ES
SS
DS
IP
ALU/EXECUT
FLAGS
BIU
3
4
5
6
Instruction
Queue
BIU - contents
Bloc for controlling the signals
FIFO memory to implement the 6 byte
s queue
Instruction pointer (next instruction to
be executed)
ALU to calculate the address
Internal communication registers
Registers for memory segmentation
EU Execution Unit
Decoding of instructions
ALU
General registers (accessible by user)
Internal registers (internal operations)
Register to store the status and contr
ol of the program
AL
BL
CL
DL
AH
BH
CH
DH
Accumulator
Base
Counter
Data
15
Code Segment
Data Segment
Stack Segment
Extra Segment
Destination Index
AX
BX
CX
DX
0
CS
DS
SS
ES
15
Instruction Pointer
Stack Pointer
Base Pointer
Source Index
IP
SP
BP
SI
DI
}
}
Automatically Incremented
Programmer can Control with jump and branch
Accumulator
Base
Counter
Data
AH
BH
CH
DH
AL
BL
CL
DL
Accumulator
Base
Counter
Data
AH
BH
CH
DH
AL
BL
CL
DL
AX, Accumulator
Main Register for Performing Arithmetic
mult/div must use AH, AL
accumulator Means Register with Simple ALU
BX, Base
Point to Translation Table in Memory
Holds Memory Offsets; Function Calls
CX, Counter
Index Counter for Loop Control
DX, Data
After Integer Division Execution - Holds Remainder
x OF DF IF TF SF ZF x AF x PF x CF
Status Flags
Indicate Current Processor Status
CF
OF
ZF
Carry Flag
Overflow Flag
Zero Flag
SF
Sign Flag
PF
Parity Flag
Arithmetic Carry
Arithmetic Overflow
Zero Result; Equal
Compare
Negative Result; NonEqual Compare
Even Number of 1 bits
AF
Auxiliary Carry
Control Flags
Influence the 8086 During Execution Phase
DF:
Direction Flag
Increment/Decrement
Enables Interrupts
TF Trap Flag
Allows Single-Step
MOV AH,[SI]
Code Segment
Data Segment
Stack Segment
Extra Segment
CS
DS
SS
ES
15
Instruction Pointer
Stack Pointer
Base Pointer
Source Index
Destination Index
IP
SP
BP
SI
DI
}
}
Memory System
Address Lines
ES
SS
DS
19
0
Physical Address
0
Index Reg.
15
Segment Reg.
BP
0
0000
DI
SI
SP
IP
Segmented Addressing
memory
CS
ES
SS
00000h
paragraph 1
DS
00010h
paragraph 2
00020h
paragraph 3
BP
DI
SI
SP
IP
Segment Registers:
Point to Base Address
Index Registers:
Contain Offset Value
fragmentation
Notation (Segmented Address):
Code
Segment
Segment
Registers
CS
Extra
Segment
ES
SS
DS
Stack
Segment
Data
Segment
00000h
System
Memory
CS:IP
DS:SI
ES:DI
SS:BP
SS:SP
Code
Segment
Segment
Registers
CS
Extra
Segment
ES
SS
DS
Stack
Segment
Data
Segment
00000h
System
Memory
1 Word = 16 bits
Byte Addressable
Little Endian Arrangement
MSB (Most Significant Byte) at Higher Address
072CH
18H
AD5FCH
072BH
A3H
AD5FBH
072AH
7EH
AD5FAH
0729H
69H
AD5F9H
0728H
AAH
AD5F8H
0727H
2EH
AD5F7H
0726H
00H
AD5F6H
0725H
55H
AD5F5H
0724H
02H
AD5F4H
0723H
72H
AD5F3H
0722H
11H
AD5F2H
0724H
0H
0000
2H
0010
5H
0101
5H
0101
hex
binary
072CH
18H
AD5FCH
072BH
A3H
AD5FBH
072AH
7EH
AD5FAH
0729H
69H
AD5F9H
0728H
AAH
AD5F8H
0727H
2EH
AD5F7H
0726H
00H
AD5F6H
0725H
02H
AD5F5H
0724H
55H
AD5F4H
0723H
11H
AD5F3H
0722H
20H
AD5F2H
0721H
72H
AD5F1H
0720H
DEH
AD5F0H
071FH
ADH
AD5EFH
071EH
FAH
AD5EEH
071DH
CEH
AD5EDH
071CH
CAH
AD5ECH
FEH
Assume:
M[DS:DI] Contains a Pointer Value
DS = AD5Fh; DI = 0005h
(All Segments Start on Paragraph Boundary)
SI M[DS:DI]
Then:
Pointer is
M[DS:DI] = M[AD5F:0005]
= M[AD5F5] = 0002h
M[DS:SI] = M[DS:(DS:DI)] = M[DS:0002h]
= M[AD5F:0002] = M[AD5F2] = 1120h
Homework:
Give several exercises
Keypoints