Beruflich Dokumente
Kultur Dokumente
K. Choi,
2012,
kyusun@cse.psu.edu
University Park
1. Introduction
The objective of this tutorial is to give you a quick overview to (1) setup the Cadence and Synopsys hspice tools for your account in IST
218 Lab, (2) use the schematic editor, (3) use the hspice tool, (3) use the chip layout editor - Cadence Virtuoso, and (4) use DRC,
Extract, LVS tools. This guide may be updated as needed during the semester, any user comments are welcome.
2. Set up the tool environment
Before you can start using design tools, there are a few configuration files needed in your working directory. These files determine the
environment in which tools run, and what libraries are to be included in your designs. The setup given below is for LINUX machines in
Lab 218. Some UNIX/LINUX commands will be included in this tutorial. Please be familiar with basic UNIX/LINUX commands to work
efficiently.
(Anyone outside of Penn State needing the setup files and scripts we use here , may request a copy of files to me by email:
kyusun@cse.psu.edu.edu I will supply the file copies for your reference for free with the basis of non-responsibility disclaimer.)
Step1.
Login to a machine in room 218 IST Building. Bring up a terminal window where you can type a UNIX command. Then type the
following:
% /home/faculty/kyusun/c411x/bin/class411setup
This setup needs to be done only once for this semester.
Now for the setup to take effect, you logout and login again.
Step 2.
Make your own class directory(folder) for CMPEN 411 class. I made:
% mkdir cmpen411
The cmpen411 is the name of your class directory(folder). You can use any name you like. This directory will be containing all your
homework, project, exam, etc. design directories and files. ls or ls al unix command will list your directory contents and you will
see the cmpen411 subdirectory.
Directory structure:
For the grading homework, projects, and exams, one must collect all files of each design project under one directory. Student will tar
and zip the directory of their design project and turn-in for grading. Any missing files may cause the design project verification to fail.
So each design project must be stand-alone, self-contained, and independent of other projects. For example, the design project for
homework 2 may include homework 1 inverter design. In this case, the inverter design files must be physically copied into the
homework 2 directory; otherwise, the turned-in homework 2 project cannot be verified due to missing homework 1 inverter files.
Step3.
Change your current directory to cmpen411 by typing:
% cd cmpen411
Now you may create your design project directory. For a short tutorial presented in this guide, create hw0 directory. Again for the
purpose of the class homework, project, and exam, one needs to identify the project file with his/her name. Please add your last name
(upto 8 characters) to your project directory name. That way, the zipped file will contain your last name and it will be quickly indentified
and separated from other student files. For example, I will add 'choi' to my directory name, so I will type :
% mkdir hw0choi
This directory (folder) and everything in it will be zipped and turned-in for the grading in subsequent homework projects.
You need to set up your directory for the CAD tool use once the directory has been created. So type:
% cd hw0choi
% runcds
This command needs to be done only once for each design project directory. (When you do homework 2 project later, you will need to
create hw2 directory, and you would need to 'cd' to that directory, and do 'runcds' once again for that directory.)
All of my design files will be in hw0choi directory from now on. When I stop working on the hw0 tutorial project today and w ant to return
to the project to continue tomorrow, I simply type:
% cd cmpen411/hw0choi
and resume. I will not type the 'runcds' again.
Now start the Cadence tool by typing the following:
% virtuoso &
Then the CIW (Command Interpreter Window) and the library manager should pop up.
Figure: CIW Window with NOT proper starting, Library Manager does NOT pops up
If you see the Library Manager on your screen, your set up is proper. If you do NOT see the Library Manager and see the
*WARNING* message in CIW window, your set up is not proper, you can still use Cadence Virtuoso tool and do the work but you need
to see the lab-support staffs in room 111 IST Building to update your account. You need to also send email to:
helpdesk@cse.psu.edu
Step4. Optional connecting to the Lab 218 IST machines from home
You can connect to the Lab 218 IST machines from home Windows PC and do the VLSI design work at home. You will need the
following:
VPN
SSH
- http:// downloads.its.psu.edu
- http:// downloads.its.psu.edu
Plus you will need one of the following X11 clients running on your Windows PC:
Xming
Xmanager
Xwin32
Exceed from Hummingbird
cygwin ('XWin -multiwindow' command)
Once you have the above programs installed on your Windows PC, follow the steps below to connect to the Lab 218 IST machines:
1. Run VPN, set ISP to CSE (this step should be omitted if you are connecting from campus, or if you live on campus)
2. Run X11 client program (I run cygwin 'XWin Server')
3. Run ssh terminal, login to one of the following machines:
p218inst10
p218inst15
p218inst20
p218inst25
p218inst30
p218inst11
p218inst16
p218inst21
p218inst26
p218inst31
p218inst12
p218inst17
p218inst22
p218inst27
p218inst32
p218inst13
p218inst18
p218inst23
p218inst28
p218inst33
p218inst14
p218inst19
p218inst24
p218inst29
Double click on the ssh shell to start the ssh Terminal session.
Click on the Settings and be sure to check on the Tunnel X11 connection as shown below.
Once the ssh shell started, click on Quick Connect and type the followings, for example:
Host Name:
User Name:
Port Number:
Authentication Method:
p218inst10.cse.psu.edu
your_cse_user_id
22
Password
Once you are logged-in, type xclock & to see if X11 is properly working. You will see a new clock on your screen. Otherwise X11 is
not working.
Once the X11 is working, you may resize you ssh Terminal and change fonts if you like. Then be sure to Save Settings and Save
Layout, these menu options are located under the File menu tap of the ssh shell window.
3. Working with Cadence tool - virtuoso
Using the Cadence tool, the overall VLSI chip design flow can be outlined as follows:
1.
2.
3.
4.
5.
Schematic design and entry transistors, symbols, input pins, output pins vdd component, and gnd component
Schematic check check and save
Schematic spice netlist file creation
Hspice simulation of the netlist file from the schematic
Schematic symbol creation
6. Layout design and entry pmos, nmos, ptap, NTAP, input pins, output pins, vdd! pin, and gnd! pin
7. Layout DRC (Design Rule Check)
8. Extraction of circuits from the layout including parasitic elements
9. Spice netlist file creation from the layout-extracted circuit
10. Hspice simulation of the spice netlist file from the layout-extracted circuit
11. LVS (Layout Versus Schematic) checking consistency verification of the layout extracted circuit with the schematic
Following lists some tutorials, many others also exists:
http://webster.engr.pitt.edu/electrical/faculty-staff/levitan/1192/index.html
http://www.ee.virginia.edu/~mrs8n/cadence/tutorial1.html
http://www.ee.virginia.edu/~mrs8n/cadence/tutorial2.html
http://www.ee.siue.edu/~cdsadmin/tutorial.htm
You may also google to find what you want to know about the Cadence tool (or any error messages).
4. Sche matic Design
We use latest Cadence tool, however the almost all of the older Cadence schematic and layout editing tool procedures are the same.
In this section, we will create our own library and generate a schematic of inverter.
Step1.
Create a library that will hold all you designs. My case, I named 'hw0choi' as my library. You must also use your last name as part of
your library name (in addition to the project folder name). For grading, everyone in class will submit their hw1 project library, grader
needs to distinguish your library for homework 1 over another student's.
In the Library Manager window,
a) Select File -> New -> Library
b) Enter the library name 'hw0yourlastname
c) Select the option 'Attach to an existing technology library'
Figure: File menu of the Library Manager, to create a new Cell View
Figure: Select the new library and type the cell name
Then you may get another pop-up window for the Virtuoso Schematic Editor License selection. Select 'Always'.
In the schematic editor, create instance of pmos4 and nmos4 from the AnalogLib library.
On the schematic editor, select Create -> Instance or use toolbar
.
Choose library NCSU_Analog_Parts in the pop-up Component Browser window.
Choose pmos4 from the P_Transistors directory.
If the Component Browser does not appear or other error messages, click the Browse button in the Add Instance. Select the Li brary,
NCSU_Analog_Parts.
Then continue select the nmos4 transistor and place it on the schematic sheet.
Change the nmos transistor width to 2.7um. All the other parameters are left unchanged. One may note that the current inverter
design, we are using 2.7um width for nmos and 4.5um width for pmos. They are optimized for equal rise and fall time of the inverter.
Next, place the Ground (gnd symbol = 0V) and VDD (vdd symbol = 5V) to the inverter schematic. The gnd and vdd are under the
component directory of Supply_Nets . After placing the instances, press ESC to exit the placing mode.
On the schematic editor, select Create -> Instance or use toolbar
.
Choose library NCSU_Analog_Parts in the pop-up Component Browser window.
Choose vdd from the Supply_Nets directory.
Likewise, choose gnd from the Supply_Nets directory. And place the gnd on the schematic.
Next step is to add input and output pins to the inverter circuit.
Choose Create -> Pin menu or use toolbar
The completed schematic for the inverter needs to be checked and saved. Cl ick the 'check and save' button.
Be sure that there are no errors in CIW. Correct any errors. You can find further instruction from Help option in CIW. There are many
detailed tutorials in this option.
Now create a netlist file from the drawn schematic and simulate the circuit.
5. Generate netlist from the sche matic and simulate it with HSPICE
Select Launch -> ADE L, the Analog Design Environment window will pop up.
Then you may get another pop-up window for the Analog Design Environment License selection. Select 'Always'.
Next, generate the netlist from the schematic. Select Simulation -> Netlist -> Create to generate the netlist.
You may use any text editor of your choice. One I use is gedit program. You can type:
% gedit SCHinv.hsp
&
hsp50
SCHinv
It will create SCHinv.sp file. Both SCHinv.s file and SCHinv.hsp file are combined into the SCHinv.sp file.
Now hspice simulate your schematic netlist using the following command:
%
hspice
SCHinv.sp
Be sure to read the hspice output, it must say it concluded and not aborted.
Once the hspice is successfully completed, you can see the input and output waveform. Type the following command to plot the
simulation output:
%
sc
SCHinv.tr0 &
Choose the SCHinv.tr0 from the Output View window of the SpiceCheck (sc) window and expand it. Then selec t ain and zout
signals, drag them to the WaveView window. You may explore other features of the SpiceCheck program to measure the signal
parameters. Be sure that the inverter circuit is properly working.
Zoom in
Likewise one can measure gate delay time for signal zout changing from logic high to logic low. Also one can measure the signal fall
time. One can explore many other features of the SpiceCheck program.
6. Generate layout
In this section, we will draw the layout view of the inverter. A layout describes the masks from which your design will be fabricated. The
layers in a layout describe the physical characteristics of the device and have more details than a schematic. Therefore, layout
verification of your design is critical. There are two types of layout design: Full-Custom and Automated. Full-custom layout is when the
user physically draws all of the layers for the individual transistor. This is a very tedious process, but it usually enables results in a
compacter design than the automated process. The automated process, on the other hand, is done by instantiating standard cells
(reusing basic blocks) and usually takes more area but it is much faster. We only introduce custom layout design here.
You should follow MOSIS SCMOS design rule for ON Semi/AIM 0.6m:
http://www.mosis.com/Technical/Designrules/scmos/scmos-main.html
We use the scalable rule under the SCN3M_SUBM technology code. The minimum size drawn transistor length is 0.6um, the lambda
() is set to 0.3um. The inverter consists of three parts -- p-transistor, n-transistor, and connections.
6.1 Generate layout with macro in the library
Step1.
Create a layout view for the inverter.
a) Select File -> New -> Cell View
b) Choose hw0choi (for my case), select the cell name inv, and select layout view.
c) Click OK. LSW and Layout Editor windows will pop up as shown below.
From: 0 To: 20
Scroll down the scroll bar to set the pmos transistor width parameter.
Scroll down the scroll bar to set the nmos transistor width parameter.
place the ntap to the layout editor window, ntap electrically connects nwell to vdd (5V).
place the ptap to the layout editor window, ptap electrically connects pwell to gnd (0V).
If your design has violated any design rules, DRC will reports the errors in the CIW. Errors are indicated by the markers (white color)
on the layout editor window. You may then proceed to correcting the errors according to the design rules. For huge layouts, the
marker might not be easily located. To find markers, choose Verify -> Markers -> Find in layout editor window. A pop-up menu will
appear. Select on the Zoom to Markers box. Click on the Apply button and Cadence will zoom in to the errors or warnings as
desired.
Finish the inverter layout design by adding vdd, gnd, input, output, etc.
First, do the metal wiring. Select the metal1 layer in LSW window.
Do touch up on nwell.
Connect the gates of pmos and nmos transistors using poly wire material.
Next, connect the drain terminal of pmos and the drain terminal of nmos transistors. Use the metal2 for the vertical wiring. To use
metal2, metal1 of the drain must be connected to the metal2. Use the via contact m2_m1 for this.
Now make an input signal connection, assume the signal come through metal1. We can use metal1 to poly contact.
Now make an output signal connection, assume the signal goes out through metal1. We can use metal1 to metal2 via contact.
Now we need to create four pins: ain, zout, vdd!, and gnd! pins.
To place the pin, first select the material metal1 from the LSW window. Then follow the instruction shown at the bottom of the layout
editor window.
Next, create vdd! and gnd! pins for the power supply.
Now the layout of the inverter must be verified. First we will extract the circuit from the layout. Then the extracted circ uit will be
simulated with hspice for correct functioning and signal timing. Then we will verify the consistency of the layout circuit with the
schematic circuit using the LVS tool.
Step 3
Once the circuit has been extracted from the layout, open the extracted file:
Go to the Library Manager window, select hw0chip (for my case) library -> select inv cell -> select extracted view. Double click on
the extracted view to open the extracted view in another layout editor window. You may want to take a detailed look at the extracted
view of your inverter layout design. You can also click on the materials to highlight all of the materials that are electric ally connected.
There should be also some parasitic capacitors, extracted from the layout design. The simulation of the extracted circuit will be more
accurate than the schematic circuit for the signal timing, because the additional consideration of the wire length and the layout area
reflected into the parasitic capacitances.
For the simulation, we need a netlist, A netlist can be generated from the extracted circuit. Similar to Section 4,
select Launch -> ADE L from the extracted view window.
VDD 5.0
CLK 5.0
RISE 0.1
FALL 0.1
ain
01010
..CL zout 0 10fF
You may use any text editor of your choice. One I use is gedit program. You can type:
% gedit LAYinv.hsp
&
hsp50
LAYinv
It will create LAYinv.sp file. Both LAYinv.s file and LAYinv.hsp file are combined into the LAYinv.sp file.
Now hspice simulate your schematic netlist using the following command:
%
hspice
LAYinv.sp
Be sure to read the hspice output, it must say it concluded and not aborted.
Once the hspice is successfully completed, you can see the input and output waveform. Type the following command to plot the
simulation output:
%
sc
LAYinv.tr0 &
Choose the LAYinv.tr0 from the Output View window of the SpiceCheck (sc) window and expand it. Then select ain and zout
signals, drag them to the WaveView window. You may explore other features of the SpiceCheck program to measure the signal
parameters. Be sure that the inverter circuit is properly working.
The signal propagation time, rise time, fall time may be different from the schematic circuit.
The output of the LVS report contains some useful information for your design. Especially when the LVS fails and the schematic and
the extracted circuits does NOT match, you may find useful clues from it.
Please try: first make a mistake in the layout of the inverter - make the nmos transistor drain not connected to zout by not drawing the
metal2 wire long enough. Extract the layout, and redo LVS.
After doing the LVS, click on Output and Error Display, observed the information. We could get six errors (actually they are all caused
by the disconnection mismatch). On the extracted view window, you can zoom-in to the problem place and find that the problem is
highlighted. Then, you can fix the problem.
One can use a rectangle to represent an inverter but we can improve the readability by using the proper inverter symbol. Replace the
rectangle representation of the inverter with the new drawing. So, first select the rectangle and delete. Move the new drawing to the
middle of the red box. The red box is the boundary of the symbol. Follow the figures below to complete the inverter symbol.
Later, when you use the inverter again, you will see the diagram shown below.
Select the Library. If the selection tab is not shown, drag the right widow boundary to the right side to enlarge it.
Finish wiring up the transistors, place power supply components vdd and gnd, and add the input and output pins to complete the circuit
schematic diagram. Do click on the Check and Save button. And be sure to check the CIW window, must see the 'no error' status.
The complete 2-input NAND gate circuit schematic is shown below.
Next, create the symbol view of the 2-input NAND gate. On the nand2 schematic editor window,
click Create -> Cellview -> From Cellview.
Next create the layout of the 2-input NAND gate. Click on the Library Manager window, File -> New -> Cellview.
Complete the 2-input NAND gate layout. Inputs are the two poly lines of the transistor gates. The inputs ain and bin are connected
with metal1 wires for easy access. Minimum two metal1 to poly contacts are used. The pmos and nmos transistor drains are
connected with metal2 wire, connected to the output pin zout. Again minimum two metal1 to metal2 contacts are used. Be sure to add
vdd! and gnd! pins also on the layout. Be sure to run the DRC and verify 'Total errors found: 0' status. Then extract the circuit from
the layout. And then do the LVS check. Once the nand2 passed with LVS, do create the netlist from the extraction and simulate.
Now the inverter and the 2-input NAND gates are completely designed and checked. We can design 2-input AND gate next, combining
the inverter and NAND gate.
11. Create AND gate cell
On the Library Manager window, click File -> New -> Cellview.
Finish wiring, with input and output pins. Do 'Check and Save', and be sure the 'no errors' status.
Just for the testing and analysis, an extra pin 'xout' is added
Once the 2-input AND gate schematic is complete and tested (with hspice simulation - function verification), we are ready to design the
layout. This time, we will generate the 2-input AND gate layout from the schematic since we have completed the 2-input NAND gate
layout and the inverter layout. On the Schematic Editor window, click Launch -> Layout XL. We will see the XL Editor for the
schematic (left) and XL Editor (right) for the layout. On the layout editor, the layout instance of 2-input NAND gate, the layout instance
of inverter, and the signal pins will be shown. We can reposition the two layouts and manually connect the signals, and place the pi ns
on the layout. The following sequence of figures will illustrate the layout design of the 2-input AND gate.
The XL Editor: left is the schematic editor and right is the layout editor. Click the 'Generate All From Source' button on the lower left
of the layout editor window.
Next, move the nand2 gate. The signal connection wires will follow the layout instance move as shown below.
Place the nand2 layout and inverter layout near each other and delete the area marker. Then set the Display Option.
Move the inverter layout over to the left, overlapping the NAND gate layout, make the overall AND gate layout as small as possible
without any DRC error.
Connect the NAND gate output to inverter input. And move each of the signal pins to the designated location following the orange
string. The final placement of the pins should eliminate any trace of the orange indicator string.
Completed 2-input AND gate layout, composed of two subcells - NAND and inverter.
And for final AND gate layout verification and characterization, we will do the hspice simulation.
From: 0 To: 20
Step2.
Create a instance of pmos transistor.
1. Select Create->instance. Then click on the Browse.. button. Wait for the Library Browser to pop up.
2. In the Library Browser, Choose NCSU_TechLib_ami06, select the cell name pmos, and select layout view.
3. Place the pmos in the layout editor and get the following layout:
Step5.
Draw the Vdd next to the nmos as in the previous step.
Step6.
1. Connect the source of p-transistor to the well-contact using the metal 1 layer.
2. Connect the source of n-transistor to the substrate-contact with the metal 1.
3. Add a contact to the gate (poly)
Figure 5 DRC
If your design has violated any design rules, DRC will reports the errors in the CIW.
Errors are indicated by the markers (white color) on the circuit. You may then proceed to correcting the errors according to the design
rules. For huge layouts, the marker might not be easily located. To find markers, choose Verify -> Markers -> Find in layout window.
A pop-up menu will appear. Select on the Zoom to Markers box.
Click on the Apply button and Cadence will zoom in to the errors or warnings as desired.
*****