VLSI Lab Manual

VLSI LAB MANUAL (10ECL77)

Subject Code

: 10ECL77

IA Marks

: 25

No. OF Practical Hrs/Week

: 03

Exam Hours

: 03

Total no. OF Practical Hrs.

: 42

Exam Marks

: 50

PART A
DIGITAL DESIGN
ASIC-DIGITAL DESIGN FLOW
1. Write Verilog Code for the following circuits and their Test Bench for verification, observe
the waveform and synthesis the code with technological library with given Constraints*. Do the
initial timing verification with gate level simulation.
i.
ii.

An inverter
A Buffer

iii.

Transmission Gate

iv.

Basic/universal gates

v.

Flip flop -RS, D, JK, T

vi.

Serial & Parallel adder

vii.

4-bit counter [Synchronous and Asynchronous counter]

viii.

Successive approximation register [SAR]

* An appropriate constraint should be given

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PART - B
ANALOG DESIGN
Analog Design Flow
1. Design an Inverter with given specifications*, completing the design flow mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis
ii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design
e. Verify & Optimize Time, Power and Area to the given constraint***

2. Design the following circuits with given specifications*, completing the design flow
mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
i) A Single Stage differential amplifier
ii) Common source and Common Drain amplifier

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3. Design an op-amp with given specification* using given differential amplifier Common
source and Common Drain amplifier in library** and completing the design flow mentioned
below:
a. Draw the schematic and verify the following
i) DC Analysis
ii). AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.

4. Design a 4 bit R-2R based DAC for the given specification and completing the design flow
mentioned using given op-amp in the library**.
a. Draw the schematic and verify the following
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check OF LVS
d. Extract RC and back annotate the same and verify the Design.

5. For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and
verify the functionality by completing ASIC Design FLOW.

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PART A
DIGITAL DESIGN
Steps to use Xilinx tool:
Start the Xilinx Project Navigator by using the desktop shortcut or by using the
Start

Programs

Xilinx ISE

Project Navigator.

In the Project Navigator window go to FILE

verilog module and give the name inverter.v

Select devices General purpose

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Spartan 3

New project

Click on new source

Define ports Finish

ISE simulator verilog

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In the create new source window select source type as verilog module give file name

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assign inputs and outputs

click next

finish yes next

next finish

Double click on source file complete the verilog code for inverter
Check syntax, and remove errors if present
Simulate the design using ISE Simulator Highlight inverter.v file in the Sources in
Project window. To run the Behavioral Simulation, Click on the symbol of FPGA device
and then right click Click on new source Click on verilog text fixture Give file name
with _tb

finish

Generate test bench file after initial begin assign value for inputs
behavioral model

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Click on simulate

see the output.

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INVERTER
1. Write Verilog Code of an inverter circuits and their Test Bench for verification
Objective:
To design an inverter in verilog using xilinx tool and verify it on ISE simulator
Tools : Xilinx ISE simulator .
Symbol and truth table:

Design Description:
NOT gate, for example, will invert the data. NOT gate has 1 input and 1 output. Whatever
the value is at the input, the output will have the opposite value. If the input is a 1, the output is a 0.
If the input is a 0, the output is a 1. B = ~A
Waveform:

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VERILOG CODE
//Data flow model
module in1(a, b);
input a;

output b;

assign b=~a;
endmodule
// Behavioural model
module in1(a, b);
input a;
output reg b;
always @(a)
begin
b=~a;
end
endmodule

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//Test bench structure

module iin_v;
reg a; // Inputs
wire b; // Outputs
// Instantiate the Unit Under Test (UUT)
in1 uut (.a(a),.b(b) );
initial begin
a = 0;
#100; // Wait 100 ns for global reset to finish
// Add stimulus here
a = 1;
#100; // Wait 100 ns for global reset to finish
end
endmodule
Waveform:

Conclusion: Design of an inverter is done using xilinx tool and is verified.

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BUFFER
2. Write Verilog Code of a Buffer circuits and their Test Bench for verification
Objective:
To design a buffer in verilog using xilinx tool and verify it on ISE simulator.
Tools : Xilinx ISE simulator .
Symbol and Truth table:

Design Description:
If we were to connect two inverter gates together so that the output of one fed into the
input of another, the two inversion functions would "cancel" each other out so that there would
be no inversion from input to final output: For this purpose, a special logic gate called a buffer is
manufactured to perform the same function as two inverters. Its symbol is simply a triangle, with
no inverting "bubble" on the output terminal: B = A

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Waveform:

// VERILOG CODE:
//Data flow model
module buffer(a, b);
input a;
output b;
assign b=a;
endmodule
// Behavioural
module buffer (a, b);
input a;
output reg b;
always @(a)
begin
b=a;
end
endmodule

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//Test bench structure

module iin_v;
reg a; // Inputs
wire b; // Outputs
// Instantiate the Unit Under Test (UUT)
in1 uut (.a(a),.b(b) );
initial begin
a = 0;

#100;

a = 1; #100;
end
endmodule
Waveform:

Conclusion: Design of a buffer in xilinx tool and is verified according to the truth Table.

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Transmission Gate
3. Write Verilog Code of a transmission gate circuits and their Test Bench for verification
Objective:
To design a transmission gate in verilog using xilinx tool and verify it on ISE simulator.
Tools : Xilinx ISE simulator .
Circuit Diagram and Truth table:

A(Select)
0
1
1

IN
X
0
1

OUT
X
0
1

Design Description:
Transmission gate is an electronic element. It is a good non-mechanical relay, built
with CMOS technology. It can be used to simplify digital logic circuits or to switch analog
signals, and so is also known as an analog gate, analogue switch or electronic relay depending on
its use. It is made by the parallel combination of an nMOS and a pMOS transistor with the input
at the gate of one transistor being complementary to the input at the gate of the other transistor.

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//VERILOG CODE
module transmission_gate(A,IN,OUT);
input A,IN;
output OUT;
wire Abar;
assign Abar=~A;
pmos(OUT,Abar,IN);
nmos(OUT,A,IN);
endmodule

//Test bench code

module tg_tb_v;
reg A; reg IN; // Inputs
wire OUT; // Outputs
// Instantiate the Unit Under Test (UUT)
transmission_gate uut (
.A(A),
.IN(IN),
.OUT(OUT) );
initial begin
// Initialize Inputs
A = 0; IN = 0;#100;
A = 0; IN = 1;#100;
A = 1; IN = 0;#100;
A = 1; IN = 1;#100;
end
endmodule

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Waveform:

Conclusion: Design of a transmission gate in xilinx tool and is verified according to the truth
Table.

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BASIC GATES
4. Write Verilog Code of a Basic gates circuits and their Test Bench for verification.
Objective:
To design a basic gates in verilog using xilinx tool and verify it on ISE simulator.
Tools : Xilinx ISE simulator .
AND GATE:

Symbol and Truth table of AND gate

Design Description:
The output of an AND gate is only equal to 1 if both inputs (A AND B in this case) are
equal to 1. Otherwise the output is equal to 0. The above picture shows a two input AND gate,
but an AND gate can have many inputs. In any case, no matter how many inputs it has, the
output is only equal to 1 if all the inputs are equal to 1, otherwise the output is 0.
The equation of an AND gate is: C = A & B
Waveform:

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OR GATE:

Symbol and Truth table of OR gate

Design Description:
The output of an OR gate is equal to 1 if either input (A OR B in this case) is equal to
one. If neither input is equal to 1, the output is equal to zero. Again, the above picture shows a
two input OR gate, but an OR gate can have as many inputs as you like. The output will be equal
to 1 if any of the inputs is equal to 1.
The equation of an OR gate is: C = A + B
Waveform:

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EX-OR GATE:

Symbol and Truth table of XOR gate:

Design Description:
The output of an XOR gate is equal to 1 if either input (A or B in this case) is equal to
one, but equal to zero if both inputs are equal to zero or if both inputs are equal to 1. This is the
difference between an OR gate and an XOR gate, an OR gates output will equal 1 if both inputs
are equal to 1.
The equation OF an XOR gate is: C = A ^ B
Waveform:

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NAND GATE:

Symbol and Truth table of NAND gate:

Design Description:
A variation on the idea of the AND gate is called the NAND gate. The word "NAND" is
a verbal contraction of the words NOT and AND. Essentially, a NAND gate behaves the same as
an AND gate with a NOT (inverter) gate connected to the output terminal. To symbolize this
output signal inversion, the NAND gate symbol has a bubble on the output line. The truth table
for a NAND gate is as one might expect, exactly opposite as that of an AND gate:
As with AND gates, NAND gates are made with more than two inputs. In such cases, the
same general principle applies: the output will be "low" (0) if and only if all inputs are "high"
(1). If any input is "low" (0), the output will go "high" (1).
The equation of an XOR gate is: C = ~(A &B)

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Waveform:

NOR GATE:

Symbol and Truth table of NOR gate:

Design Description:
A variation on the idea of the OR gate is called the NOR gate. The word "NOR" is a
verbal contraction of the words NOT and OR. Essentially, a NOR gate behaves the same as an
OR gate with a NOT (inverter) gate connected to the output terminal. To symbolize this output
signal inversion, the NOR gate symbol has a bubble on the output line. The truth table for a NOR
gate is as one might expect, exactly opposite as that of an OR gate:
As with OR gates, NOR gates are made with more than two inputs. In such cases, the
same general principle applies: the output will be "low" (0) if any inputs are "high" (1). If both
the inputs is "low" (0), the output will go "high" (1).

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Waveform:

VERILOG CODE
//Data flow model
module gat(c,d,a,o,na,no,x);
input c,d ;
output a,o,x,no,na;
assign o=(c|d); //o -> or gate output
assign no=~(c|d);

// no-> nor gate output

assign a=(c&d); // a-> and gate output

assign na=~(c&d); // na-> nand gate output
assign x=(c^d); // x-> xor gate output
endmodule

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//Test bench structure

module basi_v;
reg c;reg d;
wire a;

// Inputs

wire o; wire na; wire no; wire x;

// Outputs

// Instantiate the Unit Under Test (UUT)

gat uut (.c(c),

.d(d), .a(a), .o(o), .na(na),

.no(no),

.x(x) );

initial begin
c = 0;

d = 0;#100;

c = 0;

d = 1;#100;

c = 1;

d = 0;#100;

c = 1;

d = 1;#100;

end
endmodule
Waveform:

Conclusion: Design of Basic gates in xilinx tool and is verified according to the truth Table.

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FLIP FLOPS
5. Write Verilog Code of Flip flops circuits and their Test Bench for verification
Objective:
To design Flip flops in verilog using xilinx tool and verify it on ISE simulator
Tools : Xilinx ISE simulator .

i) D FLIPFLOP

Symbol and truth table

Design Description:
D Flip Flop has two inputs, the clock and the D input, and one output, Q. In the picture
D is connected to the node A, and Q is connected to the node B, so these are essentially names OF
the same thing. As can be seen in the truth table, the output is equal to the input on the rising edge
OF the clock. If there is no rising clock edge, the output will remain in its current state.
Waveform:

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// VERILOG CODE
module d_ff( d, clk, q, q_bar);
input d, clk;
output q, q_bar;
reg q;
reg q_bar;
always @ (posedge clk)
begin
q <= d;
q_bar <= !d;
end
endmodule
//Test bench structure
module cc_v;
reg d;

reg clk; // Inputs

wire q; wire q_bar; // Outputs

// Instantiate the Unit Under Test (UUT)
d_ff uut (.d(d), .clk(clk), .q(q), .q_bar(q_bar) );
initial begin
d = 0;

clk = 0; #100;// Initialization of Inputs

d = 0;

clk = 1; #100;

d = 1;

clk = 1; #100;

d = 1;

clk = 0; #100;

end
endmodule

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Waveform:

ii) T FLIPFLOP

Symbol and truth table

// VERILOG CODE
module t_ff ( t, clk, q, q_bar);
input t, clk;
output q, q_bar;
reg q;
reg q_bar;
always @ (posedge clk)
begin
q = ~t;
q_bar = ~q;
end
endmodule
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//Test bench structure

module cc_v;
reg t; reg clk;

// Inputs

wire q;

// Outputs

wire q_bar;

// Instantiate the Unit Under Test (UUT)

t_ff uut ( .t(t),

.clk(clk), .q(q), .q_bar(q_bar) );

initial begin
t = 0;clk = 0;

#100; // Initialization of Inputs

t = 0;clk = 1;

#100;

t = 1;clk = 1; #100
t = 1;clk = 0; #100;
end
endmodule
Waveform:

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iii) SR FLIPFLOP:

Symbol and truth table

Design Description:
An SR Flip Flop is an arrangement of logic gates that maintains a stable output even after the
inputs are turned off. This simple flip flop circuit has a set input (S) and a reset input (R). The set
input causes the output of 0 (top output) and 1 (bottom output). The reset input causes the opposite to
happen (top = 1, bottom =0). Once the outputs are established, the wiring of the circuit is maintained
until S or R go high, or power is turned of to the circuit.
Waveform:

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// VERILOG CODE
module sr_ff(clk,s,r,q,qb);
input clk,s,r;
output rer q,qb;
always @(clk,s,r)
begin
if(clk==1)
begin
if(s==0 & r==1)
begin
q=0; qb=~q;
end
else if(s==1 & r==0)
begin
q=1; qb=~q;
end
else if(s==0 & r==0)
begin
q=q; qb=~q;
end
else if(s==1 & r==1)
begin
q=1'bz; qb= 1'bz;
end
end
end
endmodule

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//Test bench structure

module rsff_v;
reg clk ;reg s;

reg r; // Inputs

wire q; wire qb; // Outputs

// Instantiate the Unit Under Test (UUT)
ff uut (

.clk(clk), .s(s), .r(r),

.q(q),

.qb(qb) );

initial begin
clk = 0; s = 1;

r = 0;

#100; // Initialization of the Inputs

clk = 1; s = 0;

r = 1;

#100;

clk = 1; s = 1;

r = 0;

#100;

clk = 1; s = 0;

r = 0;

#100;

clk = 1; s = 1;

r = 1;

#100;

end
endmodule
Waveform:

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IV) JK FLIP FLOP:

Symbol and truth table:

Design Description:
The J-K flip-flop is perhaps the most widely used type of flip-flop. Its function is
identical to that of the S-R flip flop in the SET, RESET and HOLD conditions of operation. The
difference is that the J-K flip-flop does not have any invalid states. The logic symbol for the J-K
flip-flop is presented in Figure 3-8 and its corresponding truth table is listed in Table 3-5. Notice
that for J=1 and K=1 the output toggles, that is to say that the output at time t is complemented at
time t+1.
Waveform:

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//Verilog code
module jk_ff(clk,j,k,q,qb);
input clk, j, k;
output q,qb;
reg q,qb;
always @(clk,j,k)
begin
if(clk==1)
begin
if(j==0 & k==1)
begin
q=0; qb=~q;
end
else if(j==1 & k==0)
begin
q=1; qb=~q;
end
else if(j==0 & k==0)

begin
q=q; qb=~q;
end
else if(j==1 & k==1)
q=~q; qb=~q;
end
end
endmodule

//Test bench structure

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//Test Bench code

module jk_v;
reg clk, j, k ;

// Inputs

wire q, qb; // Outputs

// Instantiate the Unit Under Test (UUT)
jk_ff uut (.clk(clk), .j(j), .k(k), .q(q),

.qb(qb)

);

initial begin
clk = 0; j = 0;

k = 0;

#100;

clk = 1; j = 1;

k = 0;

#100;

clk = 1; j = 0;

k = 1;

#100;

clk = 1; j = 0;

k = 0;

#100;

clk = 1; j = 1;

k = 1;

#100;

end
endmodule
Waveform:

Conclusion: Design of Flipflops(D,T,SR,JK) in xilinx tool and is verified according to the truth
Table.

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PARALLEL ADDER
6. Write Verilog Code of Parallel adder circuits and their Test Bench for verification
Objective:
To design parallel adder in verilog using xilinx tool and verify it on ISE simulator
Tools : Xilinx ISE simulator .

Block diagram of parallel adder.

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Design Description:
Parallel adders are digital circuits that compute the addition of variable
binary strings of equivalent or different size in parallel.
A number of full adders may be added to the ripple carry adder or ripple carry adders of different
sizes may be cascaded in order to accommodate binary vector strings of larger sizes. For an n-bit
parallel adder, it requires n computational elements (FA).
It is composed of four full adders. The augends bits of x are added to the addend bits of
y respectfully of their binary position Each bit 6 addition creates a sum and a carry out. The carry
out is then transmitted to the carry in of the next higher-order bit. The final result creates a sum
of four bits plus a carry out (c4).
// VERILOG CODE
module padd(x,y, c, sum, cout);
input [3:0] x,y;
input c;
output [3:0] sum;
output cout;
FA stage0(x[0],y[0],c,sum[0],c1);
FA stage1(x[1],y[1],c1, sum[1],c2);
FA stage2(x[2],y[2],c2, sum[2],c3);
FA stage3(x[3],y[3],c3,sum[3],cout);
endmodule
// Function of full Adder
module FA(a,b,cin, s,c0);
input a,b,cin;
output s,c0;
assign s=a^b^cin;
assign c0=(a&b)|(b&cin)|(cin&a);
endmodule

// Test bench code

module aaa_v;
reg [3:0] x; reg [3:0] y; reg c; // Inputs
wire [3:0] sum; wire cout; // Outputs
// Instantiate the Unit Under Test (UUT)
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padd uut (
.x(x),
.y(y),
.c(c),
.sum(sum),
.cout(cout)
);
initial begin
// Initialize Inputs
x = 4'b0101;
y = 4'b1100;
c = 0;
#100;
x = 4'b0001;
y = 4'b1011;
c = 1;
#100;
x = 4'b1011;
y = 4'b0101;
c = 0;
#100;
end
endmodule

Waveform:

Conclusion: Design of Parallel Adder in xilinx tool and is verified according to the truth Table.

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SERIAL ADDER
// VERILOG CODE
module fa(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
wire d,e,f;
xor(sum,a,b,c);
and(d,a,b);
and(e,b,c);
and(f,a,c);
or(carry,d,e,f);
endmodule

//TEST BENCH CODE

module fulladdt_b;
reg a;
reg b;
reg c;
wire sum;
wire carry;
fa uut ( .a(a), .b(b),.c(c),.sum(sum),.carry(carry) );

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initial begin
#10 a=1b0;b=1b0;c=1b0;
#10 a=1b0;b=1b0;c=1b1;
#10 a=1b0;b=1b1;c=1b0;
#10 a=1b0;b=1b1;c=1b1;
#10 a=1b1;b=1b0;c=1b0;
#10 a=1b1;b=1b0;c=1b1;
#10 a=1b1;b=1b1;c=1b0;
#10 a=1b1;b=1b1;c=1b1;
#10$stop;
end
endmodule

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COUNTER
7. Write Verilog Code of counter circuits and their Test Bench for verification
Objective:
To design counter in verilog using xilinx tool and verify it on ISE simulator
Tools : Xilinx ISE simulator .
Design Description:
In the 4-bit counter to the right, we are using edge-triggered master-slave
flip-flops similar to those in the Sequential portion of these pages. The output of each flipflop changes state on the falling edge (1-to-0 transition) of the T input.
The count held by this counter is read in the reverse order from the order in which the flip-flops
are triggered. Thus, output D is the high order of the count, while output A is the low order. The
binary count held by the counter is then DCBA, and runs from 0000 (decimal 0) to 1111
(decimal 15). The next clock pulse will cause the counter to try to increment to 10000
(decimal 16). However, that 1 bit is not held by any flip-flop and is therefore lost. As a result,
the counter actually reverts to 0000, and the count begins again

Up Counter:
Verilog code
module upcountermod(clk, clear, q);
input clk;
input clear;
output [3:0] q;
reg [3:0] q;
always@(posedge clear or posedge clk)
begin
if(clear)
q <=4b0000;
else
q <= q+1b1;
end
endmodule

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TEST BENCH
module upcountert_v;
reg clk;
reg clear;
wire [3:0] q;
upcountermod uut ( .clk(clk), .clear(clear),.q(q));
initial begin
clk = 0;
clear = 0;
#5 clear=1b1;
#5 clear=1b0;
end
always #5 clk=~clk;
initial #200 $stop;
endmodule

Down counter:
//Verilog code

module downcountermod(clk, clear, q);

input clk;
input clear;
output [3:0] q;
reg [3:0] q;
always@(posedge clear or posedge clk)
begin
if(clear)
q <=4b1111;
else
q <= q-1b1;
end
endmodule
TEST BENCH
module downcountert_v;
reg clk;
reg clear;
wire [3:0] q;
downcountermod uut (.clk(clk), .clear(clear),.q(q));
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initial begin
clk = 0;
clear = 0;
#5 clear=1b1;
#5 clear=1b0;
end
always #5 clk=~clk;
initial #200 $stop;
endmodule

Up-Down Counter
//Verilog code:
module updowncountermod(clk, clear, updown, q);
input clk;
input clear;
input updown;
output [3:0] q;
reg [3:0] q;
always@(posedge clear or posedge clk)
begin
if(clear)
q <=4b0000;
else if(updown)
q <= q+1b1;
else
q <= q-1b1;
end
endmodule
//TEST BENCH
module updowncountert_b;
reg clk;
reg clear;
reg updown;
wire [3:0] q;
updowncountermod uut (.clk(clk),.clear(clear), .updown(updown), .q(q) );

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initial begin
clk = 0;
clear = 0;
updown = 0;
#5 clear=1b1;
#5 clear=1b0;
#100 updown=1b1;
end
always #5 clk=~clk;
initial #150 $stop;
endmodule

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Asynchronouscounter
//Verilog code:
module asynchronouscountermod(clk, clear, q);
input clk;
input clear;
output [3:0] q;
reg [3:0] q;
always @(negedge clk or posedge clear)
q[0]<=~q[0];
always @(negedge q[0] or posedge clear)
q[1]<=~q[1];
always @(negedge q[1] or posedge clear)
q[2]<=~q[2];
always @(negedge q[2] or posedge clear)
begin
if(clear)
q <=4b0000;
else
q[3]<=~q[3];
end
endmodule

TEST BENCH
module asynchronouscountert_b;
reg clk;
reg clear;
wire [3:0] q;
asynchronouscountermod uut (.clk(clk),.clear(clear),.q(q) );
initial begin
clk = 0;
clear = 0;
#5 clear=1b1;
#5 clear=1b0;
end
always #5 clk=~clk;
initial #200 $stop;
endmodule

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SUCESSIVE APPROXIMATION ADC

8. Write Verilog Code of A successive approximation ADC circuits and their Test Bench
for verification
Objective:
To design SAR in verilog using xilinx tool and verify it on ISE simulator
Tools : Xilinx ISE simulator .
Circuit Diagram: successive approximation ADC:

Design Description:
A successive approximation ADC is a type of analog-to-digital converter that converts a
continuous analog waveform into a discrete digital representation via a binary search through all
possible quantization levels before finally converging upon a digital output for each conversion
The successive approximation Analog to digital converter circuit typically consists of four chief
subcircuits:
1. A sample and hold circuit to acquire the input voltage (Vin).
2. An analog voltage comparator that compares Vin to the output of the
internal DAC and outputs the result of the comparison to the successive
approximation register (SAR).

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3. A successive approximation register subcircuit designed to supply an approximate

digital code of Vin to the internal DAC.
4. An internal reference DAC that supplies the comparator with an analog voltage
equivalent of the digital code output of the SAR for comparison with Vin.
The successive approximation register is initialized so that the most significant bit (MSB) is
equal to a digital 1. This code is fed into the DAC, which then supplies the analog equivalent of
this digital code (Vref/2) into the comparator circuit for comparison with the sampled input
voltage. If this analog voltage exceeds Vin the comparator causes the SAR to reset this bit;
otherwise, the bit is left a 1. Then the next bit is set to 1 and the same test is done, continuing
this binary search until every bit in the SAR has been tested. The resulting code is the digital
approximation of the sampled input voltage and is finally output by the DAC at the end of the
conversion (EOC).

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PART B
ANALOG DESIGN
Analog Design Flow using Electric 9.04 - tool
Design the circuits with given specifications*, completing the design flow mentioned below:
a. Draw the schematic and verify the
following i) DC Analysis
ii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design
e. Verify & Optimize Time, Power and Area to the given constraint***
This Lab will introduce you to the Analog VLSI system Lab using Electric -9.04 tool:
Its assumed that Electric (version 8.10 or later) and LTspice have been installed properly on your
computer. With this assumption all layout and simulation work will be done (saved) in C:/Electric
(where the Electric jar file resides). Ensure that you have increased the memory in your JVM as
instructed above.

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Next go to menu item Window -> Color Schemes -> White Background Colors
Using a white background will be useful in these tutorials so that ink is minimized if they are
printed out
Its often preferable to use a black background colors to ease the stress on your eyes ;-)
Adjust the sizes of the windows to fill the available space as seen below.

Well set Electric up for use in ON Semiconductors C5 process and fabrication through MOSIS.
This process has two layers of polysilicon to make a poly1-poly2 capacitor, 3 layers of metal, and a
hi-res layer to block the implant, and thus decrease in resistance, of poly2 to fabricate higher-value
(than what we would get with poly1) poly2 resistors.

This tutorial uses the MOSIS scalable CMOS (SCMOS) submicron design rules.
While the C5 process is an n-well process well still draw the p-well, which will be ignored during
fabrication, just to make the layouts more portable between processes.

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Next, go to File -> Preferences (or just hit the wrench/screwdriver menu icon) then Technology ->
Technology to get to the window seen below.
Change the information to match what is seen below.
Note that the Analog Technology is selected.
This selection shows the resistor and capacitor Nodes in the Component menu (discussed shortly).

Next, the scale (lambda) for the C5 process is 300 nm using the MOSIS Scalable CMOS (mocmos
technology in Electric, see image above) submicron design rules.
To set the scale go to File -> Preferences -> Technology -> Scale and set mocmos scale to 300 nm
as seen below.

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Press OK to exit.
Go to File -> Save Library As -> Lib_name.jelib
Next lets begin to draw the schematic of a CMOS inverter circuit.
Go to Cell -> New Cell and enter the cell name (inverter) and view (schematic) seen below.

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After selecting the Component tab on the left side of the window we get the following.
The library name and cell name are seen above the Components, Explorer (for looking at the cells
in your library), and Layers (useful in layouts to turn on/off the display of certain layers).

Next create a new cell, Cell -> New Cell (or just use Ctrl+N) called inv_20_10 (an inverter with a
PMOS having a width of 20 and an NMOS with a width of 10)
Ensure the schematic view is selected.

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Next paste the nMos Node copied above into this new cell and then fill the window (zoom in
around the added Node).
Select the nMos Node and use Ctrl+C or Edit -> to copy the Node to the clipboard.

Repeat the above set of steps for the pMos Node in the cell

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Since want the PMOSs width to be 20 change, by editing the pMos Nodes properties, 10 to 20 as
seen below.

Next turn the grid on and add the power symbol as seen below.

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Add the wire Arcs to wire the inverter together.
Remember to use the left mouse button to select a port on a Node and the RIGHT mouse button to make
an Arc connection. The connection to the power Node is found in the center of the Node.
Next add Off-Page Nodes as seen below.
These Nodes have ports on the left and right sides (it doesnt matter which one you connect to).

Next we want to Export the inverters input and output.

Use Export -> Create Export (or Ctrl+E) to export the input (select the left port on the input side as
seen below).
Repeat for the output Off-Page Node (the right side port of the right off-page Node).
The results are seen below. Hit F5 to check the schematic for errors.

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We are now ready to create an icon view for this schematic.

Go to the menu item View -> Make Icon View.
After filling the window we get the following.

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We need to change the icon so that it looks like an inverter.
In the schematic view an instance of the icon is placed.
We can open the icon view by double clicking on the name above or
by selecting this view and going to the menu Cell -> Down Hierarchy -> Down Hierarchy (or Ctrl+D)
Lets select the icon view in the drawing area and press Ctrl+D to get the following.

To go back up in the hierarchy we can use Ctrl+U or Cell -> Up Hierarchy -> Up Hierarchy
Press Ctrl+U now to go back up to the inverter schematic (the only cell using the icon view)
Select this view again and then Ctrl+D to back into the icon view (knowing can use the Explorer to move
between cells too)
Next select and delete the box/text to get the following.

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Our icon view is now complete.

Press Ctrl+U to go back up the schematic view of the inverter (or use the Explorer).

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Lets simulate the operation of this inverter.
Create a schematic call inverter_sim.

Next, turn off the grid and then place the icon into this schematic.
This can be done in two ways.
In the Component menu select Cell -> inv_20_10 or
in the Explorer click, and hold, on the cell you want to instantiate and drag it into the drawing area.
Use either method to place the inverter icon as seen below.

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Add wire Arcs to the inverters input and output.
Next, add SPICE code (under the Misc. arrowhead) to get the following.

Double click on the Arcs (or select and use Ctrl+I) to label the wires in and out as seen below.
Also, edit the SPICE text so that the text seen below is used (set to Multi-line text).

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Using the menu item Tools -> Simulation (Spice) -> Write Spice Deck gives the following LTspice
output (after selecting the in and out voltages).

Closing LTspice results in, again, after selecting the in and out voltages:

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Lets draw the layout of the inverter next. Create a layout view for the inverter.

Now there are three views in the inv_20_10 cell group: schematic, icon, and layout
Add the following Nodes to this cell.
Annotation text was added to help know what to place and where.

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Next select the pMos Node and set its SPICE model to PMOSand set the width to 20.
Next select the nMos Node and set its SPICE model to NMOS and set its width to 10.
Keep both MOSFETs lengths at 2.
Next set the x-size of both pAct Nodes to 20 and both nAct Nodes to 10.
Further set pWell and nWell x-sizes to 20.
Next add Arcs between transistors and active areas as seen below.

Move the active areas adjacent to the transistors. Move Annotation text for labeling too.

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Lets delete the Annotation text.
Next rotate the transistors and active areas and mov
e the devices into the positions seen below.
DRC the layout to ensure no errors are present.
Next connect: the two poly gates together, the metal on the right of the devices together, and the metals on
the left of the transistors up or down to the well connections as seen below. DRC your design

Add a poly1 to metal1 contact on the left and a metal1 Pin on the right as seen below.

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Connect the Pin and Contact up as seen below.
If the width of the poly1 isnt 2 after the Arc is placed simply select the Arc and change its width to 2.
DRC the layout to ensure no errors.
We are now ready to Export in, out, gnd, and vdd.
Select the pWell Node and then hit Ctrl+E as seen below.

Select this gnd Export and change its Text size to 5 as seen below.
Remember that using the Crtl+click is useful for cycling through the selections.
Also remember that both gnd and vdd exports must be lowercase to properly NCC with the corresponding
power and ground schematic Nodes.

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Next, select the metal1 Pin we placed a moment ago (you can only export Nodes, not Arcs, and the Pin is a
Node). Export this Pin as out to match the schematic view.
Again, change the size of the Text to 5 as seen below.
Repeat for vdd and in then DRC, NCC, and Well Check the layout.
There shouldnt be any errors.

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lets simulate this layout.

Create a cell named inverter_sim with a layout view.
In the Explorer Drag inv_20_10{lay} over into the drawing area as seen below.

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Notice how we cant see whats inside the cell but we can see the Exports.
With the cell selected use the eye and closed eye on the right side of the menu to toggle between showing
and not showing the contents of the cell.
With the cell selected edit the edit the cells properties (Ctrl+I), below.

Notice that you can de-select the Easy to Select feature and make the cell hard to select. This is useful
when the layout is complicated.
If a cell or layout is hard to select you can toggle the Special Select cursor (circled on the menu).
Using Pure layers, see menu item under the left Components menu tab, requires the use of Special Select.
Lets connect metal wires to the cell as seen below.
Next edit the properties of the wire Arcs so that they correspond to the names in the inverter_sim{sch}.
Next copy the SPICE code from inverter_sim{sch} into this layout view of the cell.
Change the size of the SPICE code to 3 as seen below.

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Its tough to see the wire Arc names so change their size to 5 (again Ctrl+click and Shift+click are always
useful) DRC, NCC, and Well Check the cell inverter_sim.
We get errors for both the NCC and the Well Checks.

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The problem lies in the fact that since we used vdd and gnd symbols in the schematic we have to export
them in the layout.
We cant simply name the Arcs vdd and gnd like we did above.
Delete the vdd and gnd names from the Arcs.
Next Export the left Pins on the top and bottom metal1 Arcs with names vdd and gnd as seen below (change
text size to 5 too).
Again, if you dont use lowercase vdd and gnd for the Exports the layout and schematic wont NCC without
errors (and the layout wont Well Check correctly)
Notice how the Exports could easily be mistaken for naming of Arcs. Its important to understand what we
just did.

Now the two cells DRC, NCC, and Well Check without errors.
Further, the layout view of this cell can now be simulated using SPICE

Repeat the same procedure for single stage amplifiers and for the operation amplifier with the layout rules.

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